24 files changed, 398 insertions, 129 deletions

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index e1c84ce097..999429e62b 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_QEMU) += qemu/
 obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
 obj-$(CONFIG_INTEL_QUARK) += quark/
 obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
+obj-$(CONFIG_INTEL_TANGIER) += tangier/
 obj-y += lapic.o ioapic.o
 obj-y += irq.o
 ifndef CONFIG_$(SPL_)X86_64
diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig
index 4e7d4a4e25..75dbbc27f1 100644
--- a/arch/x86/cpu/baytrail/Kconfig
+++ b/arch/x86/cpu/baytrail/Kconfig
@@ -7,7 +7,23 @@
 config INTEL_BAYTRAIL
 	bool
 	select HAVE_FSP if !EFI
-	imply ENV_IS_IN_SPI_FLASH
+	select ARCH_MISC_INIT if !EFI
+	imply HAVE_INTEL_ME if !EFI
+	imply ENABLE_MRC_CACHE
+	imply AHCI_PCI
+	imply ICH_SPI
+	imply INTEL_ICH6_GPIO
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply SCSI
+	imply SPI_FLASH
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
+	imply USB_XHCI_HCD
+	imply VIDEO_VESA
 
 if INTEL_BAYTRAIL
 config INTERNAL_UART
diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
index 55ed7de781..cbefdf871d 100644
--- a/arch/x86/cpu/baytrail/acpi.c
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -11,8 +11,6 @@
 #include <asm/acpi_s3.h>
 #include <asm/acpi_table.h>
 #include <asm/io.h>
-#include <asm/ioapic.h>
-#include <asm/mpspec.h>
 #include <asm/tables.h>
 #include <asm/arch/global_nvs.h>
 #include <asm/arch/iomap.h>
@@ -141,33 +139,6 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
 	header->checksum = table_compute_checksum(fadt, header->length);
 }
 
-static int acpi_create_madt_irq_overrides(u32 current)
-{
-	struct acpi_madt_irqoverride *irqovr;
-	u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
-	int length = 0;
-
-	irqovr = (void *)current;
-	length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
-
-	irqovr = (void *)(current + length);
-	length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
-
-	return length;
-}
-
-u32 acpi_fill_madt(u32 current)
-{
-	current += acpi_create_madt_lapics(current);
-
-	current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
-			io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
-
-	current += acpi_create_madt_irq_overrides(current);
-
-	return current;
-}
-
 void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
 {
 	struct udevice *dev;
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index 87ba849c1c..c58f6a86a8 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -11,18 +11,6 @@
 #include <asm/mrccache.h>
 #include <asm/post.h>
 
-static struct pci_device_id mmc_supported[] = {
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SDIO },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SD },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_EMMC2 },
-	{},
-};
-
-int cpu_mmc_init(bd_t *bis)
-{
-	return pci_mmc_init("ValleyView SDHCI", mmc_supported);
-}
-
 #ifndef CONFIG_EFI_APP
 int arch_cpu_init(void)
 {
diff --git a/arch/x86/cpu/broadwell/Kconfig b/arch/x86/cpu/broadwell/Kconfig
index 1ce3848be3..bc2dba2bd7 100644
--- a/arch/x86/cpu/broadwell/Kconfig
+++ b/arch/x86/cpu/broadwell/Kconfig
@@ -6,6 +6,17 @@
 config INTEL_BROADWELL
 	bool
 	select CACHE_MRC_BIN
+	select ARCH_EARLY_INIT_R
+	imply HAVE_INTEL_ME
+	imply ENABLE_MRC_CACHE
+	imply AHCI_PCI
+	imply ICH_SPI
+	imply INTEL_BROADWELL_GPIO
+	imply SCSI
+	imply SPI_FLASH
+	imply USB
+	imply USB_EHCI_HCD
+	imply VIDEO_BROADWELL_IGD
 
 if INTEL_BROADWELL
 
diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c
index 436c6c49c3..4fa4de3525 100644
--- a/arch/x86/cpu/broadwell/refcode.c
+++ b/arch/x86/cpu/broadwell/refcode.c
@@ -56,7 +56,17 @@ struct rmodule_header {
 	uint32_t padding[4];
 } __packed;
 
-int cpu_run_reference_code(void)
+/**
+ * cpu_run_reference_code() - Run the platform reference code
+ *
+ * Some platforms require a binary blob to be executed once SDRAM is
+ * available. This is used to set up various platform features, such as the
+ * platform controller hub (PCH). This function should be implemented by the
+ * CPU-specific code.
+ *
+ * @return 0 on success, -ve on failure
+ */
+static int cpu_run_reference_code(void)
 {
 	struct pei_data _pei_data __aligned(8);
 	struct pei_data *pei_data = &_pei_data;
@@ -111,3 +121,8 @@ int cpu_run_reference_code(void)
 
 	return 0;
 }
+
+int arch_early_init_r(void)
+{
+	return cpu_run_reference_code();
+}
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index 9820651931..60eb45f9d0 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -3,6 +3,19 @@ if TARGET_COREBOOT
 config SYS_COREBOOT
 	bool
 	default y
+	imply AHCI_PCI
+	imply E1000
+	imply ICH_SPI
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply SPI_FLASH
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
+	imply USB_XHCI_HCD
+	imply VIDEO_COREBOOT
 	imply CMD_CBFS
 	imply FS_CBFS
 
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 658b900f0b..df5ad13821 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -29,11 +29,6 @@ int arch_cpu_init(void)
 	return x86_cpu_init_f();
 }
 
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 int checkcpu(void)
 {
 	return 0;
@@ -90,8 +85,3 @@ int misc_init_r(void)
 {
 	return 0;
 }
-
-int arch_misc_init(void)
-{
-	return 0;
-}
diff --git a/arch/x86/cpu/efi/efi.c b/arch/x86/cpu/efi/efi.c
index 741613f615..d82147be47 100644
--- a/arch/x86/cpu/efi/efi.c
+++ b/arch/x86/cpu/efi/efi.c
@@ -13,11 +13,6 @@ int arch_cpu_init(void)
 	return 0;
 }
 
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 int checkcpu(void)
 {
 	return 0;
@@ -36,8 +31,3 @@ int misc_init_r(void)
 {
 	return 0;
 }
-
-int arch_misc_init(void)
-{
-	return 0;
-}
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index e23d01a08f..c214ea0efe 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -8,6 +8,16 @@
 config NORTHBRIDGE_INTEL_IVYBRIDGE
 	bool
 	select CACHE_MRC_BIN if HAVE_MRC
+	imply HAVE_INTEL_ME
+	imply ENABLE_MRC_CACHE
+	imply AHCI_PCI
+	imply ICH_SPI
+	imply INTEL_ICH6_GPIO
+	imply SCSI
+	imply SPI_FLASH
+	imply USB
+	imply USB_EHCI_HCD
+	imply VIDEO_VESA
 
 if NORTHBRIDGE_INTEL_IVYBRIDGE
 
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index 462b7c09dd..7febb8cf88 100644
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -236,7 +236,7 @@ static int bd82x6x_sata_probe(struct udevice *dev)
 		bd82x6x_sata_enable(dev);
 	else {
 		bd82x6x_sata_init(dev, pch);
-		ret = ahci_probe_scsi(dev);
+		ret = ahci_probe_scsi_pci(dev);
 		if (ret)
 			return ret;
 	}
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 643d804e35..1cdbe479fd 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -233,7 +233,6 @@ static int sdram_find(struct udevice *dev)
 	uint32_t tseg_base, uma_size, tolud;
 	uint64_t tom, me_base, touud;
 	uint64_t uma_memory_base = 0;
-	uint64_t uma_memory_size;
 	unsigned long long tomk;
 	uint16_t ggc;
 	u32 val;
@@ -298,7 +297,6 @@ static int sdram_find(struct udevice *dev)
 		tolud += uma_size << 10;
 		/* UMA starts at old TOLUD */
 		uma_memory_base = tomk * 1024ULL;
-		uma_memory_size = uma_size * 1024ULL;
 		debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
 	}
 
@@ -312,13 +310,11 @@ static int sdram_find(struct udevice *dev)
 		debug("%uM UMA", uma_size >> 10);
 		tomk -= uma_size;
 		uma_memory_base = tomk * 1024ULL;
-		uma_memory_size += uma_size * 1024ULL;
 
 		/* GTT Graphics Stolen Memory Size (GGMS) */
 		uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
 		tomk -= uma_size;
 		uma_memory_base = tomk * 1024ULL;
-		uma_memory_size += uma_size * 1024ULL;
 		debug(" and %uM GTT\n", uma_size >> 10);
 	}
 
@@ -327,7 +323,6 @@ static int sdram_find(struct udevice *dev)
 	uma_size = (uma_memory_base - tseg_base) >> 10;
 	tomk -= uma_size;
 	uma_memory_base = tomk * 1024ULL;
-	uma_memory_size += uma_size * 1024ULL;
 	debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
 
 	debug("Available memory below 4GB: %lluM\n", tomk >> 10);
diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig
index 6808c9a6b9..da378128fe 100644
--- a/arch/x86/cpu/qemu/Kconfig
+++ b/arch/x86/cpu/qemu/Kconfig
@@ -6,6 +6,13 @@
 
 config QEMU
 	bool
+	select ARCH_EARLY_INIT_R
+	imply AHCI_PCI
+	imply E1000
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
+	imply VIDEO_VESA
 
 if QEMU
 
diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig
index 163caac660..0ed724813d 100644
--- a/arch/x86/cpu/quark/Kconfig
+++ b/arch/x86/cpu/quark/Kconfig
@@ -7,6 +7,20 @@
 config INTEL_QUARK
 	bool
 	select HAVE_RMU
+	select ARCH_EARLY_INIT_R
+	select ARCH_MISC_INIT
+	imply ENABLE_MRC_CACHE
+	imply ETH_DESIGNWARE
+	imply ICH_SPI
+	imply INTEL_ICH6_GPIO
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply SPI_FLASH
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
 
 if INTEL_QUARK
 
diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c
index 3968f7a8bf..5717a620b5 100644
--- a/arch/x86/cpu/quark/acpi.c
+++ b/arch/x86/cpu/quark/acpi.c
@@ -6,8 +6,6 @@
 
 #include <common.h>
 #include <asm/acpi_table.h>
-#include <asm/ioapic.h>
-#include <asm/mpspec.h>
 #include <asm/tables.h>
 #include <asm/arch/global_nvs.h>
 #include <asm/arch/iomap.h>
@@ -136,33 +134,6 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
 	header->checksum = table_compute_checksum(fadt, header->length);
 }
 
-static int acpi_create_madt_irq_overrides(u32 current)
-{
-	struct acpi_madt_irqoverride *irqovr;
-	u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
-	int length = 0;
-
-	irqovr = (void *)current;
-	length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
-
-	irqovr = (void *)(current + length);
-	length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
-
-	return length;
-}
-
-u32 acpi_fill_madt(u32 current)
-{
-	current += acpi_create_madt_lapics(current);
-
-	current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
-			io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
-
-	current += acpi_create_madt_irq_overrides(current);
-
-	return current;
-}
-
 void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
 {
 	/* quark is a uni-processor */
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 0c2cea4ee9..c36a5892d5 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -16,11 +16,6 @@
 #include <asm/arch/msg_port.h>
 #include <asm/arch/quark.h>
 
-static struct pci_device_id mmc_supported[] = {
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
-	{},
-};
-
 static void quark_setup_mtrr(void)
 {
 	u32 base, mask;
@@ -328,11 +323,6 @@ int arch_early_init_r(void)
 	return 0;
 }
 
-int cpu_mmc_init(bd_t *bis)
-{
-	return pci_mmc_init("Quark SDHCI", mmc_supported);
-}
-
 int arch_misc_init(void)
 {
 #ifdef CONFIG_ENABLE_MRC_CACHE
diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
index 6136d75422..835de85268 100644
--- a/arch/x86/cpu/queensbay/Kconfig
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -8,6 +8,21 @@ config INTEL_QUEENSBAY
 	bool
 	select HAVE_FSP
 	select HAVE_CMC
+	select ARCH_EARLY_INIT_R
+	imply AHCI_PCI
+	imply ICH_SPI
+	imply INTEL_ICH6_GPIO
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply PCH_GBE
+	imply SCSI
+	imply SPI_FLASH
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
+	imply VIDEO_VESA
 
 if INTEL_QUEENSBAY
 
diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index af3ffad385..c0681995bd 100644
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -5,4 +5,4 @@
 #
 
 obj-y += fsp_configs.o irq.o
-obj-y += tnc.o topcliff.o
+obj-y += tnc.o
diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c
deleted file mode 100644
index b76dd7de69..0000000000
--- a/arch/x86/cpu/queensbay/topcliff.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mmc.h>
-#include <pci_ids.h>
-
-static struct pci_device_id mmc_supported[] = {
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
-	{},
-};
-
-int cpu_mmc_init(bd_t *bis)
-{
-	return pci_mmc_init("Topcliff SDHCI", mmc_supported);
-}
diff --git a/arch/x86/cpu/tangier/Kconfig b/arch/x86/cpu/tangier/Kconfig
new file mode 100644
index 0000000000..86a334047c
--- /dev/null
+++ b/arch/x86/cpu/tangier/Kconfig
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2017 Intel Corporation
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+config INTEL_TANGIER
+	bool
+	depends on INTEL_MID
+	imply INTEL_MID_SERIAL
+	imply MMC
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply MMC_SDHCI_TANGIER
+	imply TANGIER_WATCHDOG
+	imply USB
+	imply USB_DWC3
+
+config SYS_CAR_ADDR
+	hex
+	default 0x19200000
+
+config SYS_CAR_SIZE
+	hex
+	default 0x4000
+	help
+	  Space in bytes in eSRAM used as Cache-As-RAM (CAR).
+	  Note this size must not exceed eSRAM's total size.
+
+config SYS_USB_OTG_BASE
+	hex
+	default 0xf9100000
diff --git a/arch/x86/cpu/tangier/Makefile b/arch/x86/cpu/tangier/Makefile
new file mode 100644
index 0000000000..d146b3f5c2
--- /dev/null
+++ b/arch/x86/cpu/tangier/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017 Intel Corporation
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += car.o tangier.o sdram.o
diff --git a/arch/x86/cpu/tangier/car.S b/arch/x86/cpu/tangier/car.S
new file mode 100644
index 0000000000..6982106c19
--- /dev/null
+++ b/arch/x86/cpu/tangier/car.S
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010-2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.section .text
+
+.globl car_init
+car_init:
+	jmp	car_init_ret
diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c
new file mode 100644
index 0000000000..5743077431
--- /dev/null
+++ b/arch/x86/cpu/tangier/sdram.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/e820.h>
+#include <asm/global_data.h>
+#include <asm/sfi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * SFI tables are part of the first stage bootloader.
+ *
+ * U-Boot finds the System Table by searching 16-byte boundaries between
+ * physical address 0x000E0000 and 0x000FFFFF. U-Boot shall search this region
+ * starting at the low address and shall stop searching when the 1st valid SFI
+ * System Table is found.
+ */
+#define SFI_BASE_ADDR		0x000E0000
+#define SFI_LENGTH		0x00020000
+#define SFI_TABLE_LENGTH	16
+
+static int sfi_table_check(struct sfi_table_header *sbh)
+{
+	char chksum = 0;
+	char *pos = (char *)sbh;
+	u32 i;
+
+	if (sbh->len < SFI_TABLE_LENGTH)
+		return -ENXIO;
+
+	if (sbh->len > SFI_LENGTH)
+		return -ENXIO;
+
+	for (i = 0; i < sbh->len; i++)
+		chksum += *pos++;
+
+	if (chksum)
+		error("sfi: Invalid checksum\n");
+
+	/* Checksum is OK if zero */
+	return chksum ? -EILSEQ : 0;
+}
+
+static int sfi_table_is_type(struct sfi_table_header *sbh, const char *signature)
+{
+	return !strncmp(sbh->sig, signature, SFI_SIGNATURE_SIZE) &&
+	       !sfi_table_check(sbh);
+}
+
+static struct sfi_table_simple *sfi_get_table_by_sig(unsigned long addr,
+						     const char *signature)
+{
+	struct sfi_table_simple *sb;
+	u32 i;
+
+	for (i = 0; i < SFI_LENGTH; i += SFI_TABLE_LENGTH) {
+		sb = (struct sfi_table_simple *)(addr + i);
+		if (sfi_table_is_type(&sb->header, signature))
+			return sb;
+	}
+
+	return NULL;
+}
+
+static struct sfi_table_simple *sfi_search_mmap(void)
+{
+	struct sfi_table_header *sbh;
+	struct sfi_table_simple *sb;
+	u32 sys_entry_cnt;
+	u32 i;
+
+	/* Find SYST table */
+	sb = sfi_get_table_by_sig(SFI_BASE_ADDR, SFI_SIG_SYST);
+	if (!sb) {
+		error("sfi: failed to locate SYST table\n");
+		return NULL;
+	}
+
+	sys_entry_cnt = (sb->header.len - sizeof(*sbh)) / 8;
+
+	/* Search through each SYST entry for MMAP table */
+	for (i = 0; i < sys_entry_cnt; i++) {
+		sbh = (struct sfi_table_header *)(unsigned long)sb->pentry[i];
+
+		if (sfi_table_is_type(sbh, SFI_SIG_MMAP))
+			return (struct sfi_table_simple *)sbh;
+	}
+
+	error("sfi: failed to locate SFI MMAP table\n");
+	return NULL;
+}
+
+#define sfi_for_each_mentry(i, sb, mentry)				\
+	for (i = 0, mentry = (struct sfi_mem_entry *)sb->pentry;	\
+	     i < SFI_GET_NUM_ENTRIES(sb, struct sfi_mem_entry);		\
+	     i++, mentry++)						\
+
+static unsigned sfi_setup_e820(unsigned max_entries, struct e820entry *entries)
+{
+	struct sfi_table_simple *sb;
+	struct sfi_mem_entry *mentry;
+	unsigned long long start, end, size;
+	int type, total = 0;
+	u32 i;
+
+	sb = sfi_search_mmap();
+	if (!sb)
+		return 0;
+
+	sfi_for_each_mentry(i, sb, mentry) {
+		start = mentry->phys_start;
+		size = mentry->pages << 12;
+		end = start + size;
+
+		if (start > end)
+			continue;
+
+		/* translate SFI mmap type to E820 map type */
+		switch (mentry->type) {
+		case SFI_MEM_CONV:
+			type = E820_RAM;
+			break;
+		case SFI_MEM_UNUSABLE:
+		case SFI_RUNTIME_SERVICE_DATA:
+			continue;
+		default:
+			type = E820_RESERVED;
+		}
+
+		if (total == E820MAX)
+			break;
+		entries[total].addr = start;
+		entries[total].size = size;
+		entries[total].type = type;
+
+		total++;
+	}
+
+	return total;
+}
+
+static int sfi_get_bank_size(void)
+{
+	struct sfi_table_simple *sb;
+	struct sfi_mem_entry *mentry;
+	int bank = 0;
+	u32 i;
+
+	sb = sfi_search_mmap();
+	if (!sb)
+		return 0;
+
+	sfi_for_each_mentry(i, sb, mentry) {
+		if (mentry->type != SFI_MEM_CONV)
+			continue;
+
+		gd->bd->bi_dram[bank].start = mentry->phys_start;
+		gd->bd->bi_dram[bank].size = mentry->pages << 12;
+		bank++;
+	}
+
+	return bank;
+}
+
+static phys_size_t sfi_get_ram_size(void)
+{
+	struct sfi_table_simple *sb;
+	struct sfi_mem_entry *mentry;
+	phys_size_t ram = 0;
+	u32 i;
+
+	sb = sfi_search_mmap();
+	if (!sb)
+		return 0;
+
+	sfi_for_each_mentry(i, sb, mentry) {
+		if (mentry->type != SFI_MEM_CONV)
+			continue;
+
+		ram += mentry->pages << 12;
+	}
+
+	debug("sfi: RAM size %llu\n", ram);
+	return ram;
+}
+
+unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
+{
+	return sfi_setup_e820(max_entries, entries);
+}
+
+int dram_init_banksize(void)
+{
+	sfi_get_bank_size();
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = sfi_get_ram_size();
+	return 0;
+}
diff --git a/arch/x86/cpu/tangier/tangier.c b/arch/x86/cpu/tangier/tangier.c
new file mode 100644
index 0000000000..20d6c6039b
--- /dev/null
+++ b/arch/x86/cpu/tangier/tangier.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/scu.h>
+#include <asm/u-boot-x86.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+int arch_cpu_init(void)
+{
+	return x86_cpu_init_f();
+}
+
+int checkcpu(void)
+{
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	return default_print_cpuinfo();
+}
+
+void reset_cpu(ulong addr)
+{
+	scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
+}