diff options
Diffstat (limited to 'arch/powerpc')
71 files changed, 3553 insertions, 108 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 18808da37dd..2bae08e2786 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -101,34 +101,42 @@ config TARGET_IDS8313 config TARGET_KMETER1 bool "Support kmeter1" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_KMCOGE5NE bool "Support kmcoge5ne" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_KMTEGR1 bool "Support kmtegr1" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_TUXX1 bool "Support tuxx1" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_KMSUPX5 bool "Support kmsupx5" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_TUGE1 bool "Support tuge1" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_KMOPTI2 bool "Support kmopti2" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_KMTEPR2 bool "Support kmtepr2" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_TQM834X bool "Support TQM834x" diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index 304029977e5..aeb42b109d0 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -27,7 +27,9 @@ obj-y += cpu_init.o obj-y += speed.o obj-y += interrupts.o obj-y += ecc.o +ifndef CONFIG_PINCTRL obj-$(CONFIG_QE) += qe_io.o +endif obj-$(CONFIG_FSL_SERDES) += serdes.o ifndef CONFIG_ARCH_MPC8308 obj-$(CONFIG_PCI) += pci.o diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 438b14b162e..840f907acb8 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -9,10 +9,14 @@ #include <ioports.h> #include <asm/io.h> #include <asm/processor.h> +#include <fsl_qe.h> #ifdef CONFIG_USB_EHCI_FSL #include <usb/ehci-ci.h> #endif #include <linux/delay.h> +#ifdef CONFIG_QE +#include <fsl_qe.h> +#endif #include "lblaw/lblaw.h" #include "elbc/elbc.h" @@ -26,9 +30,8 @@ DECLARE_GLOBAL_DATA_PTR; extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); -extern void qe_init(uint qe_base); -extern void qe_reset(void); +#if !defined(CONFIG_PINCTRL) static void config_qe_ioports(void) { u8 port, pin; @@ -45,6 +48,7 @@ static void config_qe_ioports(void) } } #endif +#endif /* * Breathe some life into the CPU... @@ -191,10 +195,13 @@ void cpu_init_f (volatile immap_t * im) __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir); #endif +#if !defined(CONFIG_PINCTRL) #ifdef CONFIG_QE /* Config QE ioports */ config_qe_ioports(); #endif +#endif + /* Set up preliminary BR/OR regs */ init_early_memctl_regs(); diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index ebdedb28889..4ea7b27ef41 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -121,7 +121,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) "clock-frequency", get_serial_clock(), 1); #endif - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size); #if defined(CONFIG_BOOTCOUNT_LIMIT) && \ (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X)) diff --git a/arch/powerpc/cpu/mpc83xx/qe_io.c b/arch/powerpc/cpu/mpc83xx/qe_io.c index 88aa6895511..52360703a7d 100644 --- a/arch/powerpc/cpu/mpc83xx/qe_io.c +++ b/arch/powerpc/cpu/mpc83xx/qe_io.c @@ -12,57 +12,93 @@ #include <asm/immap_83xx.h> #define NUM_OF_PINS 32 -void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) + +/** qe_cfg_iopin configure one io pin setting + * + * @par_io: pointer to parallel I/O base + * @port: io pin port + * @pin: io pin number which get configured + * @dir: direction of io pin 2 bits valid + * 00 = pin disabled + * 01 = output + * 10 = input + * 11 = pin is I/O + * @open_drain: is pin open drain + * @assign: pin assignment registers select the function of the pin + */ +static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir, + int open_drain, int assign) { - u32 pin_2bit_mask; - u32 pin_2bit_dir; - u32 pin_2bit_assign; - u32 pin_1bit_mask; - u32 tmp_val; - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio; + u32 dbit_mask; + u32 dbit_dir; + u32 dbit_asgn; + u32 bit_mask; + u32 tmp_val; + int offset; + + offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2); /* Calculate pin location and 2bit mask and dir */ - pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); - pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); + dbit_mask = (u32)(0x3 << offset); + dbit_dir = (u32)(dir << offset); /* Setup the direction */ - tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \ + tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ? in_be32(&par_io->ioport[port].dir2) : in_be32(&par_io->ioport[port].dir1); - if (pin > (NUM_OF_PINS/2) -1) { - out_be32(&par_io->ioport[port].dir2, ~pin_2bit_mask & tmp_val); - out_be32(&par_io->ioport[port].dir2, pin_2bit_dir | tmp_val); + if (pin > (NUM_OF_PINS / 2) - 1) { + out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val); } else { - out_be32(&par_io->ioport[port].dir1, ~pin_2bit_mask & tmp_val); - out_be32(&par_io->ioport[port].dir1, pin_2bit_dir | tmp_val); + out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val); } /* Calculate pin location for 1bit mask */ - pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1))); /* Setup the open drain */ tmp_val = in_be32(&par_io->ioport[port].podr); - if (open_drain) { - out_be32(&par_io->ioport[port].podr, pin_1bit_mask | tmp_val); - } else { - out_be32(&par_io->ioport[port].podr, ~pin_1bit_mask & tmp_val); - } + if (open_drain) + out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val); + else + out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val); /* Setup the assignment */ - tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? - in_be32(&par_io->ioport[port].ppar2): + tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ? + in_be32(&par_io->ioport[port].ppar2) : in_be32(&par_io->ioport[port].ppar1); - pin_2bit_assign = (u32)(assign - << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2)); + dbit_asgn = (u32)(assign << offset); /* Clear and set 2 bits mask */ - if (pin > (NUM_OF_PINS/2) - 1) { - out_be32(&par_io->ioport[port].ppar2, ~pin_2bit_mask & tmp_val); - out_be32(&par_io->ioport[port].ppar2, pin_2bit_assign | tmp_val); + if (pin > (NUM_OF_PINS / 2) - 1) { + out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val); } else { - out_be32(&par_io->ioport[port].ppar1, ~pin_2bit_mask & tmp_val); - out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val); + out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val); } } + +#if !defined(CONFIG_PINCTRL) +/** qe_config_iopin configure one io pin setting + * + * @port: io pin port + * @pin: io pin number which get configured + * @dir: direction of io pin 2 bits valid + * 00 = pin disabled + * 01 = output + * 10 = input + * 11 = pin is I/O + * @open_drain: is pin open drain + * @assign: pin assignment registers select the function of the pin + */ +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio; + + qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign); +} +#endif diff --git a/arch/powerpc/cpu/mpc83xx/traps.c b/arch/powerpc/cpu/mpc83xx/traps.c index c3cc119d654..ea8bc6c1528 100644 --- a/arch/powerpc/cpu/mpc83xx/traps.c +++ b/arch/powerpc/cpu/mpc83xx/traps.c @@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Returns 0 if exception not found and fixup otherwise. */ extern unsigned long search_exception_table(unsigned long); -#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) +#define END_OF_MEM (gd->ram_base + gd->ram_size) /* * Trap & Exception support diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 753d0750b2b..54c7fd9522a 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -40,14 +40,6 @@ config TARGET_P4080DS imply CMD_SATA imply PANIC_HANG -config TARGET_P5020DS - bool "Support P5020DS" - select PHYS_64BIT - select ARCH_P5020 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - imply CMD_SATA - imply PANIC_HANG - config TARGET_P5040DS bool "Support P5040DS" select PHYS_64BIT @@ -109,22 +101,6 @@ config TARGET_P1010RDB_PB imply CMD_SATA imply PANIC_HANG -config TARGET_P1023RDB - bool "Support P1023RDB" - select ARCH_P1023 - select FSL_DDR_INTERACTIVE - imply CMD_EEPROM - imply PANIC_HANG - -config TARGET_P1020MBG - bool "Support P1020MBG-PC" - select SUPPORT_SPL - select SUPPORT_TPL - select ARCH_P1020 - imply CMD_EEPROM - imply CMD_SATA - imply PANIC_HANG - config TARGET_P1020RDB_PC bool "Support P1020RDB-PC" select SUPPORT_SPL @@ -143,42 +119,6 @@ config TARGET_P1020RDB_PD imply CMD_SATA imply PANIC_HANG -config TARGET_P1020UTM - bool "Support P1020UTM" - select SUPPORT_SPL - select SUPPORT_TPL - select ARCH_P1020 - imply CMD_EEPROM - imply CMD_SATA - imply PANIC_HANG - -config TARGET_P1021RDB - bool "Support P1021RDB" - select SUPPORT_SPL - select SUPPORT_TPL - select ARCH_P1021 - imply CMD_EEPROM - imply CMD_SATA - imply PANIC_HANG - -config TARGET_P1024RDB - bool "Support P1024RDB" - select SUPPORT_SPL - select SUPPORT_TPL - select ARCH_P1024 - imply CMD_EEPROM - imply CMD_SATA - imply PANIC_HANG - -config TARGET_P1025RDB - bool "Support P1025RDB" - select SUPPORT_SPL - select SUPPORT_TPL - select ARCH_P1025 - imply CMD_EEPROM - imply CMD_SATA - imply SATA_SIL - config TARGET_P2020RDB bool "Support P2020RDB-PC" select SUPPORT_SPL @@ -1506,7 +1446,6 @@ source "board/freescale/mpc8568mds/Kconfig" source "board/freescale/mpc8569mds/Kconfig" source "board/freescale/mpc8572ds/Kconfig" source "board/freescale/p1010rdb/Kconfig" -source "board/freescale/p1023rdb/Kconfig" source "board/freescale/p1_p2_rdb_pc/Kconfig" source "board/freescale/p2041rdb/Kconfig" source "board/freescale/qemu-ppce500/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 9569c1a64b8..0d8353ceb26 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -672,10 +672,10 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) "clock-frequency", get_bus_freq(0), 1); #endif - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size); #ifdef CONFIG_MP - ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); + ft_fixup_cpu(blob, (u64)gd->ram_base + (u64)gd->ram_size); ft_fixup_num_cores(blob); #endif diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index f37a45e2694..db6ed1fc92e 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -37,7 +37,7 @@ extern unsigned long search_exception_table(unsigned long); * amount of memory on the system if we're unable to keep all * the memory mapped in. */ -#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) +#define END_OF_MEM (gd->ram_base + get_effective_memsize()) static __inline__ void set_tsr(unsigned long val) { diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index 24e53115ecc..010b6d4fe60 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -8,6 +8,8 @@ #include <fdt_support.h> #include <asm/mp.h> +DECLARE_GLOBAL_DATA_PTR; + extern void ft_fixup_num_cores(void *blob); extern void ft_srio_setup(void *blob); @@ -27,7 +29,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size); #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", diff --git a/arch/powerpc/cpu/mpc86xx/traps.c b/arch/powerpc/cpu/mpc86xx/traps.c index c0161e3379c..3ee0ec859cf 100644 --- a/arch/powerpc/cpu/mpc86xx/traps.c +++ b/arch/powerpc/cpu/mpc86xx/traps.c @@ -30,7 +30,7 @@ extern unsigned long search_exception_table(unsigned long); * amount of memory on the system if we're unable to keep all * the memory mapped in. */ -#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) +#define END_OF_MEM (gd->ram_base + get_effective_memsize()) /* * Trap & Exception support diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c index 4d952a3882f..226e258f0ea 100644 --- a/arch/powerpc/cpu/mpc8xx/fdt.c +++ b/arch/powerpc/cpu/mpc8xx/fdt.c @@ -25,5 +25,5 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", gd->arch.brg_clk, 1); - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size); } diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 2b24e755faa..b2d1dc5b481 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -343,6 +343,7 @@ int fixup_cpu(void) return 0; } +#ifndef CONFIG_DM_ETH /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() @@ -370,3 +371,4 @@ int cpu_eth_init(struct bd_info *bis) #endif return 0; } +#endif diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 7eb005f4501..266d345f720 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,5 +1,11 @@ # SPDX-License-Identifier: GPL-2.0+ +dtb-$(CONFIG_TARGET_KMCOGE5NE) += kmcoge5ne.dtb +dtb-$(CONFIG_TARGET_KMETER1) += kmeter1.dtb +dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb +dtb-$(CONFIG_TARGET_KMSUPX5) += kmsupc5.dtb kmsupm5.dtb +dtb-$(CONFIG_TARGET_KMTEGR1) += kmtegr1.dtb +dtb-$(CONFIG_TARGET_KMTEPR2) += kmtepr2.dtb dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb @@ -16,6 +22,8 @@ dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb +dtb-$(CONFIG_TARGET_TUGE1) += kmtuge1.dtb +dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb diff --git a/arch/powerpc/dts/km8309-uboot.dtsi b/arch/powerpc/dts/km8309-uboot.dtsi new file mode 100644 index 00000000000..c44ce7d8dcd --- /dev/null +++ b/arch/powerpc/dts/km8309-uboot.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA 8309 U-Boot specific Device Tree Source parts + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/ { + cpus { + u-boot,dm-pre-reloc; + PowerPC,8309@0 { + u-boot,dm-pre-reloc; + }; + }; + + chosen { + stdout-path = &serial0; + }; +}; + +&qe { + compatible = "fsl,qe", "simple-bus"; +}; + +&soc { + u-boot,dm-pre-reloc; +}; + +&serial0 { + clock-frequency = <132000000>; + u-boot,dm-pre-reloc; +}; diff --git a/arch/powerpc/dts/km8321-uboot.dtsi b/arch/powerpc/dts/km8321-uboot.dtsi new file mode 100644 index 00000000000..348826057a8 --- /dev/null +++ b/arch/powerpc/dts/km8321-uboot.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA 8321 U-Boot specific Device Tree Source parts + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/ { + cpus { + u-boot,dm-pre-reloc; + PowerPC,8321@0 { + u-boot,dm-pre-reloc; + }; + }; + + chosen { + stdout-path = &serial0; + }; +}; + +&enet_piggy2 { + status = "okay"; +}; + +&qe { + compatible = "fsl,qe", "simple-bus"; +}; + +&serial0 { + clock-frequency = <132000000>; + u-boot,dm-pre-reloc; +}; + +&soc { + u-boot,dm-pre-reloc; + + par_io@1400 { + compatible = "fsl,mpc8360-par_io"; + u-boot,dm-pre-reloc; + + serial_pin@0 { + u-boot,dm-pre-reloc; + }; + ucc_pin@0 { + u-boot,dm-pre-reloc; + }; + ucc_pin@1 { + u-boot,dm-pre-reloc; + }; + ucc_pin@3 { + u-boot,dm-pre-reloc; + }; + ucc_pin@4 { + u-boot,dm-pre-reloc; + }; + ucc_pin@5 { + u-boot,dm-pre-reloc; + }; + ucc_pin@6 { + u-boot,dm-pre-reloc; + }; + ucc_pin@7 { + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/powerpc/dts/km8321.dtsi b/arch/powerpc/dts/km8321.dtsi new file mode 100644 index 00000000000..e49361359d8 --- /dev/null +++ b/arch/powerpc/dts/km8321.dtsi @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA km8321 common ports Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8321@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <16384>; // L1, 16K + i-cache-size = <16384>; // L1, 16K + timebase-frequency = <66000000>; + bus-frequency = <264000000>; + clock-frequency = <528000000>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + soc: soc8321@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0x0 0xe0000000 0x00100000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <264000000>; + + i2c0: i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc8313-i2c","fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + clock-frequency = <100000>; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <264000000>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8321-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8321-dma-channel", + "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8321-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8321-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8321-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + + ipic: pic@700 { + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "fsl,pq2pro-pic", "fsl,ipic"; + interrupt-controller; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + + par_io: par_io@1400 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1400 0x100>; + ranges; + device_type = "par_io"; + num-ports = <7>; + + qe_pio_d: gpio-controller@48 { + #gpio-cells = <2>; + compatible = "fsl,mpc8360-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank"; + reg = <0x1448 0x18>; + gpio-controller; + }; + }; + }; + + qe: qe@e0100000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe"; + ranges = <0x0 0xe0100000 0x00100000>; + reg = <0xe0100000 0x480>; + brg-frequency = <0>; + bus-frequency = <396000000>; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x00010000 0x00004000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0x4000>; + }; + }; + + /* Piggy2 (UCC4, MDIO 0x00, RMII) */ + enet_piggy2: ucc@3200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <4>; + reg = <0x3200 0x200>; + interrupts = <35>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk17"; + phy-handle = <&phy_piggy2>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc4>; + }; + + mdio: mdio@3320 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3320 0x18>; + compatible = "fsl,ucc-mdio"; + + /* Piggy2 (UCC4, MDIO 0x00, RMII) */ + phy_piggy2: ethernet-phy@00 { + reg = <0x0>; + device_type = "ethernet-phy"; + }; + }; + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + big-endian; + interrupts = <32 8 33 8>; + interrupt-parent = <&ipic>; + }; + bootcount@0x13ff8 { + device_type = "bootcount"; + compatible = "u-boot,bootcount"; + reg = <0x13ff8 0x08>; + }; + + spi0: spi@4c0 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x4c0 0x40>; + interrupts = <2>; + interrupt-parent = <&qeic>; + mode = "qe"; + #address-cells = <1>; + #size-cells = <0>; + pio-handle = <&pio_spi>; + }; + }; + + localbus: localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8321-localbus", "fsl,pq2pro-localbus", + "simple-bus"; + reg = <0xe0005000 0xd8>; + }; +}; + +#include "km8321-uboot.dtsi" diff --git a/arch/powerpc/dts/km836x-uboot.dtsi b/arch/powerpc/dts/km836x-uboot.dtsi new file mode 100644 index 00000000000..ac5339eff65 --- /dev/null +++ b/arch/powerpc/dts/km836x-uboot.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA km836x U-Boot specific Device Tree Source parts + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/ { + cpus { + u-boot,dm-pre-reloc; + PowerPC,8360@0 { + u-boot,dm-pre-reloc; + }; + }; + + chosen { + stdout-path = &serial0; + }; +}; + +&qe { + compatible = "fsl,qe", "simple-bus"; +}; + +&soc { + u-boot,dm-pre-reloc; + + par_io@1400 { + u-boot,dm-pre-reloc; + + serial_pin@0 { + u-boot,dm-pre-reloc; + }; + ucc_pin@0 { + u-boot,dm-pre-reloc; + }; + ucc_pin@1 { + u-boot,dm-pre-reloc; + }; + ucc_pin@3 { + u-boot,dm-pre-reloc; + }; + ucc_pin@4 { + u-boot,dm-pre-reloc; + }; + ucc_pin@5 { + u-boot,dm-pre-reloc; + }; + ucc_pin@6 { + u-boot,dm-pre-reloc; + }; + ucc_pin@7 { + u-boot,dm-pre-reloc; + }; + }; +}; + +&serial0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/powerpc/dts/km836x.dtsi b/arch/powerpc/dts/km836x.dtsi new file mode 100644 index 00000000000..a8c83fc7e37 --- /dev/null +++ b/arch/powerpc/dts/km836x.dtsi @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA km836x common ports Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8360@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; /* 32 bytes */ + i-cache-line-size = <32>; /* 32 bytes */ + d-cache-size = <32768>; /* L1, 32K */ + i-cache-size = <32768>; /* L1, 32K */ + timebase-frequency = <0>; /* Filled in by U-Boot */ + bus-frequency = <0>; /* Filled in by U-Boot */ + clock-frequency = <0>; /* Filled in by U-Boot */ + }; + }; + + memory { + device_type = "memory"; + reg = <0 0>; /* Filled in by U-Boot */ + }; + + soc: soc8360@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8360-immr", "simple-bus"; + ranges = <0x0 0xe0000000 0x00200000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <0>;/* Filled in by U-Boot */ + + /* power management control module*/ + pmc: power@b00 { + compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; + reg = <0xb00 0x100 0xa00 0x100>; + interrupts = <80 0x8>; + interrupt-parent = <&ipic>; + }; + + i2c0: i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc8313-i2c","fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + clock-frequency = <100000>; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <264000000>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + status = "disabled"; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <133333333>; + interrupts = <10 0x8>; + interrupt-parent = <&ipic>; + status = "disabled"; + }; + + ipic: pic@700 { + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "fsl,pq2pro-pic", "fsl,ipic"; + interrupt-controller; + reg = <0x700 0x100>; + }; + + par_io: par_io@1400 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1400 0x100>; + ranges; + compatible = "fsl,mpc8360-par_io"; + device_type = "par_io"; + num-ports = <7>; + + qe_pio_c: gpio-controller@30 { + #gpio-cells = <2>; + compatible = "fsl,mpc8360-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank"; + reg = <0x1430 0x18>; + gpio-controller; + }; + }; + + qe: qe@100000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe"; + ranges = <0x0 0x100000 0x100000>; + reg = <0x100000 0x480>; + clock-frequency = <0>; /* Filled in by U-Boot */ + brg-frequency = <0>; /* Filled in by U-Boot */ + bus-frequency = <0>; /* Filled in by U-Boot */ + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x00010000 0x0000c000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0xc000>; + }; + }; + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + big-endian; + interrupts = < + 32 0x8 /* ucc1 */ + 33 0x8 /* ucc2 */ + 34 0x8 /* ucc3 */ + 35 0x8 /* ucc4 */ + 40 0x8 /* ucc1 */ + >; + interrupt-parent = <&ipic>; + }; + + spi0: spi@4c0 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x4c0 0x40>; + interrupts = <2>; + interrupt-parent = <&qeic>; + mode = "qe"; + #address-cells = <1>; + #size-cells = <0>; + pio-handle = <&pio_spi>; + }; + + bootcount@0x1bff8 { + device_type = "bootcount"; + compatible = "u-boot,bootcount"; + reg = <0x1bff8 0x08>; + }; + }; + }; + + localbus: localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", + "simple-bus"; + reg = <0xe0005000 0xd8>; + }; +}; + +#include "km836x-uboot.dtsi" diff --git a/arch/powerpc/dts/kmcoge5ne-uboot.dtsi b/arch/powerpc/dts/kmcoge5ne-uboot.dtsi new file mode 100644 index 00000000000..6a5e74f434b --- /dev/null +++ b/arch/powerpc/dts/kmcoge5ne-uboot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA kmcoge5ne U-Boot specific Device Tree Source parts + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/ { + aliases { + /delete-property/ ethernet1; + /delete-property/ ethernet2; + }; +}; + +&enet_switch { + status = "disabled"; +}; + +&enet_mate { + status = "disabled"; +}; diff --git a/arch/powerpc/dts/kmcoge5ne.dts b/arch/powerpc/dts/kmcoge5ne.dts new file mode 100644 index 00000000000..467e5bd9d27 --- /dev/null +++ b/arch/powerpc/dts/kmcoge5ne.dts @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA KMCOGE5ne Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +#include "km836x.dtsi" + +/ { + model = "kmcoge5ne"; + compatible = "ABB,kmcoge5ne"; + + aliases { + ethernet0 = &enet_admin; + ethernet1 = &enet_mate; + ethernet2 = &enet_switch; + serial0 = &serial0; + }; +}; + +&soc { + /* brg for hdlc clk */ + brg@0 { + compatible = "fsl,mpc-brg"; + brg-name = "brg16"; + brg-frequency = <20000000>; /* 20 MHz */ + pio-handle = <&pio_brg>; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the fan unit */ + fanu-ivm@50 { + label = "FANUV"; + compatible = "dummy"; + reg = <0x50>; + }; + + /* fan unit (GPIOs and so on) */ + fanu@20 { + label = "FANUV_CTRL"; + compatible = "dummy"; + reg = <0x20>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + backplane@50 { + label = "BP_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + }; +}; + +&serial0 { + status = "okay"; +}; + +&par_io { + pio_ucc1: ucc_pin@0 { /* RGMII mng-switch */ + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */ + 0 2 1 0 1 0 /* MDC (PA2, in, f1) */ + + 0 3 1 0 1 0 /* TxD0 (PA3, in, f1) */ + 0 4 1 0 1 0 /* TxD1 (PA4, in, f1) */ + 0 5 1 0 1 0 /* TxD2 (PA5, in, f1) */ + 0 6 1 0 1 0 /* TxD3 (PA6, in, f1) */ + 0 9 2 0 1 0 /* RxD0 (PA9, out, f1) */ + 0 10 2 0 1 0 /* RxD1 (PA10, out, f1) */ + 0 11 2 0 1 0 /* RxD2 (PA11, out, f1) */ + 0 12 2 0 1 0 /* RxD3 (PA12, out, f1) */ + 0 7 1 0 1 0 /* TX_EN (PA7, in, f1) */ + 0 15 2 0 1 0 /* RX_DV (PA15, out, f1) */ + 0 0 2 0 1 0 /* RX_CLK (PA0, out, f1) */ + 2 9 1 0 3 0 /* GTX_CLK (CLK10) */ + 2 8 2 0 1 0 /* GTX125 (CLK9) */ + >; + }; + + pio_ucc4: ucc_pin@3 { /* RMII, admin front port */ + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */ + 0 2 1 0 1 0 /* MDC (PA2, in, f1) */ + + 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ + 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ + 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ + 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ + 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ + 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ + 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ + + 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_ucc5: ucc_pin@4 { /* RMII, mate backplane port */ + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */ + 0 2 1 0 1 0 /* MDC (PA2, in, f1) */ + + 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ + 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ + 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ + 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ + 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ + 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ + 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ + + 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3) */ + 4 29 3 0 3 0 /* SPI_MISO (PE29, out, f3) */ + 4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3) */ + >; + }; + + pio_brg: brg_pin@0 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 25 1 0 1 0 /* BRG (PC25, out, f1) */ + >; + }; + + pio_tdm: tdm_pin@00 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + /* TDMa */ + 0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */ + 0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */ + 0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */ + 2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */ + /* TDMb */ + 0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */ + 0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */ + 0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */ + 2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */ + /* TDMc */ + 1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */ + 1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */ + 1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */ + 2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */ + /* TDMd */ + 1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */ + 1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */ + 1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */ + 2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */ + /* TDMe */ + 3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */ + 3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */ + 3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */ + 2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */ + /* TDMf */ + 3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */ + 3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */ + 3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */ + 2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */ + /* TDMg */ + 4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */ + 4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */ + 4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */ + 2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */ + /* TDMh */ + 4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */ + 4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */ + 4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */ + 2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */ + /* RxTxClk0/1 */ + 2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */ + 2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */ + /* RxTxSync0/1 */ + 2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */ + 2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */ + }; +}; + +&qe { + /* mng-switch port (UCC1, MDIO 0x10, RGMII) */ + enet_switch: ethernet@2000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk9"; + /*id=0, full-dup, 1G, no-pause, no-asym_p*/ + fixed-link = <0 1 1000 0 0>; + phy-connection-type = "rgmii-id"; + pio-handle = <&pio_ucc1>; + }; + + /* admin and debug port (UCC4, MDIO 0x00, RMII) */ + enet_admin: ucc@3200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <4>; + reg = <0x3200 0x200>; + interrupts = <35>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk17"; + phy-handle = <&phy_admin>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc4>; + }; + + /* mate backplane port (UCC5, MDIO 0x08, RMII) */ + enet_mate: ucc@2400 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <5>; + reg = <0x2400 0x200>; + interrupts = <40>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_mate>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc5>; + }; + + mdio@3320 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3320 0x18>; + compatible = "fsl,ucc-mdio"; + + /* admin front port (UCC4, MDIO 0x00, RMII) */ + phy_admin: ethernet-phy@00 { + reg = <0x0>; + }; + + /* mate bp port (UCC5, MDIO 0x08, RMII) */ + phy_mate: ethernet-phy@08 { + reg = <0x08>; + }; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 + 1 0 0xe8000000 0x01000000 + 3 0 0xa0000000 0x10000000 + 4 0 0xb0000000 0x10000000>; + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x04000000>; + nornand = "nor"; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xC0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xE0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; + +#include "kmcoge5ne-uboot.dtsi" diff --git a/arch/powerpc/dts/kmeter1-uboot.dtsi b/arch/powerpc/dts/kmeter1-uboot.dtsi new file mode 100644 index 00000000000..898fa7dc7a8 --- /dev/null +++ b/arch/powerpc/dts/kmeter1-uboot.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA kmeter1 U-Boot specific Device Tree Source parts + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/ { + aliases { + /delete-property/ ethernet1; + /delete-property/ ethernet2; + /delete-property/ ethernet3; + /delete-property/ ethernet4; + /delete-property/ ethernet5; + /delete-property/ ethernet6; + }; +}; + +&enet_estar1 { + status = "disabled"; +}; + +&enet_estar2 { + status = "disabled"; +}; + +&enet_eth1 { + status = "disabled"; +}; + +&enet_eth2 { + status = "disabled"; +}; + +&enet_eth3 { + status = "disabled"; +}; + +&enet_eth4 { + status = "disabled"; +}; diff --git a/arch/powerpc/dts/kmeter1.dts b/arch/powerpc/dts/kmeter1.dts new file mode 100644 index 00000000000..f1f79952abe --- /dev/null +++ b/arch/powerpc/dts/kmeter1.dts @@ -0,0 +1,480 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA KMETER1 Device Tree Source + * + * 2008-2011 DENX Software Engineering GmbH + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + */ + +/dts-v1/; + +#include "km836x.dtsi" + +/ { + model = "KMETER1"; + compatible = "ABB,KMETER1"; + + aliases { + ethernet0 = &enet_piggy2; + ethernet1 = &enet_estar1; + ethernet2 = &enet_estar2; + ethernet3 = &enet_eth1; + ethernet4 = &enet_eth2; + ethernet5 = &enet_eth3; + ethernet6 = &enet_eth4; + serial0 = &serial0; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@48 { + label = "Top"; + compatible = "national,lm75"; + reg = <0x48>; + }; + + temp@49 { + label = "Control"; + compatible = "national,lm75"; + reg = <0x49>; + }; + + temp@4a { + label = "Power"; + compatible = "national,lm75"; + reg = <0x4a>; + }; + + temp@4b { + label = "Front"; + compatible = "national,lm75"; + reg = <0x4b>; + }; + }; + }; +}; + +&serial0 { + status = "okay"; +}; + +&par_io { + pio_ucc1: ucc_pin@0 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 0 3 1 0 1 0 /* TxD0 */ + 0 4 1 0 1 0 /* TxD1 */ + 0 5 1 0 1 0 /* TxD2 */ + 0 6 1 0 1 0 /* TxD3 */ + 0 9 2 0 1 0 /* RxD0 */ + 0 10 2 0 1 0 /* RxD1 */ + 0 11 2 0 1 0 /* RxD2 */ + 0 12 2 0 1 0 /* RxD3 */ + 0 7 1 0 1 0 /* TX_EN */ + 0 8 1 0 1 0 /* TX_ER */ + 0 15 2 0 1 0 /* RX_DV */ + 0 16 2 0 1 0 /* RX_ER */ + 0 0 2 0 1 0 /* RX_CLK */ + 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ + 2 8 2 0 1 0 /* GTX125 - CLK9 */ + >; + }; + + pio_ucc2: ucc_pin@1 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 0 17 1 0 1 0 /* TxD0 */ + 0 18 1 0 1 0 /* TxD1 */ + 0 19 1 0 1 0 /* TxD2 */ + 0 20 1 0 1 0 /* TxD3 */ + 0 23 2 0 1 0 /* RxD0 */ + 0 24 2 0 1 0 /* RxD1 */ + 0 25 2 0 1 0 /* RxD2 */ + 0 26 2 0 1 0 /* RxD3 */ + 0 21 1 0 1 0 /* TX_EN */ + 0 22 1 0 1 0 /* TX_ER */ + 0 29 2 0 1 0 /* RX_DV */ + 0 30 2 0 1 0 /* RX_ER */ + 0 31 2 0 1 0 /* RX_CLK */ + 2 2 1 0 2 0 /* GTX_CLK - CLK3 */ + 2 3 2 0 1 0 /* GTX125 - CLK4 */ + >; + }; + + pio_ucc4: ucc_pin@3 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ + 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ + 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ + 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ + 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ + 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ + 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ + + 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_ucc5: ucc_pin@4 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ + 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ + 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ + 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ + 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ + 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ + 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ + >; + }; + + pio_ucc6: ucc_pin@5 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */ + 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */ + 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */ + 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */ + 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */ + 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */ + 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */ + >; + }; + + pio_ucc7: ucc_pin@6 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */ + 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */ + 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */ + 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */ + 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */ + 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */ + 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */ + >; + }; + + pio_ucc8: ucc_pin@7 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */ + 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */ + 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */ + 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */ + 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */ + 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */ + 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */ + + 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3 */ + 4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3 */ + >; + }; + + /* UCC3 as HDLC controller for ICN */ + pio5: ucc_pin@02 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 1 0 1 0 1 0 /* TxD0 */ + 1 6 2 0 1 0 /* RxD0 */ + 1 12 2 0 1 0 /* CTS */ + 2 11 2 0 1 0 /* TX-CLK12 */ + >; + }; + + pio_tdm: tdm_pin@00 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + /* TDMa */ + 0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */ + 0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */ + 0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */ + 2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */ + /* TDMb */ + 0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */ + 0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */ + 0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */ + 2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */ + /* TDMc */ + 1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */ + 1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */ + 1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */ + 2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */ + /* TDMd */ + 1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */ + 1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */ + 1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */ + 2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */ + /* TDMe */ + 3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */ + 3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */ + 3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */ + 2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */ + /* TDMf */ + 3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */ + 3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */ + 3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */ + 2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */ + /* TDMg */ + 4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */ + 4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */ + 4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */ + 2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */ + /* TDMh */ + 4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */ + 4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */ + 4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */ + 2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */ + /* RxTxClk0/1 */ + 2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */ + 2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */ + /* RxTxSync0/1 */ + 2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */ + 2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */ + }; +}; + +&qe { + /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ + enet_estar1: ucc@2000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk9"; + phy-handle = <&phy_estar1>; + phy-connection-type = "rgmii-id"; + pio-handle = <&pio_ucc1>; + }; + + /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ + enet_estar2: ucc@3000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <2>; + reg = <0x3000 0x200>; + interrupts = <33>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk4"; + phy-handle = <&phy_estar2>; + phy-connection-type = "rgmii-id"; + pio-handle = <&pio_ucc2>; + }; + + /* Piggy2 (UCC4, MDIO 0x00, RMII) */ + enet_piggy2: ucc@3200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <4>; + reg = <0x3200 0x200>; + interrupts = <35>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk17"; + phy-handle = <&phy_piggy2>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc4>; + }; + + /* Eth-1 (UCC5, MDIO 0x08, RMII) */ + enet_eth1: ucc@2400 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <5>; + reg = <0x2400 0x200>; + interrupts = <40>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth1>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc5>; + }; + + /* Eth-2 (UCC6, MDIO 0x09, RMII) */ + enet_eth2: ucc@3400 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <6>; + reg = <0x3400 0x200>; + interrupts = <41>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth2>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc6>; + }; + + /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ + enet_eth3: ucc@2600 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <7>; + reg = <0x2600 0x200>; + interrupts = <42>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth3>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc7>; + }; + + /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ + enet_eth4: ucc@3600 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <8>; + reg = <0x3600 0x200>; + interrupts = <43>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth4>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc8>; + }; + + mdio@3320 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3320 0x18>; + compatible = "fsl,ucc-mdio"; + + /* Piggy2 (UCC4, MDIO 0x00, RMII) */ + phy_piggy2: ethernet-phy@0 { + reg = <0x0>; + }; + + /* Eth-1 (UCC5, MDIO 0x08, RMII) */ + phy_eth1: ethernet-phy@8 { + reg = <0x08>; + }; + + /* Eth-2 (UCC6, MDIO 0x09, RMII) */ + phy_eth2: ethernet-phy@9 { + reg = <0x09>; + }; + + /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ + phy_eth3: ethernet-phy@a { + reg = <0x0a>; + }; + + /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ + phy_eth4: ethernet-phy@b { + reg = <0x0b>; + }; + + /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ + phy_estar1: ethernet-phy@10 { + interrupt-parent = <&ipic>; + interrupts = <17 0x8>; + reg = <0x10>; + }; + + /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ + phy_estar2: ethernet-phy@11 { + interrupt-parent = <&ipic>; + interrupts = <18 0x8>; + reg = <0x11>; + }; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */ + 1 0 0xe8000000 0x01000000 /* LB 1 */ + 3 0 0xa0000000 0x10000000>; /* LB 3 */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x04000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xC0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xE0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; + +#include "kmeter1-uboot.dtsi" diff --git a/arch/powerpc/dts/kmopti2.dts b/arch/powerpc/dts/kmopti2.dts new file mode 100644 index 00000000000..23e31872dd5 --- /dev/null +++ b/arch/powerpc/dts/kmopti2.dts @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA OPTI2 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "KMOPTI2"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@49 { + label = "board"; + compatible = "national,lm75"; + reg = <0x49>; + }; + + temp@4a { + label = "power"; + compatible = "national,lm75"; + reg = <0x4a>; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 0 3 0 1 0 /* SPI_MOSI (PD0, bi, f3) */ + 3 1 3 0 1 0 /* SPI_MISO (PD1, bi, f3) */ + 3 2 3 0 1 0 /* SPI_CLK (PD2, bi, f3) */ + >; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000 /* LB 2 PAXE */ + 3 0 0xb0000000 0x10000000>; /* LB 3 OPI2 */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + use-advanced-sector-protection; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmsupc5.dts b/arch/powerpc/dts/kmsupc5.dts new file mode 100644 index 00000000000..60ca0d3324f --- /dev/null +++ b/arch/powerpc/dts/kmsupc5.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA SUPC5 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "SUPC5"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@49 { + label = "board"; + compatible = "national,lm75"; + reg = <0x49>; + }; + }; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + /* UCC4_RMII_CLK (CLK17) */ + 3 10 2 0 3 0 + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* + * port pin dir open_drain assignment has_irq + * SPI_MOSI (PD0, bi, f3) + */ + 3 0 3 0 1 0 + /* SPI_MISO (PD1, bi, f3) */ + 3 1 3 0 1 0 + /* SPI_CLK (PD2, bi, f3) */ + 3 2 3 0 1 0 + >; + }; +}; + +&spi0 { + pio-handle = <&pio_spi>; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000>; /* LB 2 LPXF */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmsupm5.dts b/arch/powerpc/dts/kmsupm5.dts new file mode 100644 index 00000000000..1cd11c33449 --- /dev/null +++ b/arch/powerpc/dts/kmsupm5.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA SUPM5 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "SUPM5"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@49 { + label = "board"; + compatible = "national,lm75"; + reg = <0x49>; + }; + }; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 0 3 0 1 0 /* SPI_MOSI (PD0, bi, f3) */ + 3 1 3 0 1 0 /* SPI_MISO (PD1, bi, f3) */ + 3 2 3 0 1 0 /* SPI_CLK (PD2, bi, f3) */ + >; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000>; /* LB 2 LPXF */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmtegr1.dts b/arch/powerpc/dts/kmtegr1.dts new file mode 100644 index 00000000000..c9b21cf5002 --- /dev/null +++ b/arch/powerpc/dts/kmtegr1.dts @@ -0,0 +1,392 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA TEGR1 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +/ { + model = "KMTEGR1"; + compatible = "ABB,kmpbec8309"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_zynq; + ethernet1 = &enet_piggy2; + serial0 = &serial0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8309@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <16384>; // L1, 16K + i-cache-size = <16384>; // L1, 16K + timebase-frequency = <66000000>; + bus-frequency = <264000000>; + clock-frequency = <264000000>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + soc: soc8309@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0x0 0xe0000000 0x00100000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <264000000>; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc8313-i2c","fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + clock-frequency = <400000>; + + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* + * Inventory EEPROM of the + * unit itself + */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@48 { + label = "front"; + compatible = "national,lm75"; + reg = <0x48>; + }; + + temp@49 { + label = "board"; + compatible = "national,lm75"; + reg = <0x49>; + }; + + temp@4a { + label = "power"; + compatible = "national,lm75"; + reg = <0x4a>; + }; + + temp@4b { + label = "bottom"; + compatible = "national,lm75"; + reg = <0x4b>; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + }; + }; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <264000000>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8309-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8309-dma-channel", + "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8309-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8309-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8309-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + + ipic: pic@700 { + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "fsl,pq2pro-pic", "fsl,ipic"; + interrupt-controller; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + + gpio1: gpio-controller@c00 { + #gpio-cells = <2>; + compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio"; + reg = <0xc00 0x100>; + interrupts = <75 0x8>; + interrupt-parent = <&ipic>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio-controller@d00 { + #gpio-cells = <2>; + compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio"; + reg = <0xd00 0x100>; + interrupts = <75 0x8>; + interrupt-parent = <&ipic>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + spi@7000 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x7000 0x1000>; + interrupts = <16 0x8>; + interrupt-parent = <&ipic>; + mode = "cpu"; + #address-cells = <1>; + #size-cells = <0>; + + /* GPIO_15 chipselect for ZYNQ flash */ + gpios = <&gpio1 15 0>; + + zynq_flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,m25p80"; + reg = <0>; + spi-max-frequency = <4000000>; + m25p,fast-read; + partition@0 { + label = "bootloader"; + reg = <0x0 0x01000000>; + }; + }; + }; + }; + + qe: qe@e0100000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe"; + ranges = <0x0 0xe0100000 0x00100000>; + reg = <0xe0100000 0x480>; + brg-frequency = <0>; + bus-frequency = <396000000>; + fsl,qe-num-snums = <32>; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x00010000 0x00004000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0x4000>; + }; + }; + + /* ZYNQ (UCC1, MDIO 0x10, MII) */ + enet_zynq: ethernet@2000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + /*id=0, full-dup, 100M, no-pause, no-asym_p*/ + fixed-link = <0 1 100 0 0>; + rx-clock-name = "clk9"; + tx-clock-name = "clk10"; + phy-connection-type = "mii"; + }; + + /* Piggy2 (UCC3, MDIO 0x00, RMII) */ + enet_piggy2: ucc@2200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <3>; + reg = <0x2200 0x200>; + interrupts = <34>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk12"; + phy-handle = <&phy_piggy2>; + phy-connection-type = "rmii"; + }; + + mdio@2320 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2320 0x38>; + compatible = "fsl,ucc-mdio"; + + /* Piggy2 (UCC3, MDIO 0x00, RMII) */ + phy_piggy2: ethernet-phy@0 { + reg = <0x0>; + device_type = "ethernet-phy"; + }; + + /* Explicitly set the tbi-phy to a non-zero address + * so that it does not conflict with phy_piggy2 that + * is unfortunately at address 0 + */ + tbi1: tbi-phy@1 { + reg = <0x1>; + device_type = "tbi-phy"; + }; + }; + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + big-endian; + interrupts = <32 8 33 8>; + interrupt-parent = <&ipic>; + }; + bootcount@0x13ff8 { + device_type = "bootcount"; + compatible = "u-boot,bootcount"; + reg = <0x13ff8 0x08>; + }; + + }; + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8309-localbus", "fsl,pq2pro-localbus", + "simple-bus"; + reg = <0xe0005000 0xd8>; + ranges = <0 0 0xf0000000 0x04000000 + 1 0 0xe8000000 0x01000000 + 2 0 0xe0000000 0x10000000 + 3 0 0xb0000000 0x10000000>; + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + nornand = "nor"; + #address-cells = <1>; + #size-cells = <1>; + use-advanced-sector-protection; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xc0000>; + }; + partition@c0000 { /* 256KB */ + label = "qe-fw"; + reg = <0xc0000 0x40000>; + }; + partition@100000 { /* 128KB */ + label = "env"; + reg = <0x100000 0x20000>; + }; + partition@120000 { /* 128KB */ + label = "envred"; + reg = <0x120000 0x20000>; + }; + partition@140000 { /* 64256KB */ + label = "ubi0"; + reg = <0x140000 0x3EC0000>; + }; + }; + }; +}; + +#include "km8309-uboot.dtsi" diff --git a/arch/powerpc/dts/kmtepr2.dts b/arch/powerpc/dts/kmtepr2.dts new file mode 100644 index 00000000000..5a272ec6cbe --- /dev/null +++ b/arch/powerpc/dts/kmtepr2.dts @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA TEPR2 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "KMTEPR2"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@49 { + label = "board"; + compatible = "national,lm75"; + reg = <0x49>; + }; + + temp@4a { + label = "power"; + compatible = "national,lm75"; + reg = <0x4a>; + }; + }; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* + *port pin dir open_drain assignment has_irq + * SPI_MOSI (PD0, bi, f3) + */ + 3 0 3 0 1 0 + /* SPI_MISO (PD1, bi, f3) */ + 3 1 3 0 1 0 + /* SPI_CLK (PD2, bi, f3) */ + 3 2 3 0 1 0 + >; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000 /* LB 2 NVSRAM */ + 3 0 0xb0000000 0x10000000>; /* LB 3 TEP2 */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + use-advanced-sector-protection; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmtuge1.dts b/arch/powerpc/dts/kmtuge1.dts new file mode 100644 index 00000000000..8a7b5a42cba --- /dev/null +++ b/arch/powerpc/dts/kmtuge1.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA TUGE1 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "TUGE1"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* + *port pin dir open_drain assignment has_irq + * SPI_MOSI (PD0, bi, f3) + */ + 3 0 3 0 1 0 + /* SPI_MISO (PD1, bi, f3) */ + 3 1 3 0 1 0 + /* SPI_CLK (PD2, bi, f3) */ + 3 2 3 0 1 0 + >; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000>; /* LB 2 PAXI */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmtuxa1.dts b/arch/powerpc/dts/kmtuxa1.dts new file mode 100644 index 00000000000..c2681c5efbc --- /dev/null +++ b/arch/powerpc/dts/kmtuxa1.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA TUXA1 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "TUXA1"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* + *port pin dir open_drain assignment has_irq + * SPI_MOSI (PD0, bi, f3) + */ + 3 0 3 0 1 0 + /* SPI_MISO (PD1, bi, f3) */ + 3 1 3 0 1 0 + /* SPI_CLK (PD2, bi, f3) */ + 3 2 3 0 1 0 + >; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000 /* LB 2 LPXF */ + 3 0 0xb0000000 0x10000000>; /* LB 3 PINC2 */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts index c66c4923ac3..360d254d91e 100644 --- a/arch/powerpc/dts/p1010rdb-pa.dts +++ b/arch/powerpc/dts/p1010rdb-pa.dts @@ -15,3 +15,4 @@ }; /include/ "p1010si-post.dtsi" +/include/ "p1010rdb.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts b/arch/powerpc/dts/p1010rdb-pa_36b.dts index b943de7cbb2..062086a8c09 100644 --- a/arch/powerpc/dts/p1010rdb-pa_36b.dts +++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts @@ -15,3 +15,4 @@ }; /include/ "p1010si-post.dtsi" +/include/ "p1010rdb.dtsi" diff --git a/arch/powerpc/dts/p1010rdb.dtsi b/arch/powerpc/dts/p1010rdb.dtsi index 4f58ee24460..c2aecde134d 100644 --- a/arch/powerpc/dts/p1010rdb.dtsi +++ b/arch/powerpc/dts/p1010rdb.dtsi @@ -4,11 +4,78 @@ * * Copyright 2020 NXP */ +/ { + aliases { + spi0 = &espi0; + }; +}; + &soc { + mdio@24000 { + phy0: ethernet-phy@0 { + reg = <0x1>; + }; + + phy1: ethernet-phy@1 { + reg = <0x0>; + }; + + phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + tbi-phy@3 { + device_type = "tbi-phy"; + reg = <0x3>; + }; + }; + + mdio@25000 { + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + mdio@26000 { + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + enet0: ethernet@b0000 { + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + }; + + enet1: ethernet@b1000 { + phy-handle = <&phy1>; + tbi-handle = <&tbi0>; + phy-connection-type = "sgmii"; + }; + + enet2: ethernet@b2000 { + phy-handle = <&phy2>; + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + }; + i2c@3000 { rtc@68 { compatible = "pericom,pt7c4338"; reg = <0x68>; }; }; + + spi@7000 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; + }; }; diff --git a/arch/powerpc/dts/p1010si-post.dtsi b/arch/powerpc/dts/p1010si-post.dtsi index 02894413818..2e7eb0e2fb1 100644 --- a/arch/powerpc/dts/p1010si-post.dtsi +++ b/arch/powerpc/dts/p1010si-post.dtsi @@ -23,8 +23,43 @@ single-cpu-affinity; last-interrupt-source = <255>; }; + + espi0: spi@7000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7000 0x1000>; + fsl,espi-num-chipselects = <1>; + status = "disabled"; + }; + /include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" + +/include/ "pq3-etsec2-0.dtsi" + enet0: ethernet@b0000 { + queue-group@b0000 { + fsl,rx-bit-map = <0xff>; + fsl,tx-bit-map = <0xff>; + }; + }; + +/include/ "pq3-etsec2-1.dtsi" + enet1: ethernet@b1000 { + queue-group@b1000 { + fsl,rx-bit-map = <0xff>; + fsl,tx-bit-map = <0xff>; + }; + }; + +/include/ "pq3-etsec2-2.dtsi" + enet2: ethernet@b2000 { + queue-group@b2000 { + fsl,rx-bit-map = <0xff>; + fsl,tx-bit-map = <0xff>; + }; + + }; }; /* controller at 0x9000 */ diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 1dce8e86e9a..03b68869918 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -44,10 +44,35 @@ clock-frequency = <0>; }; - /include/ "pq3-i2c-0.dtsi" - /include/ "pq3-i2c-1.dtsi" + espi0: spi@7000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + +/include/ "pq3-i2c-0.dtsi" +/include/ "pq3-i2c-1.dtsi" + +/include/ "pq3-etsec2-0.dtsi" + enet0: enet0_grp2: ethernet@b0000 { + }; + +/include/ "pq3-etsec2-1.dtsi" + enet1: enet1_grp2: ethernet@b1000 { + }; + +/include/ "pq3-etsec2-2.dtsi" + enet2: enet2_grp2: ethernet@b2000 { + }; }; +/include/ "pq3-etsec2-grp2-0.dtsi" +/include/ "pq3-etsec2-grp2-1.dtsi" +/include/ "pq3-etsec2-grp2-2.dtsi" + /* PCIe controller base address 0x9000 */ &pci1 { compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts index 7ebaa619df4..ab423253663 100644 --- a/arch/powerpc/dts/p1020rdb-pc.dts +++ b/arch/powerpc/dts/p1020rdb-pc.dts @@ -30,6 +30,22 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ }; + + aliases { + spi0 = &espi0; + }; }; +/include/ "p1020rdb-pc.dtsi" /include/ "p1020-post.dtsi" + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; +}; diff --git a/arch/powerpc/dts/p1020rdb-pc.dtsi b/arch/powerpc/dts/p1020rdb-pc.dtsi new file mode 100644 index 00000000000..6bf424fd3ff --- /dev/null +++ b/arch/powerpc/dts/p1020rdb-pc.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges) + * + * Copyright 2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&soc { + mdio@24000 { + phy0: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <3 1 0 0>; + reg = <0x0>; + }; + + phy1: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <2 1 0 0>; + reg = <0x1>; + }; + + tbi0: tbi-phy@11 { + device_type = "tbi-phy"; + reg = <0x11>; + }; + }; + + mdio@25000 { + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + enet0: ethernet@b0000 { + phy-connection-type = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + + }; + + enet1: ethernet@b1000 { + phy-handle = <&phy0>; + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + }; + + enet2: ethernet@b2000 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; +}; diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts index c0e5ef4cf42..708f9a9db1b 100644 --- a/arch/powerpc/dts/p1020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts @@ -30,6 +30,22 @@ ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */ 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ }; + + aliases { + spi0 = &espi0; + }; }; +/include/ "p1020rdb-pc.dtsi" /include/ "p1020-post.dtsi" + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; +}; diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts index 21174a09be5..b05f3deed51 100644 --- a/arch/powerpc/dts/p1020rdb-pd.dts +++ b/arch/powerpc/dts/p1020rdb-pd.dts @@ -17,6 +17,51 @@ soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; + + mdio@24000 { + phy0: ethernet-phy@0 { + interrupts = <3 1 0 0>; + reg = <0x0>; + }; + + phy1: ethernet-phy@1 { + interrupts = <2 1 0 0>; + reg = <0x1>; + }; + }; + + mdio@25000 { + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + mdio@26000 { + tbi2: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + enet0: ethernet@b0000 { + phy-connection-type = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + enet1: ethernet@b1000 { + phy-handle = <&phy0>; + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + }; + + enet2: ethernet@b2000 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; }; pci1: pcie@ffe09000 { @@ -30,6 +75,21 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ }; + + aliases { + spi0 = &espi0; + }; }; /include/ "p1020-post.dtsi" + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; +}; diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 4ed093dad4e..6d46f7d8dd7 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -38,8 +38,21 @@ clock-frequency = <0>; }; - /include/ "pq3-i2c-0.dtsi" - /include/ "pq3-i2c-1.dtsi" + espi0: spi@7000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + +/include/ "pq3-i2c-0.dtsi" +/include/ "pq3-i2c-1.dtsi" + +/include/ "pq3-etsec1-0.dtsi" +/include/ "pq3-etsec1-1.dtsi" +/include/ "pq3-etsec1-2.dtsi" }; /* PCIe controller base address 0x8000 */ diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts index 08befd4c593..b37931ac449 100644 --- a/arch/powerpc/dts/p2020rdb-pc.dts +++ b/arch/powerpc/dts/p2020rdb-pc.dts @@ -35,6 +35,22 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ }; + + aliases { + spi0 = &espi0; + }; }; +/include/ "p2020rdb-pc.dtsi" /include/ "p2020-post.dtsi" + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; +}; diff --git a/arch/powerpc/dts/p2020rdb-pc.dtsi b/arch/powerpc/dts/p2020rdb-pc.dtsi new file mode 100644 index 00000000000..0d2acc746e4 --- /dev/null +++ b/arch/powerpc/dts/p2020rdb-pc.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges) + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&soc { + mdio@24520 { + phy0: ethernet-phy@0 { + interrupts = <3 1 0 0>; + reg = <0x0>; + }; + phy1: ethernet-phy@1 { + interrupts = <2 1 0 0>; + reg = <0x1>; + }; + }; + + mdio@25520 { + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + mdio@26520 { + status = "disabled"; + }; + + enet0: ethernet@24000 { + phy-connection-type = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + enet1: ethernet@25000 { + tbi-handle = <&tbi0>; + phy-handle = <&phy0>; + phy-connection-type = "sgmii"; + }; + + enet2: ethernet@26000 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; +}; diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts index 04b2519e1a5..ecdc022d997 100644 --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts @@ -35,6 +35,22 @@ ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */ 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ }; + + aliases { + spi0 = &espi0; + }; }; +/include/ "p2020rdb-pc.dtsi" /include/ "p2020-post.dtsi" + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; +}; diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi index 95931e299d8..ad09b138fc8 100644 --- a/arch/powerpc/dts/p2041.dtsi +++ b/arch/powerpc/dts/p2041.dtsi @@ -60,6 +60,15 @@ clock-frequency = <0x0>; }; + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + usb0: usb@210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>; diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts index 9d59f9c8331..0fa1f098524 100644 --- a/arch/powerpc/dts/p2041rdb.dts +++ b/arch/powerpc/dts/p2041rdb.dts @@ -26,6 +26,7 @@ phy_sgmii_1e = &phy_sgmii_1e; phy_sgmii_1f = &phy_sgmii_1f; phy_xgmii_2 = &phy_xgmii_2; + spi0 = &espi0; }; soc: soc@ffe000000 { @@ -111,4 +112,16 @@ }; }; +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + /* input clock */ + spi-max-frequency = <10000000>; + }; +}; + /include/ "p2041si-post.dtsi" diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi index 3152683b846..e34117b65a0 100644 --- a/arch/powerpc/dts/p3041.dtsi +++ b/arch/powerpc/dts/p3041.dtsi @@ -60,6 +60,15 @@ clock-frequency = <0x0>; }; + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + usb0: usb@fe210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>; diff --git a/arch/powerpc/dts/p3041ds.dts b/arch/powerpc/dts/p3041ds.dts index b984ddea985..069dae3b85b 100644 --- a/arch/powerpc/dts/p3041ds.dts +++ b/arch/powerpc/dts/p3041ds.dts @@ -27,6 +27,7 @@ emi1_rgmii = &hydra_mdio_rgmii; emi1_sgmii = &hydra_mdio_sgmii; emi2_xgmii = &hydra_mdio_xgmii; + spi0 = &espi0; }; soc: soc@ffe000000 { @@ -142,4 +143,16 @@ }; }; +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + /* input clock */ + spi-max-frequency = <10000000>; + }; +}; + /include/ "p3041si-post.dtsi" diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi index 4a80561e188..8ab5cf541a0 100644 --- a/arch/powerpc/dts/p4080.dtsi +++ b/arch/powerpc/dts/p4080.dtsi @@ -80,6 +80,15 @@ clock-frequency = <0x0>; }; + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + esdhc: esdhc@114000 { compatible = "fsl,esdhc"; reg = <0x114000 0x1000>; diff --git a/arch/powerpc/dts/p4080ds.dts b/arch/powerpc/dts/p4080ds.dts index 53c51d479c4..d5618f1e49a 100644 --- a/arch/powerpc/dts/p4080ds.dts +++ b/arch/powerpc/dts/p4080ds.dts @@ -27,6 +27,7 @@ emi1_rgmii = &p4080mdio0; emi2_slot4 = &p4080xmdio1; emi2_slot5 = &p4080xmdio3; + spi0 = &espi0; }; soc: soc@ffe000000 { @@ -204,4 +205,16 @@ }; }; +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + /* input clock */ + spi-max-frequency = <10000000>; + }; +}; + /include/ "p4080si-post.dtsi" diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi index 45988574a2e..10402cf2224 100644 --- a/arch/powerpc/dts/p5040.dtsi +++ b/arch/powerpc/dts/p5040.dtsi @@ -59,6 +59,15 @@ clock-frequency = <0x0>; }; + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + usb@210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>; diff --git a/arch/powerpc/dts/p5040ds.dts b/arch/powerpc/dts/p5040ds.dts index 6ebc801a451..c2ec765d3e4 100644 --- a/arch/powerpc/dts/p5040ds.dts +++ b/arch/powerpc/dts/p5040ds.dts @@ -39,6 +39,7 @@ hydra_sg_slot6 = &hydra_sg_slot6; hydra_xg_slot1 = &hydra_xg_slot1; hydra_xg_slot2 = &hydra_xg_slot2; + spi0 = &espi0; }; soc: soc@ffe000000 { @@ -265,4 +266,16 @@ }; }; +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + /* input clock */ + spi-max-frequency = <10000000>; + }; +}; + /include/ "p5040si-post.dtsi" diff --git a/arch/powerpc/dts/pq3-etsec1-0.dtsi b/arch/powerpc/dts/pq3-etsec1-0.dtsi new file mode 100644 index 00000000000..8800243f349 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-0.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>; +}; + +mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x24520 0x20>; +}; diff --git a/arch/powerpc/dts/pq3-etsec1-1.dtsi b/arch/powerpc/dts/pq3-etsec1-1.dtsi new file mode 100644 index 00000000000..2bc62d1a575 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-1.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>; +}; + +mdio@25520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x25520 0x20>; +}; diff --git a/arch/powerpc/dts/pq3-etsec1-2.dtsi b/arch/powerpc/dts/pq3-etsec1-2.dtsi new file mode 100644 index 00000000000..d45865fe03a --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-2.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@26000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <2>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + ranges = <0x0 0x26000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>; +}; + +mdio@26520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x26520 0x20>; +}; diff --git a/arch/powerpc/dts/pq3-etsec1-3.dtsi b/arch/powerpc/dts/pq3-etsec1-3.dtsi new file mode 100644 index 00000000000..853a27359d9 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-3.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@27000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <3>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x27000 0x1000>; + ranges = <0x0 0x27000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>; +}; + +mdio@27520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x27520 0x20>; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-0.dtsi new file mode 100644 index 00000000000..f9d3d046505 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-0.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +mdio@24000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-mdio"; + reg = <0x24000 0x1000 0xb0030 0x4>; +}; + +ethernet@b0000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0xb0000 0x1000>; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group@b0000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb0000 0x1000>; + interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-1.dtsi new file mode 100644 index 00000000000..6c014819093 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-1.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +mdio@25000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-tbi"; + reg = <0x25000 0x1000 0xb1030 0x4>; +}; + +ethernet@b1000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0xb1000 0x1000>; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group@b1000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb1000 0x1000>; + interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-2.dtsi new file mode 100644 index 00000000000..2a597c0db64 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-2.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +mdio@26000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-tbi"; + reg = <0x26000 0x1000 0xb1030 0x4>; +}; + +ethernet@b2000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0xb2000 0x1000>; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group@b2000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb2000 0x1000>; + interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi new file mode 100644 index 00000000000..16752a7c45a --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&enet0_grp2 { + queue-group@b4000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb4000 0x1000>; + interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi new file mode 100644 index 00000000000..0464938424a --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&enet1_grp2 { + queue-group@b5000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb5000 0x1000>; + interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi new file mode 100644 index 00000000000..fe8003c44a9 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&enet2_grp2 { + queue-group@b6000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb6000 0x1000>; + interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/t1024rdb.dts b/arch/powerpc/dts/t1024rdb.dts index 32aaa4adaa4..eeba99f84de 100644 --- a/arch/powerpc/dts/t1024rdb.dts +++ b/arch/powerpc/dts/t1024rdb.dts @@ -17,6 +17,7 @@ aliases { sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4; + spi0 = &espi0; }; soc: soc@ffe000000 { @@ -63,7 +64,18 @@ }; }; }; +}; +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + /* input clock */ + spi-max-frequency = <10000000>; + }; }; #include "t1024si-post.dtsi" diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi index 521825d85a4..cf8962abe25 100644 --- a/arch/powerpc/dts/t102x.dtsi +++ b/arch/powerpc/dts/t102x.dtsi @@ -49,6 +49,15 @@ clock-frequency = <0x0>; }; + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + usb0@210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>; diff --git a/arch/powerpc/dts/t1042d4rdb.dts b/arch/powerpc/dts/t1042d4rdb.dts index 16a8ed4c797..3584c06aa8d 100644 --- a/arch/powerpc/dts/t1042d4rdb.dts +++ b/arch/powerpc/dts/t1042d4rdb.dts @@ -14,4 +14,19 @@ #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; + + aliases { + spi0 = &espi0; + }; +}; + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; }; diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi index 0a08a69f31a..2c7e5b47185 100644 --- a/arch/powerpc/dts/t104x.dtsi +++ b/arch/powerpc/dts/t104x.dtsi @@ -59,6 +59,15 @@ clock-frequency = <0x0>; }; + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + usb0@210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>; diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi index a9e9b404f66..7e446b18df6 100644 --- a/arch/powerpc/dts/t2080.dtsi +++ b/arch/powerpc/dts/t2080.dtsi @@ -69,6 +69,16 @@ voltage-ranges = <1800 1800 3300 3300>; }; + espi0: spi@110000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc8536-espi"; + reg = <0x110000 0x1000>; + interrupts = <53 0x2 0 0>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + usb0: usb@210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>; diff --git a/arch/powerpc/dts/t2080qds.dts b/arch/powerpc/dts/t2080qds.dts index 1819a081dd6..f9e786b2395 100644 --- a/arch/powerpc/dts/t2080qds.dts +++ b/arch/powerpc/dts/t2080qds.dts @@ -14,4 +14,37 @@ #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; + + aliases { + spi0 = &espi0; + }; +}; + +&espi0 { + + status = "okay"; + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */ + reg = <0>; + spi-max-frequency = <10000000>; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25wf040", "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <10000000>; + }; + + flash@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "eon,en25s64", "jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <10000000>; + }; + }; diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts index 49c1765b299..34ec6a74cb1 100644 --- a/arch/powerpc/dts/t2080rdb.dts +++ b/arch/powerpc/dts/t2080rdb.dts @@ -14,4 +14,19 @@ #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; + + aliases { + spi0 = &espi0; + }; +}; + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; /* 16MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; }; diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi index 9b5902fe9e2..498da4f795b 100644 --- a/arch/powerpc/dts/t4240.dtsi +++ b/arch/powerpc/dts/t4240.dtsi @@ -99,6 +99,15 @@ clock-frequency = <0x0>; }; + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + usb@210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>; diff --git a/arch/powerpc/dts/t4240rdb.dts b/arch/powerpc/dts/t4240rdb.dts index f67d7ce2ae6..635065a0368 100644 --- a/arch/powerpc/dts/t4240rdb.dts +++ b/arch/powerpc/dts/t4240rdb.dts @@ -14,4 +14,19 @@ #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; + + aliases { + spi0 = &espi0; + }; +}; + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; }; diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 8c8ed99cd34..b903e6ec8dc 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -298,8 +298,8 @@ void boot_prep_vxworks(bootm_headers_t *images) if (!images->ft_addr) return; - base = (u64)gd->bd->bi_memstart; - size = (u64)gd->bd->bi_memsize; + base = (u64)gd->ram_base; + size = (u64)gd->ram_size; off = fdt_path_offset(images->ft_addr, "/memory"); if (off < 0) |