diff options
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r-- | arch/powerpc/include/asm/apm821xx.h | 59 | ||||
-rw-r--r-- | arch/powerpc/include/asm/ppc4xx-ebc.h | 3 | ||||
-rw-r--r-- | arch/powerpc/include/asm/ppc4xx-isram.h | 10 | ||||
-rw-r--r-- | arch/powerpc/include/asm/ppc4xx-sdram.h | 12 | ||||
-rw-r--r-- | arch/powerpc/include/asm/ppc4xx-uic.h | 5 | ||||
-rw-r--r-- | arch/powerpc/include/asm/ppc4xx.h | 4 |
6 files changed, 12 insertions, 81 deletions
diff --git a/arch/powerpc/include/asm/apm821xx.h b/arch/powerpc/include/asm/apm821xx.h deleted file mode 100644 index d027866d3d9..00000000000 --- a/arch/powerpc/include/asm/apm821xx.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri <tmarri@apm.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _APM821XX_H_ -#define _APM821XX_H_ - -#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ - -/* Memory mapped registers */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) - -#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) - -#define SDR0_SRST0_DMC 0x00200000 -#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ - -/* AHB config. */ -#define AHB_TOP 0xA4 -#define AHB_BOT 0xA5 - -/* clk divisors */ -#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ -#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ -#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ -#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ -#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ -#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ -#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000/* PLB Early Clk Div*/ -#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ -#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ - -/* - + * Clocking Controller - + */ -#define CPR0_CLKUPD 0x0020 -#define CPR0_PLLC 0x0040 -#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) -#define CPR0_PLLD 0x0060 -#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) -#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) -#define CPR0_CPUD 0x0080 -#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) -#define CPR0_PLB2D 0x00a0 -#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) -#define CPR0_OPBD 0x00c0 -#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) -#define CPR0_PERD 0x00e0 -#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) -#define CPR0_DDR2D 0x0100 -#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) -#define CLK_ICFG 0x0140 - -#endif /* _APM821XX_H_ */ diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h index 07a3fe033fc..952783f9619 100644 --- a/arch/powerpc/include/asm/ppc4xx-ebc.h +++ b/arch/powerpc/include/asm/ppc4xx-ebc.h @@ -53,8 +53,7 @@ #define EBC_NUM_BANKS 6 #endif -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define EBC_NUM_BANKS 3 #endif diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h index 4d1106b1242..2ae399f2488 100644 --- a/arch/powerpc/include/asm/ppc4xx-isram.h +++ b/arch/powerpc/include/asm/ppc4xx-isram.h @@ -8,8 +8,7 @@ /* * Internal SRAM */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define ISRAM0_DCR_BASE 0x380 #else #define ISRAM0_DCR_BASE 0x020 @@ -26,8 +25,7 @@ #define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ #define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) #define ISRAM1_DCR_BASE 0x0B0 #define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ #define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ @@ -41,8 +39,6 @@ #if defined(CONFIG_460EX) || defined(CONFIG_460GT) #define ISRAM1_SIZE 0x0984 /* OCM size 64k */ -#elif defined(CONFIG_APM821XX) -#define ISRAM1_SIZE 0x0784 /* OCM size 32k */ #endif /* @@ -51,7 +47,7 @@ #if defined (CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) #define L2_CACHE_BASE 0x030 #define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index 12d6d038c7b..e6fed83bf1c 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -276,7 +276,7 @@ */ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) @@ -349,7 +349,7 @@ /* * Memory controller registers */ -#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) +#if defined(CONFIG_405EX) #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ #define SDRAM_BEARL 0x02 /* PLB bus error address low */ @@ -359,9 +359,9 @@ #define SDRAM_PLBOPT 0x08 /* PLB slave options */ #define SDRAM_PUABA 0x09 /* PLB upper address base */ #define SDRAM_MCSTAT 0x1F /* memory controller status */ -#else /* CONFIG_405EX || CONFIG_APM821XX */ +#else /* CONFIG_405EX */ #define SDRAM_MCSTAT 0x14 /* memory controller status */ -#endif /* CONFIG_405EX || CONFIG_APM821XX */ +#endif /* CONFIG_405EX */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ @@ -407,12 +407,12 @@ #define SDRAM_MEMODE 0x89 /* memory extended mode */ #define SDRAM_ECCES 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ -#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX) +#if !defined(CONFIG_405EX) #define SDRAM_RID 0xA8 /* revision ID */ #endif #define SDRAM_FCSR 0xB0 /* feedback calibration status */ #define SDRAM_RTSR 0xB1 /* run time status tracking */ -#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) +#if defined(CONFIG_405EX) #define SDRAM_RID 0xF8 /* revision ID */ #endif diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h index 05b4690a5c1..58e65c1336f 100644 --- a/arch/powerpc/include/asm/ppc4xx-uic.h +++ b/arch/powerpc/include/asm/ppc4xx-uic.h @@ -15,7 +15,7 @@ */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) #define UIC_MAX 4 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) @@ -236,8 +236,7 @@ #define VECNUM_ETH0 (32 + 28) #endif /* CONFIG_440SPE */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) /* UIC 0 */ #define VECNUM_UIC2NCI 10 #define VECNUM_UIC2CI 11 diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h index e6a3bff079e..b8b0ff9f25b 100644 --- a/arch/powerpc/include/asm/ppc4xx.h +++ b/arch/powerpc/include/asm/ppc4xx.h @@ -56,10 +56,6 @@ #include <asm/ppc460sx.h> #endif -#if defined(CONFIG_APM821XX) -#include <asm/apm821xx.h> -#endif - /* * Common registers for all SoC's */ |