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-rw-r--r--arch/powerpc/cpu/mpc83xx/Kconfig8
-rw-r--r--arch/powerpc/cpu/mpc83xx/Makefile2
-rw-r--r--arch/powerpc/cpu/mpc83xx/cpu_init.c11
-rw-r--r--arch/powerpc/cpu/mpc83xx/fdt.c2
-rw-r--r--arch/powerpc/cpu/mpc83xx/qe_io.c98
-rw-r--r--arch/powerpc/cpu/mpc83xx/traps.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig61
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c4
-rw-r--r--arch/powerpc/cpu/mpc85xx/traps.c2
-rw-r--r--arch/powerpc/cpu/mpc86xx/fdt.c4
-rw-r--r--arch/powerpc/cpu/mpc86xx/traps.c2
-rw-r--r--arch/powerpc/cpu/mpc8xx/fdt.c2
-rw-r--r--arch/powerpc/cpu/mpc8xxx/cpu.c2
13 files changed, 98 insertions, 102 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 18808da37dd..2bae08e2786 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -101,34 +101,42 @@ config TARGET_IDS8313
config TARGET_KMETER1
bool "Support kmeter1"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMCOGE5NE
bool "Support kmcoge5ne"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMTEGR1
bool "Support kmtegr1"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_TUXX1
bool "Support tuxx1"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMSUPX5
bool "Support kmsupx5"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_TUGE1
bool "Support tuge1"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMOPTI2
bool "Support kmopti2"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMTEPR2
bool "Support kmtepr2"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_TQM834X
bool "Support TQM834x"
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index 304029977e5..aeb42b109d0 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -27,7 +27,9 @@ obj-y += cpu_init.o
obj-y += speed.o
obj-y += interrupts.o
obj-y += ecc.o
+ifndef CONFIG_PINCTRL
obj-$(CONFIG_QE) += qe_io.o
+endif
obj-$(CONFIG_FSL_SERDES) += serdes.o
ifndef CONFIG_ARCH_MPC8308
obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 438b14b162e..840f907acb8 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -9,10 +9,14 @@
#include <ioports.h>
#include <asm/io.h>
#include <asm/processor.h>
+#include <fsl_qe.h>
#ifdef CONFIG_USB_EHCI_FSL
#include <usb/ehci-ci.h>
#endif
#include <linux/delay.h>
+#ifdef CONFIG_QE
+#include <fsl_qe.h>
+#endif
#include "lblaw/lblaw.h"
#include "elbc/elbc.h"
@@ -26,9 +30,8 @@ DECLARE_GLOBAL_DATA_PTR;
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
int open_drain, int assign);
-extern void qe_init(uint qe_base);
-extern void qe_reset(void);
+#if !defined(CONFIG_PINCTRL)
static void config_qe_ioports(void)
{
u8 port, pin;
@@ -45,6 +48,7 @@ static void config_qe_ioports(void)
}
}
#endif
+#endif
/*
* Breathe some life into the CPU...
@@ -191,10 +195,13 @@ void cpu_init_f (volatile immap_t * im)
__raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
#endif
+#if !defined(CONFIG_PINCTRL)
#ifdef CONFIG_QE
/* Config QE ioports */
config_qe_ioports();
#endif
+#endif
+
/* Set up preliminary BR/OR regs */
init_early_memctl_regs();
diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c
index ebdedb28889..4ea7b27ef41 100644
--- a/arch/powerpc/cpu/mpc83xx/fdt.c
+++ b/arch/powerpc/cpu/mpc83xx/fdt.c
@@ -121,7 +121,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
"clock-frequency", get_serial_clock(), 1);
#endif
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+ fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
(defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
diff --git a/arch/powerpc/cpu/mpc83xx/qe_io.c b/arch/powerpc/cpu/mpc83xx/qe_io.c
index 88aa6895511..52360703a7d 100644
--- a/arch/powerpc/cpu/mpc83xx/qe_io.c
+++ b/arch/powerpc/cpu/mpc83xx/qe_io.c
@@ -12,57 +12,93 @@
#include <asm/immap_83xx.h>
#define NUM_OF_PINS 32
-void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
+
+/** qe_cfg_iopin configure one io pin setting
+ *
+ * @par_io: pointer to parallel I/O base
+ * @port: io pin port
+ * @pin: io pin number which get configured
+ * @dir: direction of io pin 2 bits valid
+ * 00 = pin disabled
+ * 01 = output
+ * 10 = input
+ * 11 = pin is I/O
+ * @open_drain: is pin open drain
+ * @assign: pin assignment registers select the function of the pin
+ */
+static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
+ int open_drain, int assign)
{
- u32 pin_2bit_mask;
- u32 pin_2bit_dir;
- u32 pin_2bit_assign;
- u32 pin_1bit_mask;
- u32 tmp_val;
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio;
+ u32 dbit_mask;
+ u32 dbit_dir;
+ u32 dbit_asgn;
+ u32 bit_mask;
+ u32 tmp_val;
+ int offset;
+
+ offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
/* Calculate pin location and 2bit mask and dir */
- pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
- pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
+ dbit_mask = (u32)(0x3 << offset);
+ dbit_dir = (u32)(dir << offset);
/* Setup the direction */
- tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
+ tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
in_be32(&par_io->ioport[port].dir2) :
in_be32(&par_io->ioport[port].dir1);
- if (pin > (NUM_OF_PINS/2) -1) {
- out_be32(&par_io->ioport[port].dir2, ~pin_2bit_mask & tmp_val);
- out_be32(&par_io->ioport[port].dir2, pin_2bit_dir | tmp_val);
+ if (pin > (NUM_OF_PINS / 2) - 1) {
+ out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
+ out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
} else {
- out_be32(&par_io->ioport[port].dir1, ~pin_2bit_mask & tmp_val);
- out_be32(&par_io->ioport[port].dir1, pin_2bit_dir | tmp_val);
+ out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
+ out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
}
/* Calculate pin location for 1bit mask */
- pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1)));
+ bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
/* Setup the open drain */
tmp_val = in_be32(&par_io->ioport[port].podr);
- if (open_drain) {
- out_be32(&par_io->ioport[port].podr, pin_1bit_mask | tmp_val);
- } else {
- out_be32(&par_io->ioport[port].podr, ~pin_1bit_mask & tmp_val);
- }
+ if (open_drain)
+ out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
+ else
+ out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
/* Setup the assignment */
- tmp_val = (pin > (NUM_OF_PINS/2) - 1) ?
- in_be32(&par_io->ioport[port].ppar2):
+ tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
+ in_be32(&par_io->ioport[port].ppar2) :
in_be32(&par_io->ioport[port].ppar1);
- pin_2bit_assign = (u32)(assign
- << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2));
+ dbit_asgn = (u32)(assign << offset);
/* Clear and set 2 bits mask */
- if (pin > (NUM_OF_PINS/2) - 1) {
- out_be32(&par_io->ioport[port].ppar2, ~pin_2bit_mask & tmp_val);
- out_be32(&par_io->ioport[port].ppar2, pin_2bit_assign | tmp_val);
+ if (pin > (NUM_OF_PINS / 2) - 1) {
+ out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
+ out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
} else {
- out_be32(&par_io->ioport[port].ppar1, ~pin_2bit_mask & tmp_val);
- out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val);
+ out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
+ out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
}
}
+
+#if !defined(CONFIG_PINCTRL)
+/** qe_config_iopin configure one io pin setting
+ *
+ * @port: io pin port
+ * @pin: io pin number which get configured
+ * @dir: direction of io pin 2 bits valid
+ * 00 = pin disabled
+ * 01 = output
+ * 10 = input
+ * 11 = pin is I/O
+ * @open_drain: is pin open drain
+ * @assign: pin assignment registers select the function of the pin
+ */
+void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio;
+
+ qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
+}
+#endif
diff --git a/arch/powerpc/cpu/mpc83xx/traps.c b/arch/powerpc/cpu/mpc83xx/traps.c
index c3cc119d654..ea8bc6c1528 100644
--- a/arch/powerpc/cpu/mpc83xx/traps.c
+++ b/arch/powerpc/cpu/mpc83xx/traps.c
@@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);
-#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
+#define END_OF_MEM (gd->ram_base + gd->ram_size)
/*
* Trap & Exception support
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 753d0750b2b..54c7fd9522a 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -40,14 +40,6 @@ config TARGET_P4080DS
imply CMD_SATA
imply PANIC_HANG
-config TARGET_P5020DS
- bool "Support P5020DS"
- select PHYS_64BIT
- select ARCH_P5020
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- imply CMD_SATA
- imply PANIC_HANG
-
config TARGET_P5040DS
bool "Support P5040DS"
select PHYS_64BIT
@@ -109,22 +101,6 @@ config TARGET_P1010RDB_PB
imply CMD_SATA
imply PANIC_HANG
-config TARGET_P1023RDB
- bool "Support P1023RDB"
- select ARCH_P1023
- select FSL_DDR_INTERACTIVE
- imply CMD_EEPROM
- imply PANIC_HANG
-
-config TARGET_P1020MBG
- bool "Support P1020MBG-PC"
- select SUPPORT_SPL
- select SUPPORT_TPL
- select ARCH_P1020
- imply CMD_EEPROM
- imply CMD_SATA
- imply PANIC_HANG
-
config TARGET_P1020RDB_PC
bool "Support P1020RDB-PC"
select SUPPORT_SPL
@@ -143,42 +119,6 @@ config TARGET_P1020RDB_PD
imply CMD_SATA
imply PANIC_HANG
-config TARGET_P1020UTM
- bool "Support P1020UTM"
- select SUPPORT_SPL
- select SUPPORT_TPL
- select ARCH_P1020
- imply CMD_EEPROM
- imply CMD_SATA
- imply PANIC_HANG
-
-config TARGET_P1021RDB
- bool "Support P1021RDB"
- select SUPPORT_SPL
- select SUPPORT_TPL
- select ARCH_P1021
- imply CMD_EEPROM
- imply CMD_SATA
- imply PANIC_HANG
-
-config TARGET_P1024RDB
- bool "Support P1024RDB"
- select SUPPORT_SPL
- select SUPPORT_TPL
- select ARCH_P1024
- imply CMD_EEPROM
- imply CMD_SATA
- imply PANIC_HANG
-
-config TARGET_P1025RDB
- bool "Support P1025RDB"
- select SUPPORT_SPL
- select SUPPORT_TPL
- select ARCH_P1025
- imply CMD_EEPROM
- imply CMD_SATA
- imply SATA_SIL
-
config TARGET_P2020RDB
bool "Support P2020RDB-PC"
select SUPPORT_SPL
@@ -1506,7 +1446,6 @@ source "board/freescale/mpc8568mds/Kconfig"
source "board/freescale/mpc8569mds/Kconfig"
source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
-source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 9569c1a64b8..0d8353ceb26 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -672,10 +672,10 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
"clock-frequency", get_bus_freq(0), 1);
#endif
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+ fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
#ifdef CONFIG_MP
- ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
+ ft_fixup_cpu(blob, (u64)gd->ram_base + (u64)gd->ram_size);
ft_fixup_num_cores(blob);
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c
index f37a45e2694..db6ed1fc92e 100644
--- a/arch/powerpc/cpu/mpc85xx/traps.c
+++ b/arch/powerpc/cpu/mpc85xx/traps.c
@@ -37,7 +37,7 @@ extern unsigned long search_exception_table(unsigned long);
* amount of memory on the system if we're unable to keep all
* the memory mapped in.
*/
-#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
+#define END_OF_MEM (gd->ram_base + get_effective_memsize())
static __inline__ void set_tsr(unsigned long val)
{
diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c
index 24e53115ecc..010b6d4fe60 100644
--- a/arch/powerpc/cpu/mpc86xx/fdt.c
+++ b/arch/powerpc/cpu/mpc86xx/fdt.c
@@ -8,6 +8,8 @@
#include <fdt_support.h>
#include <asm/mp.h>
+DECLARE_GLOBAL_DATA_PTR;
+
extern void ft_fixup_num_cores(void *blob);
extern void ft_srio_setup(void *blob);
@@ -27,7 +29,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+ fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "ns16550",
diff --git a/arch/powerpc/cpu/mpc86xx/traps.c b/arch/powerpc/cpu/mpc86xx/traps.c
index c0161e3379c..3ee0ec859cf 100644
--- a/arch/powerpc/cpu/mpc86xx/traps.c
+++ b/arch/powerpc/cpu/mpc86xx/traps.c
@@ -30,7 +30,7 @@ extern unsigned long search_exception_table(unsigned long);
* amount of memory on the system if we're unable to keep all
* the memory mapped in.
*/
-#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
+#define END_OF_MEM (gd->ram_base + get_effective_memsize())
/*
* Trap & Exception support
diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c
index 4d952a3882f..226e258f0ea 100644
--- a/arch/powerpc/cpu/mpc8xx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xx/fdt.c
@@ -25,5 +25,5 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
gd->arch.brg_clk, 1);
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+ fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
}
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 2b24e755faa..b2d1dc5b481 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -343,6 +343,7 @@ int fixup_cpu(void)
return 0;
}
+#ifndef CONFIG_DM_ETH
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
@@ -370,3 +371,4 @@ int cpu_eth_init(struct bd_info *bis)
#endif
return 0;
}
+#endif
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-30 14:01:13 +0000