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-rw-r--r--arch/mips/mach-octeon/Kconfig46
-rw-r--r--arch/mips/mach-octeon/Makefile10
-rw-r--r--arch/mips/mach-octeon/cache.c24
-rw-r--r--arch/mips/mach-octeon/clock.c14
-rw-r--r--arch/mips/mach-octeon/cpu.c66
-rw-r--r--arch/mips/mach-octeon/dram.c28
-rw-r--r--arch/mips/mach-octeon/include/ioremap.h30
-rw-r--r--arch/mips/mach-octeon/include/mach/cavm-reg.h17
-rw-r--r--arch/mips/mach-octeon/include/mach/clock.h12
-rw-r--r--arch/mips/mach-octeon/lowlevel_init.S19
10 files changed, 266 insertions, 0 deletions
diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig
new file mode 100644
index 0000000000..3c8ca8dd36
--- /dev/null
+++ b/arch/mips/mach-octeon/Kconfig
@@ -0,0 +1,46 @@
+menu "Octeon platforms"
+ depends on ARCH_OCTEON
+
+config SYS_SOC
+ string
+ default "octeon"
+
+config OCTEON_CN7XXX
+ bool "Octeon CN7XXX SoC"
+
+config OCTEON_CN70XX
+ bool "Octeon CN70XX SoC"
+ select OCTEON_CN7XXX
+
+config OCTEON_CN73XX
+ bool "Octeon CN73XX SoC"
+ select OCTEON_CN7XXX
+
+config OCTEON_CN78XX
+ bool "Octeon CN78XX SoC"
+ select OCTEON_CN7XXX
+
+choice
+ prompt "Octeon MIPS family select"
+
+config SOC_OCTEON3
+ bool "Octeon III family"
+ help
+ This selects the Octeon III SoC family CN70xx, CN73XX, CN78xx
+ and CNF75XX.
+
+endchoice
+
+config SYS_DCACHE_SIZE
+ default 32768
+
+config SYS_DCACHE_LINE_SIZE
+ default 128
+
+config SYS_ICACHE_SIZE
+ default 79872
+
+config SYS_ICACHE_LINE_SIZE
+ default 128
+
+endmenu
diff --git a/arch/mips/mach-octeon/Makefile b/arch/mips/mach-octeon/Makefile
new file mode 100644
index 0000000000..2e37ca572c
--- /dev/null
+++ b/arch/mips/mach-octeon/Makefile
@@ -0,0 +1,10 @@
+# (C) Copyright 2019 Marvell, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += lowlevel_init.o
+obj-y += cache.o
+obj-y += clock.o
+obj-y += cpu.o
+obj-y += dram.o
diff --git a/arch/mips/mach-octeon/cache.c b/arch/mips/mach-octeon/cache.c
new file mode 100644
index 0000000000..9a88bb97c7
--- /dev/null
+++ b/arch/mips/mach-octeon/cache.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include <cpu_func.h>
+
+/*
+ * The Octeon platform is cache coherent and cache flushes and invalidates
+ * are not needed. Define some platform specific empty flush_foo()
+ * functions here to overwrite the _weak common function as a no-op.
+ * This effectively disables all cache operations.
+ */
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+}
diff --git a/arch/mips/mach-octeon/clock.c b/arch/mips/mach-octeon/clock.c
new file mode 100644
index 0000000000..119b3ac50b
--- /dev/null
+++ b/arch/mips/mach-octeon/clock.c
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018, 2019 Marvell International Ltd.
+ */
+
+#include <asm/global_data.h>
+#include <mach/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong notrace get_tbclk(void)
+{
+ return gd->cpu_clk;
+}
diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c
new file mode 100644
index 0000000000..2680a2e6ed
--- /dev/null
+++ b/arch/mips/mach-octeon/cpu.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include <asm/global_data.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/io.h>
+#include <mach/clock.h>
+#include <mach/cavm-reg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int get_clocks(void)
+{
+ const u64 ref_clock = PLL_REF_CLK;
+ void __iomem *rst_boot;
+ u64 val;
+
+ rst_boot = ioremap(CAVM_RST_BOOT, 0);
+ val = ioread64(rst_boot);
+ gd->cpu_clk = ref_clock * FIELD_GET(RST_BOOT_C_MUL, val);
+ gd->bus_clk = ref_clock * FIELD_GET(RST_BOOT_PNR_MUL, val);
+
+ debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk);
+
+ return 0;
+}
+
+/* Early mach init code run from flash */
+int mach_cpu_init(void)
+{
+ void __iomem *mio_boot_reg_cfg0;
+
+ /* Remap boot-bus 0x1fc0.0000 -> 0x1f40.0000 */
+ /* ToDo: Move this to an early running bus (bootbus) DM driver */
+ mio_boot_reg_cfg0 = ioremap(CAVM_MIO_BOOT_REG_CFG0, 0);
+ clrsetbits_be64(mio_boot_reg_cfg0, 0xffff, 0x1f40);
+
+ /* Get clocks and store them in GD */
+ get_clocks();
+
+ return 0;
+}
+
+/**
+ * Returns number of cores
+ *
+ * @return number of CPU cores for the specified node
+ */
+static int cavm_octeon_num_cores(void)
+{
+ void __iomem *ciu_fuse;
+
+ ciu_fuse = ioremap(CAVM_CIU_FUSE, 0);
+ return fls64(ioread64(ciu_fuse) & 0xffffffffffff);
+}
+
+int print_cpuinfo(void)
+{
+ printf("SoC: Octeon CN73xx (%d cores)\n", cavm_octeon_num_cores());
+
+ return 0;
+}
diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c
new file mode 100644
index 0000000000..ff7a59f2ab
--- /dev/null
+++ b/arch/mips/mach-octeon/dram.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) Stefan Roese <sr@denx.de>
+ */
+
+#include <dm.h>
+#include <ram.h>
+#include <asm/global_data.h>
+#include <linux/compat.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ /*
+ * No DDR init yet -> run in L2 cache
+ */
+ gd->ram_size = (4 << 20);
+ gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->bd->bi_dram[1].size = 0;
+
+ return 0;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return gd->ram_top;
+}
diff --git a/arch/mips/mach-octeon/include/ioremap.h b/arch/mips/mach-octeon/include/ioremap.h
new file mode 100644
index 0000000000..59b75008a2
--- /dev/null
+++ b/arch/mips/mach-octeon/include/ioremap.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_OCTEON_IOREMAP_H
+#define __ASM_MACH_OCTEON_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
+ phys_addr_t size)
+{
+ return phys_addr;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+ unsigned long flags)
+{
+ return (void __iomem *)(XKPHYS | offset);
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+ return 0;
+}
+
+#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
+
+#endif /* __ASM_MACH_OCTEON_IOREMAP_H */
diff --git a/arch/mips/mach-octeon/include/mach/cavm-reg.h b/arch/mips/mach-octeon/include/mach/cavm-reg.h
new file mode 100644
index 0000000000..45850ea355
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cavm-reg.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef __CAVM_REG_H__
+
+/* Register offsets */
+#define CAVM_CIU_FUSE 0x00010100000001a0
+#define CAVM_MIO_BOOT_REG_CFG0 0x0001180000000000
+#define CAVM_RST_BOOT 0x0001180006001600
+
+/* Register bits */
+#define RST_BOOT_C_MUL GENMASK_ULL(36, 30)
+#define RST_BOOT_PNR_MUL GENMASK_ULL(29, 24)
+
+#endif /* __CAVM_REG_H__ */
diff --git a/arch/mips/mach-octeon/include/mach/clock.h b/arch/mips/mach-octeon/include/mach/clock.h
new file mode 100644
index 0000000000..85c8d3dc4f
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/clock.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018, 2019 Marvell International Ltd.
+ */
+
+#ifndef __CLOCK_H__
+
+/** System PLL reference clock */
+#define PLL_REF_CLK 50000000 /* 50 MHz */
+#define NS_PER_REF_CLK_TICK (1000000000 / PLL_REF_CLK)
+
+#endif /* __CLOCK_H__ */
diff --git a/arch/mips/mach-octeon/lowlevel_init.S b/arch/mips/mach-octeon/lowlevel_init.S
new file mode 100644
index 0000000000..d9aab38cde
--- /dev/null
+++ b/arch/mips/mach-octeon/lowlevel_init.S
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Stefan Roese <sr@denx.de>
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/cacheops.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+
+ .set noreorder
+
+LEAF(lowlevel_init)
+ jr ra
+ nop
+ END(lowlevel_init)
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-05 08:54:56 +0000