diff options
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/cpu/armv7/tegra3/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/tegra3/pinmux.c | 507 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-tegra3/pinmux.h | 610 |
3 files changed, 1118 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/tegra3/Makefile b/arch/arm/cpu/armv7/tegra3/Makefile index 1d5c6bc521f..0fe1db2a932 100644 --- a/arch/arm/cpu/armv7/tegra3/Makefile +++ b/arch/arm/cpu/armv7/tegra3/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS-y := board.o sys_info.o +COBJS-y := board.o pinmux.o sys_info.o COBJS := $(COBJS-y) diff --git a/arch/arm/cpu/armv7/tegra3/pinmux.c b/arch/arm/cpu/armv7/tegra3/pinmux.c new file mode 100644 index 00000000000..8a9f87a1b4c --- /dev/null +++ b/arch/arm/cpu/armv7/tegra3/pinmux.c @@ -0,0 +1,507 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Tegra3 pin multiplexing functions */ + +#include <asm/io.h> +#include <asm/arch-tegra/bitfield.h> +#include <asm/arch/tegra.h> +#include <asm/arch/pinmux.h> +#include <common.h> + +struct tegra_pingroup_desc { + const char *name; + enum pmux_func funcs[4]; + enum pmux_func func_safe; + enum pmux_vddio vddio; + enum pmux_pin_io io; +}; + +#define PMUX_MUXCTL_SHIFT 0 +#define PMUX_PULL_SHIFT 2 +#define PMUX_TRISTATE_SHIFT 4 +#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT) +#define PMUX_IO_SHIFT 5 +#define PMUX_OD_SHIFT 6 +#define PMUX_LOCK_SHIFT 7 +#define PMUX_IO_RESET_SHIFT 8 + +/* Convenient macro for defining pin group properties */ +#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \ + { \ + .vddio = PMUX_VDDIO_ ## vdd, \ + .funcs = { \ + PMUX_FUNC_ ## f0, \ + PMUX_FUNC_ ## f1, \ + PMUX_FUNC_ ## f2, \ + PMUX_FUNC_ ## f3, \ + }, \ + .func_safe = PMUX_FUNC_RSVD, \ + .io = PMUX_PIN_ ## iod, \ + } + +/* Input and output pins */ +#define PINI(pg_name, vdd, f0, f1, f2, f3) \ + PIN(pg_name, vdd, f0, f1, f2, f3, INPUT) +#define PINO(pg_name, vdd, f0, f1, f2, f3) \ + PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT) + +const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { + /* NAME VDD f0 f1 f2 f3 fSafe io */ + PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI), + PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI), + PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI), + PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI), + PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI), + PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI), + PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI), + PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI), + PINI(ULPI_CLK, BB, SPI1, RSVD, UARTD, ULPI), + PINI(ULPI_DIR, BB, SPI1, RSVD, UARTD, ULPI), + PINI(ULPI_NXT, BB, SPI1, RSVD, UARTD, ULPI), + PINI(ULPI_STP, BB, SPI1, RSVD, UARTD, ULPI), + PINI(DAP3_FS, BB, I2S2, RSVD1, DISPA, DISPB), + PINI(DAP3_DIN, BB, I2S2, RSVD1, DISPA, DISPB), + PINI(DAP3_DOUT, BB, I2S2, RSVD1, DISPA, DISPB), + PINI(DAP3_SCLK, BB, I2S2, RSVD1, DISPA, DISPB), + PINI(GPIO_PV0, BB, RSVD, RSVD, RSVD, RSVD), + PINI(GPIO_PV1, BB, RSVD, RSVD, RSVD, RSVD), + PINI(SDMMC1_CLK, SDMMC1, SDMMC1, RSVD1, RSVD2, BAD), + PINI(SDMMC1_CMD, SDMMC1, SDMMC1, RSVD1, RSVD2, BAD), + PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, RSVD1, UARTE, BAD), + PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, RSVD1, UARTE, BAD), + PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, RSVD1, UARTE, BAD), + PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD1, UARTE, BAD), + PINI(GPIO_PV2, SDMMC1, OWR, RSVD1, RSVD2, RSVD3), + PINI(GPIO_PV3, SDMMC1, BAD, RSVD1, RSVD2, RSVD3), + PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD1, RSVD2, RSVD3), + PINI(CLK2_REQ, SDMMC1, DAP, RSVD1, RSVD2, RSVD3), + PINO(LCD_PWR1, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_PWR2, LCD, DISPA, DISPB, SPI5, BAD), + PINO(LCD_SDIN, LCD, DISPA, DISPB, SPI5, RSVD), + PINO(LCD_SDOUT, LCD, DISPA, DISPB, SPI5, BAD), + PINO(LCD_WR_N, LCD, DISPA, DISPB, SPI5, BAD), + PINO(LCD_CS0_N, LCD, DISPA, DISPB, SPI5, RSVD), + PINO(LCD_DC0, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_SCK, LCD, DISPA, DISPB, SPI5, BAD), + PINO(LCD_PWR0, LCD, DISPA, DISPB, SPI5, BAD), + PINO(LCD_PCLK, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_DE, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_HSYNC, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_VSYNC, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D0, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D1, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D2, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D3, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D4, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D5, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D6, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D7, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D8, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D9, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D10, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D11, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D12, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D13, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D14, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D15, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D16, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D17, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D18, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D19, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D20, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D21, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D22, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_D23, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_CS1_N, LCD, DISPA, DISPB, SPI5, RSVD2), + PINO(LCD_M1, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINO(LCD_DC1, LCD, DISPA, DISPB, RSVD1, RSVD2), + PINI(HDMI_INT, LCD, RSVD, RSVD, RSVD, RSVD), + PINI(DDC_SCL, LCD, I2C4, RSVD1, RSVD2, RSVD3), + PINI(DDC_SDA, LCD, I2C4, RSVD1, RSVD2, RSVD3), + PINI(CRT_HSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3), + PINI(CRT_VSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3), + PINI(VI_D0, VI, BAD, RSVD1, VI, RSVD2), + PINI(VI_D1, VI, BAD, SDMMC2, VI, RSVD1), + PINI(VI_D2, VI, BAD, SDMMC2, VI, RSVD1), + PINI(VI_D3, VI, BAD, SDMMC2, VI, RSVD1), + PINI(VI_D4, VI, BAD, SDMMC2, VI, RSVD1), + PINI(VI_D5, VI, BAD, SDMMC2, VI, RSVD1), + PINI(VI_D6, VI, BAD, SDMMC2, VI, RSVD1), + PINI(VI_D7, VI, BAD, SDMMC2, VI, RSVD1), + PINI(VI_D8, VI, BAD, SDMMC2, VI, RSVD1), + PINI(VI_D9, VI, BAD, SDMMC2, VI, RSVD1), + PINI(VI_D10, VI, BAD, RSVD1, VI, RSVD2), + PINI(VI_D11, VI, BAD, RSVD1, VI, RSVD2), + PINI(VI_PCLK, VI, RSVD1, SDMMC2, VI, RSVD2), + PINI(VI_MCLK, VI, VI, BAD, BAD, BAD), + PINI(VI_VSYNC, VI, BAD, RSVD1, VI, RSVD2), + PINI(VI_HSYNC, VI, BAD, RSVD1, VI, RSVD2), + PINI(UART2_RXD, UART, IRDA, SPDIF, UARTA, SPI4), + PINI(UART2_TXD, UART, IRDA, SPDIF, UARTA, SPI4), + PINI(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4), + PINI(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4), + PINI(UART3_TXD, UART, UARTC, RSVD1, GMI, RSVD2), + PINI(UART3_RXD, UART, UARTC, RSVD1, GMI, RSVD2), + PINI(UART3_CTS_N, UART, UARTC, RSVD1, GMI, RSVD2), + PINI(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD2), + PINI(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD1), + PINI(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD2), + PINI(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD2), + PINI(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD1), + PINI(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD1), + PINI(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD1), + PINI(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD1), + PINI(GEN1_I2C_SDA, UART, I2C1, RSVD1, RSVD2, RSVD3), + PINI(GEN1_I2C_SCL, UART, I2C1, RSVD1, RSVD2, RSVD3), + PINI(DAP4_FS, UART, I2S3, RSVD1, GMI, RSVD2), + PINI(DAP4_DIN, UART, I2S3, RSVD1, GMI, RSVD2), + PINI(DAP4_DOUT, UART, I2S3, RSVD1, GMI, RSVD2), + PINI(DAP4_SCLK, UART, I2S3, RSVD1, GMI, RSVD2), + PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD1, RSVD2, RSVD3), + PINI(CLK3_REQ, UART, DEV3, RSVD1, RSVD2, RSVD3), + PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT), + PINI(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, BAD), + PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV), + PINI(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT), + PINI(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA), + PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT), + PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD2), + PINI(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD2), + PINI(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD2), + PINI(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD2), + PINI(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD2), + PINI(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT), + PINI(GMI_A17, GMI, UARTD, SPI4, GMI, BAD), + PINI(GMI_A18, GMI, UARTD, SPI4, GMI, BAD), + PINI(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD3), + PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD3), + PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD3), + PINI(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD3), + PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD3), + PINI(GEN2_I2C_SCL, GMI, I2C2, BAD, GMI, RSVD3), + PINI(GEN2_I2C_SDA, GMI, I2C2, BAD, GMI, RSVD3), + PINI(SDMMC4_CLK, SDMMC4, BAD, NAND, GMI, SDMMC4), + PINI(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDMMC4), + PINI(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDMMC4), + PINI(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDMMC4), + PINI(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDMMC4), + PINI(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDMMC4), + PINI(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDMMC4), + PINI(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDMMC4), + PINI(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDMMC4), + PINI(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDMMC4), + PINI(SDMMC4_RST_N, SDMMC4, VGP6, RSVD1, RSVD2, POPSDMMC4), + PINI(CAM_MCLK, CAM, VI, BAD, VI_ALT2, POPSDMMC4), + PINI(GPIO_PCC1, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4), + PINI(GPIO_PBB0, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4), + PINI(CAM_I2C_SCL, CAM, BAD, I2C3, RSVD2, POPSDMMC4), + PINI(CAM_I2C_SDA, CAM, BAD, I2C3, RSVD2, POPSDMMC4), + PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, POPSDMMC4), + PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, POPSDMMC4), + PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, POPSDMMC4), + PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, POPSDMMC4), + PINI(GPIO_PBB7, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4), + PINI(GPIO_PCC2, CAM, I2S4, RSVD1, RSVD2, RSVD3), + PINI(JTAG_RTCK, SYS, RTCK, RSVD1, RSVD2, RSVD3), + PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD1, RSVD2, RSVD3), + PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD1, RSVD2, RSVD3), + PINI(KB_ROW0, SYS, KBC, BAD, RSVD2, RSVD3), + PINI(KB_ROW1, SYS, KBC, BAD, RSVD2, RSVD3), + PINI(KB_ROW2, SYS, KBC, BAD, RSVD2, RSVD3), + PINI(KB_ROW3, SYS, KBC, BAD, RSVD2, BAD), + PINI(KB_ROW4, SYS, KBC, BAD, TRACE, RSVD3), + PINI(KB_ROW5, SYS, KBC, BAD, TRACE, OWR), + PINI(KB_ROW6, SYS, KBC, BAD, SDMMC2, BAD), + PINI(KB_ROW7, SYS, KBC, BAD, SDMMC2, BAD), + PINI(KB_ROW8, SYS, KBC, BAD, SDMMC2, BAD), + PINI(KB_ROW9, SYS, KBC, BAD, SDMMC2, BAD), + PINI(KB_ROW10, SYS, KBC, BAD, SDMMC2, BAD), + PINI(KB_ROW11, SYS, KBC, BAD, SDMMC2, BAD), + PINI(KB_ROW12, SYS, KBC, BAD, SDMMC2, BAD), + PINI(KB_ROW13, SYS, KBC, BAD, SDMMC2, BAD), + PINI(KB_ROW14, SYS, KBC, BAD, SDMMC2, BAD), + PINI(KB_ROW15, SYS, KBC, BAD, SDMMC2, BAD), + PINI(KB_COL0, SYS, KBC, BAD, TRACE, BAD), + PINI(KB_COL1, SYS, KBC, BAD, TRACE, BAD), + PINI(KB_COL2, SYS, KBC, BAD, TRACE, RSVD), + PINI(KB_COL3, SYS, KBC, BAD, TRACE, RSVD), + PINI(KB_COL4, SYS, KBC, BAD, TRACE, RSVD), + PINI(KB_COL5, SYS, KBC, BAD, TRACE, RSVD), + PINI(KB_COL6, SYS, KBC, BAD, TRACE, BAD), + PINI(KB_COL7, SYS, KBC, BAD, TRACE, BAD), + PINI(CLK_32K_OUT, SYS, BLINK, RSVD1, RSVD2, RSVD3), + PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD1, RSVD2, RSVD3), + PINI(CORE_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD), + PINI(CPU_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD), + PINI(PWR_INT_N, SYS, RSVD, RSVD, RSVD, RSVD), + PINI(CLK_32K_IN, SYS, RSVD, RSVD, RSVD, RSVD), + PINI(OWR, SYS, OWR, RSVD, RSVD, RSVD), + PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDMMC2), + PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDMMC2), + PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDMMC2), + PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDMMC2), + PINI(CLK1_REQ, AUDIO, DAP, HDA, RSVD2, RSVD3), + PINI(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD1, RSVD2, RSVD3), + PINI(SPDIF_IN, AUDIO, SPDIF, HDA, BAD, DAPSDMMC2), + PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD1, BAD, DAPSDMMC2), + PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD2, GMI), + PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD2, GMI), + PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD2, GMI), + PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD2, GMI), + PINI(SPI2_MOSI, AUDIO, SPI6, SPI2, BAD, GMI), + PINI(SPI2_MISO, AUDIO, SPI6, SPI2, BAD, GMI), + PINI(SPI2_CS0_N, AUDIO, SPI6, SPI2, BAD, GMI), + PINI(SPI2_SCK, AUDIO, SPI6, SPI2, BAD, GMI), + PINI(SPI1_MOSI, AUDIO, SPI2, SPI1, BAD, GMI), + PINI(SPI1_SCK, AUDIO, SPI2, SPI1, BAD, GMI), + PINI(SPI1_CS0_N, AUDIO, SPI2, SPI1, BAD, GMI), + PINI(SPI1_MISO, AUDIO, BAD, SPI1, BAD, RSVD3), + PINI(SPI2_CS1_N, AUDIO, BAD, SPI2, BAD, BAD), + PINI(SPI2_CS2_N, AUDIO, BAD, SPI2, BAD, BAD), + PINI(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDMMC3, BAD), + PINI(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDMMC3, BAD), + PINI(SDMMC3_DAT0, SDMMC3, RSVD0, RSVD1, SDMMC3, BAD), + PINI(SDMMC3_DAT1, SDMMC3, RSVD0, RSVD1, SDMMC3, BAD), + PINI(SDMMC3_DAT2, SDMMC3, RSVD0, PWM1, SDMMC3, BAD), + PINI(SDMMC3_DAT3, SDMMC3, RSVD0, PWM0, SDMMC3, BAD), + PINI(SDMMC3_DAT4, SDMMC3, PWM1, BAD, SDMMC3, BAD), + PINI(SDMMC3_DAT5, SDMMC3, PWM0, BAD, SDMMC3, BAD), + PINI(SDMMC3_DAT6, SDMMC3, SPDIF, BAD, SDMMC3, BAD), + PINI(SDMMC3_DAT7, SDMMC3, SPDIF, BAD, SDMMC3, BAD), + PINI(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3), + PINI(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3), + PINI(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3), + PINI(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3), + PINI(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3), + PINI(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3), + PINI(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3), + PINI(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3), + PINI(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3), + PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3), + PINI(HDMI_CEC, SYS, CEC, RSVD1, RSVD2, RSVD3), +}; + +void pinmux_set_tristate(enum pmux_pingrp pin, int enable) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *tri = &pmt->pmt_ctl[pin]; + u32 reg; + + /* Error check on pin */ + assert(pmux_pingrp_isvalid(pin)); + + reg = readl(tri); + if (enable) + reg |= PMUX_TRISTATE_MASK; + else + reg &= ~PMUX_TRISTATE_MASK; + writel(reg, tri); +} + +void pinmux_tristate_enable(enum pmux_pingrp pin) +{ + pinmux_set_tristate(pin, 1); +} + +void pinmux_tristate_disable(enum pmux_pingrp pin) +{ + pinmux_set_tristate(pin, 0); +} + +void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pull = &pmt->pmt_ctl[pin]; + u32 reg; + + /* Error check on pin and pupd */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_pupd_isvalid(pupd)); + + reg = readl(pull); + reg &= ~(0x3 << PMUX_PULL_SHIFT); + reg |= (pupd << PMUX_PULL_SHIFT); + writel(reg, pull); +} + +void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *muxctl = &pmt->pmt_ctl[pin]; + int i, mux = -1; + u32 reg; + + /* Error check on pin and func */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_func_isvalid(func)); + + /* Handle special values */ + if (func == PMUX_FUNC_SAFE) + func = tegra_soc_pingroups[pin].func_safe; + + if (func & PMUX_FUNC_RSVD) { + mux = func & 0x3; + } else { + /* Search for the appropriate function */ + for (i = 0; i < 4; i++) { + if (tegra_soc_pingroups[pin].funcs[i] == func) { + mux = i; + break; + } + } + } + assert(mux != -1); + + reg = readl(muxctl); + reg &= ~(0x3 << PMUX_MUXCTL_SHIFT); + reg |= (mux << PMUX_MUXCTL_SHIFT); + writel(reg, muxctl); + +} + +void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pin_io = &pmt->pmt_ctl[pin]; + u32 reg; + + /* Error check on pin and io */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_io_isvalid(io)); + + reg = readl(pin_io); + reg &= ~(0x1 << PMUX_IO_SHIFT); + reg |= (io & 0x1) << PMUX_IO_SHIFT; + writel(reg, pin_io); +} + +static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pin_lock = &pmt->pmt_ctl[pin]; + u32 reg; + + /* Error check on pin and lock */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_lock_isvalid(lock)); + + if (lock == PMUX_PIN_LOCK_DEFAULT) + return 0; + + reg = readl(pin_lock); + reg &= ~(0x1 << PMUX_LOCK_SHIFT); + if (lock == PMUX_PIN_LOCK_ENABLE) + reg |= (0x1 << PMUX_LOCK_SHIFT); + writel(reg, pin_lock); + + return 0; +} + +static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pin_od = &pmt->pmt_ctl[pin]; + u32 reg; + + /* Error check on pin and od */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_od_isvalid(od)); + + if (od == PMUX_PIN_OD_DEFAULT) + return 0; + + reg = readl(pin_od); + reg &= ~(0x1 << PMUX_OD_SHIFT); + if (od == PMUX_PIN_OD_ENABLE) + reg |= (0x1 << PMUX_OD_SHIFT); + writel(reg, pin_od); + + return 0; +} + +static int pinmux_set_ioreset(enum pmux_pingrp pin, + enum pmux_pin_ioreset ioreset) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pin_ioreset = &pmt->pmt_ctl[pin]; + u32 reg; + + /* Error check on pin and ioreset */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_pin_ioreset_isvalid(ioreset)); + + if (ioreset == PMUX_PIN_IO_RESET_DEFAULT) + return 0; + + reg = readl(pin_ioreset); + reg &= ~(0x1 << PMUX_IO_RESET_SHIFT); + if (ioreset == PMUX_PIN_IO_RESET_ENABLE) + reg |= (0x1 << PMUX_IO_RESET_SHIFT); + writel(reg, pin_ioreset); + + return 0; +} + +void pinmux_config_pingroup(struct pingroup_config *config) +{ + enum pmux_pingrp pin = config->pingroup; + + pinmux_set_func(pin, config->func); + pinmux_set_pullupdown(pin, config->pull); + pinmux_set_tristate(pin, config->tristate); + pinmux_set_io(pin, config->io); + pinmux_set_lock(pin, config->lock); + pinmux_set_od(pin, config->od); + pinmux_set_ioreset(pin, config->ioreset); +} + +void pinmux_config_table(struct pingroup_config *config, int len) +{ + int i; + + for (i = 0; i < len; i++) + pinmux_config_pingroup(&config[i]); +} diff --git a/arch/arm/include/asm/arch-tegra3/pinmux.h b/arch/arm/include/asm/arch-tegra3/pinmux.h new file mode 100644 index 00000000000..5f6e387669a --- /dev/null +++ b/arch/arm/include/asm/arch-tegra3/pinmux.h @@ -0,0 +1,610 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PINMUX_H_ +#define _PINMUX_H_ + +/* + * Pin groups which we adjust. There are three basic attributes of each pin + * group which use this enum: + * + * - function + * - pullup / pulldown + * - tristate or normal + */ +enum pmux_pingrp { + PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */ + PINGRP_ULPI_DATA1, + PINGRP_ULPI_DATA2, + PINGRP_ULPI_DATA3, + PINGRP_ULPI_DATA4, + PINGRP_ULPI_DATA5, + PINGRP_ULPI_DATA6, + PINGRP_ULPI_DATA7, + PINGRP_ULPI_CLK, + PINGRP_ULPI_DIR, + PINGRP_ULPI_NXT, + PINGRP_ULPI_STP, + PINGRP_DAP3_FS, + PINGRP_DAP3_DIN, + PINGRP_DAP3_DOUT, + PINGRP_DAP3_SCLK, + PINGRP_GPIO_PV0, + PINGRP_GPIO_PV1, + PINGRP_SDMMC1_CLK, + PINGRP_SDMMC1_CMD, + PINGRP_SDMMC1_DAT3, + PINGRP_SDMMC1_DAT2, + PINGRP_SDMMC1_DAT1, + PINGRP_SDMMC1_DAT0, + PINGRP_GPIO_PV2, + PINGRP_GPIO_PV3, + PINGRP_CLK2_OUT, + PINGRP_CLK2_REQ, + PINGRP_LCD_PWR1, + PINGRP_LCD_PWR2, + PINGRP_LCD_SDIN, + PINGRP_LCD_SDOUT, + PINGRP_LCD_WR_N, + PINGRP_LCD_CS0_N, + PINGRP_LCD_DC0, + PINGRP_LCD_SCK, + PINGRP_LCD_PWR0, + PINGRP_LCD_PCLK, + PINGRP_LCD_DE, + PINGRP_LCD_HSYNC, + PINGRP_LCD_VSYNC, + PINGRP_LCD_D0, + PINGRP_LCD_D1, + PINGRP_LCD_D2, + PINGRP_LCD_D3, + PINGRP_LCD_D4, + PINGRP_LCD_D5, + PINGRP_LCD_D6, + PINGRP_LCD_D7, + PINGRP_LCD_D8, + PINGRP_LCD_D9, + PINGRP_LCD_D10, + PINGRP_LCD_D11, + PINGRP_LCD_D12, + PINGRP_LCD_D13, + PINGRP_LCD_D14, + PINGRP_LCD_D15, + PINGRP_LCD_D16, + PINGRP_LCD_D17, + PINGRP_LCD_D18, + PINGRP_LCD_D19, + PINGRP_LCD_D20, + PINGRP_LCD_D21, + PINGRP_LCD_D22, + PINGRP_LCD_D23, + PINGRP_LCD_CS1_N, + PINGRP_LCD_M1, + PINGRP_LCD_DC1, + PINGRP_HDMI_INT, + PINGRP_DDC_SCL, + PINGRP_DDC_SDA, + PINGRP_CRT_HSYNC, + PINGRP_CRT_VSYNC, + PINGRP_VI_D0, + PINGRP_VI_D1, + PINGRP_VI_D2, + PINGRP_VI_D3, + PINGRP_VI_D4, + PINGRP_VI_D5, + PINGRP_VI_D6, + PINGRP_VI_D7, + PINGRP_VI_D8, + PINGRP_VI_D9, + PINGRP_VI_D10, + PINGRP_VI_D11, + PINGRP_VI_PCLK, + PINGRP_VI_MCLK, + PINGRP_VI_VSYNC, + PINGRP_VI_HSYNC, + PINGRP_UART2_RXD, + PINGRP_UART2_TXD, + PINGRP_UART2_RTS_N, + PINGRP_UART2_CTS_N, + PINGRP_UART3_TXD, + PINGRP_UART3_RXD, + PINGRP_UART3_CTS_N, + PINGRP_UART3_RTS_N, + PINGRP_GPIO_PU0, + PINGRP_GPIO_PU1, + PINGRP_GPIO_PU2, + PINGRP_GPIO_PU3, + PINGRP_GPIO_PU4, + PINGRP_GPIO_PU5, + PINGRP_GPIO_PU6, + PINGRP_GEN1_I2C_SDA, + PINGRP_GEN1_I2C_SCL, + PINGRP_DAP4_FS, + PINGRP_DAP4_DIN, + PINGRP_DAP4_DOUT, + PINGRP_DAP4_SCLK, + PINGRP_CLK3_OUT, + PINGRP_CLK3_REQ, + PINGRP_GMI_WP_N, + PINGRP_GMI_IORDY, + PINGRP_GMI_WAIT, + PINGRP_GMI_ADV_N, + PINGRP_GMI_CLK, + PINGRP_GMI_CS0_N, + PINGRP_GMI_CS1_N, + PINGRP_GMI_CS2_N, + PINGRP_GMI_CS3_N, + PINGRP_GMI_CS4_N, + PINGRP_GMI_CS6_N, + PINGRP_GMI_CS7_N, + PINGRP_GMI_AD0, + PINGRP_GMI_AD1, + PINGRP_GMI_AD2, + PINGRP_GMI_AD3, + PINGRP_GMI_AD4, + PINGRP_GMI_AD5, + PINGRP_GMI_AD6, + PINGRP_GMI_AD7, + PINGRP_GMI_AD8, + PINGRP_GMI_AD9, + PINGRP_GMI_AD10, + PINGRP_GMI_AD11, + PINGRP_GMI_AD12, + PINGRP_GMI_AD13, + PINGRP_GMI_AD14, + PINGRP_GMI_AD15, + PINGRP_GMI_A16, + PINGRP_GMI_A17, + PINGRP_GMI_A18, + PINGRP_GMI_A19, + PINGRP_GMI_WR_N, + PINGRP_GMI_OE_N, + PINGRP_GMI_DQS, + PINGRP_GMI_RST_N, + PINGRP_GEN2_I2C_SCL, + PINGRP_GEN2_I2C_SDA, + PINGRP_SDMMC4_CLK, + PINGRP_SDMMC4_CMD, + PINGRP_SDMMC4_DAT0, + PINGRP_SDMMC4_DAT1, + PINGRP_SDMMC4_DAT2, + PINGRP_SDMMC4_DAT3, + PINGRP_SDMMC4_DAT4, + PINGRP_SDMMC4_DAT5, + PINGRP_SDMMC4_DAT6, + PINGRP_SDMMC4_DAT7, + PINGRP_SDMMC4_RST_N, + PINGRP_CAM_MCLK, + PINGRP_GPIO_PCC1, + PINGRP_GPIO_PBB0, + PINGRP_CAM_I2C_SCL, + PINGRP_CAM_I2C_SDA, + PINGRP_GPIO_PBB3, + PINGRP_GPIO_PBB4, + PINGRP_GPIO_PBB5, + PINGRP_GPIO_PBB6, + PINGRP_GPIO_PBB7, + PINGRP_GPIO_PCC2, + PINGRP_JTAG_RTCK, + PINGRP_PWR_I2C_SCL, + PINGRP_PWR_I2C_SDA, + PINGRP_KB_ROW0, + PINGRP_KB_ROW1, + PINGRP_KB_ROW2, + PINGRP_KB_ROW3, + PINGRP_KB_ROW4, + PINGRP_KB_ROW5, + PINGRP_KB_ROW6, + PINGRP_KB_ROW7, + PINGRP_KB_ROW8, + PINGRP_KB_ROW9, + PINGRP_KB_ROW10, + PINGRP_KB_ROW11, + PINGRP_KB_ROW12, + PINGRP_KB_ROW13, + PINGRP_KB_ROW14, + PINGRP_KB_ROW15, + PINGRP_KB_COL0, + PINGRP_KB_COL1, + PINGRP_KB_COL2, + PINGRP_KB_COL3, + PINGRP_KB_COL4, + PINGRP_KB_COL5, + PINGRP_KB_COL6, + PINGRP_KB_COL7, + PINGRP_CLK_32K_OUT, + PINGRP_SYS_CLK_REQ, + PINGRP_CORE_PWR_REQ, + PINGRP_CPU_PWR_REQ, + PINGRP_PWR_INT_N, + PINGRP_CLK_32K_IN, + PINGRP_OWR, + PINGRP_DAP1_FS, + PINGRP_DAP1_DIN, + PINGRP_DAP1_DOUT, + PINGRP_DAP1_SCLK, + PINGRP_CLK1_REQ, + PINGRP_CLK1_OUT, + PINGRP_SPDIF_IN, + PINGRP_SPDIF_OUT, + PINGRP_DAP2_FS, + PINGRP_DAP2_DIN, + PINGRP_DAP2_DOUT, + PINGRP_DAP2_SCLK, + PINGRP_SPI2_MOSI, + PINGRP_SPI2_MISO, + PINGRP_SPI2_CS0_N, + PINGRP_SPI2_SCK, + PINGRP_SPI1_MOSI, + PINGRP_SPI1_SCK, + PINGRP_SPI1_CS0_N, + PINGRP_SPI1_MISO, + PINGRP_SPI2_CS1_N, + PINGRP_SPI2_CS2_N, + PINGRP_SDMMC3_CLK, + PINGRP_SDMMC3_CMD, + PINGRP_SDMMC3_DAT0, + PINGRP_SDMMC3_DAT1, + PINGRP_SDMMC3_DAT2, + PINGRP_SDMMC3_DAT3, + PINGRP_SDMMC3_DAT4, + PINGRP_SDMMC3_DAT5, + PINGRP_SDMMC3_DAT6, + PINGRP_SDMMC3_DAT7, + PINGRP_PEX_L0_PRSNT_N, + PINGRP_PEX_L0_RST_N, + PINGRP_PEX_L0_CLKREQ_N, + PINGRP_PEX_WAKE_N, + PINGRP_PEX_L1_PRSNT_N, + PINGRP_PEX_L1_RST_N, + PINGRP_PEX_L1_CLKREQ_N, + PINGRP_PEX_L2_PRSNT_N, + PINGRP_PEX_L2_RST_N, + PINGRP_PEX_L2_CLKREQ_N, + PINGRP_HDMI_CEC, /* offset 0x33e0 */ + PINGRP_COUNT, +}; + +enum pdrive_pingrp { + PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */ + PDRIVE_PINGROUP_AO2, + PDRIVE_PINGROUP_AT1, + PDRIVE_PINGROUP_AT2, + PDRIVE_PINGROUP_AT3, + PDRIVE_PINGROUP_AT4, + PDRIVE_PINGROUP_AT5, + PDRIVE_PINGROUP_CDEV1, + PDRIVE_PINGROUP_CDEV2, + PDRIVE_PINGROUP_CSUS, + PDRIVE_PINGROUP_DAP1, + PDRIVE_PINGROUP_DAP2, + PDRIVE_PINGROUP_DAP3, + PDRIVE_PINGROUP_DAP4, + PDRIVE_PINGROUP_DBG, + PDRIVE_PINGROUP_LCD1, + PDRIVE_PINGROUP_LCD2, + PDRIVE_PINGROUP_SDIO2, + PDRIVE_PINGROUP_SDIO3, + PDRIVE_PINGROUP_SPI, + PDRIVE_PINGROUP_UAA, + PDRIVE_PINGROUP_UAB, + PDRIVE_PINGROUP_UART2, + PDRIVE_PINGROUP_UART3, + PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */ + PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */ + PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */ + PDRIVE_PINGROUP_DDC, + PDRIVE_PINGROUP_GMA, + PDRIVE_PINGROUP_GMB, + PDRIVE_PINGROUP_GMC, + PDRIVE_PINGROUP_GMD, + PDRIVE_PINGROUP_GME, + PDRIVE_PINGROUP_GMF, + PDRIVE_PINGROUP_GMG, + PDRIVE_PINGROUP_GMH, + PDRIVE_PINGROUP_OWR, + PDRIVE_PINGROUP_UAD, + PDRIVE_PINGROUP_GPV, + PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */ + PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */ + PDRIVE_PINGROUP_COUNT, +}; + +/* + * Functions which can be assigned to each of the pin groups. The values here + * bear no relation to the values programmed into pinmux registers and are + * purely a convenience. The translation is done through a table search. + */ +enum pmux_func { + PMUX_FUNC_RSVD = 0x8000, + PMUX_FUNC_RSVD0 = PMUX_FUNC_RSVD, + PMUX_FUNC_RSVD1 = 0x8000, + PMUX_FUNC_RSVD2 = 0x8001, + PMUX_FUNC_RSVD3 = 0x8002, + PMUX_FUNC_RSVD4 = 0x8003, + PMUX_FUNC_BAD = 0x4000, /* Invalid! */ + PMUX_FUNC_NONE = 0, + + PMUX_FUNC_AHB_CLK, + PMUX_FUNC_APB_CLK, + PMUX_FUNC_AUDIO_SYNC, + PMUX_FUNC_CRT, + PMUX_FUNC_DAP1, + PMUX_FUNC_DAP2, + PMUX_FUNC_DAP3, + PMUX_FUNC_DAP4, + PMUX_FUNC_DAP5, + PMUX_FUNC_DISPA, + PMUX_FUNC_DISPB, + PMUX_FUNC_EMC_TEST0_DLL, + PMUX_FUNC_EMC_TEST1_DLL, + PMUX_FUNC_GMI, + PMUX_FUNC_GMI_INT, + PMUX_FUNC_HDMI, + PMUX_FUNC_I2C, + PMUX_FUNC_I2C1 = PMUX_FUNC_I2C, + PMUX_FUNC_I2C2, + PMUX_FUNC_I2C3, + PMUX_FUNC_IDE, + PMUX_FUNC_IRDA, + PMUX_FUNC_KBC, + PMUX_FUNC_MIO, + PMUX_FUNC_MIPI_HS, + PMUX_FUNC_NAND, + PMUX_FUNC_OSC, + PMUX_FUNC_OWR, + PMUX_FUNC_PCIE, + PMUX_FUNC_PLLA_OUT, + PMUX_FUNC_PLLC_OUT1, + PMUX_FUNC_PLLM_OUT1, + PMUX_FUNC_PLLP_OUT2, + PMUX_FUNC_PLLP_OUT3, + PMUX_FUNC_PLLP_OUT4, + PMUX_FUNC_PWM, + PMUX_FUNC_PWR_INTR, + PMUX_FUNC_PWR_ON, + PMUX_FUNC_RTCK, + PMUX_FUNC_SDIO1, + PMUX_FUNC_SDMMC1 = PMUX_FUNC_SDIO1, + PMUX_FUNC_SDIO2, + PMUX_FUNC_SDMMC2 = PMUX_FUNC_SDIO2, + PMUX_FUNC_SDIO3, + PMUX_FUNC_SDMMC3 = PMUX_FUNC_SDIO3, + PMUX_FUNC_SDIO4, + PMUX_FUNC_SDMMC4 = PMUX_FUNC_SDIO4, + PMUX_FUNC_SFLASH, + PMUX_FUNC_SPDIF, + PMUX_FUNC_SPI1, + PMUX_FUNC_SPI2, + PMUX_FUNC_SPI2_ALT, + PMUX_FUNC_SPI3, + PMUX_FUNC_SPI4, + PMUX_FUNC_TRACE, + PMUX_FUNC_TWC, + PMUX_FUNC_UARTA, + PMUX_FUNC_UARTB, + PMUX_FUNC_UARTC, + PMUX_FUNC_UARTD, + PMUX_FUNC_UARTE, + PMUX_FUNC_ULPI, + PMUX_FUNC_VI, + PMUX_FUNC_VI_SENSOR_CLK, + PMUX_FUNC_XIO, + PMUX_FUNC_BLINK, + PMUX_FUNC_CEC, + PMUX_FUNC_CLK12, + PMUX_FUNC_DAP, + PMUX_FUNC_DAPSDMMC2, + PMUX_FUNC_DDR, + PMUX_FUNC_DEV3, + PMUX_FUNC_DTV, + PMUX_FUNC_VI_ALT1, + PMUX_FUNC_VI_ALT2, + PMUX_FUNC_VI_ALT3, + PMUX_FUNC_EMC_DLL, + PMUX_FUNC_EXTPERIPH1, + PMUX_FUNC_EXTPERIPH2, + PMUX_FUNC_EXTPERIPH3, + PMUX_FUNC_GMI_ALT, + PMUX_FUNC_HDA, + PMUX_FUNC_HSI, + PMUX_FUNC_I2C4, + PMUX_FUNC_I2C5, + PMUX_FUNC_I2CPWR, + PMUX_FUNC_I2S0, + PMUX_FUNC_I2S1, + PMUX_FUNC_I2S2, + PMUX_FUNC_I2S3, + PMUX_FUNC_I2S4, + PMUX_FUNC_NAND_ALT, + PMUX_FUNC_POPSDIO4, + PMUX_FUNC_POPSDMMC4, + PMUX_FUNC_PWM0, + PMUX_FUNC_PWM1, + PMUX_FUNC_PWM2, + PMUX_FUNC_PWM3, + PMUX_FUNC_SATA, + PMUX_FUNC_SPI5, + PMUX_FUNC_SPI6, + PMUX_FUNC_SYSCLK, + PMUX_FUNC_VGP1, + PMUX_FUNC_VGP2, + PMUX_FUNC_VGP3, + PMUX_FUNC_VGP4, + PMUX_FUNC_VGP5, + PMUX_FUNC_VGP6, + PMUX_FUNC_SAFE, + + PMUX_FUNC_MAX, +}; + +/* return 1 if a pmux_func is in range */ +#define pmux_func_isvalid(func) ((((func) > 0) && ((func) < PMUX_FUNC_MAX)) || \ + (((func) >= PMUX_FUNC_RSVD0) && ((func) <= PMUX_FUNC_RSVD4))) + +/* return 1 if a pingrp is in range */ +#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT)) + +/* The pullup/pulldown state of a pin group */ +enum pmux_pull { + PMUX_PULL_NORMAL = 0, + PMUX_PULL_DOWN, + PMUX_PULL_UP, +}; +/* return 1 if a pin_pupd_is in range */ +#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \ + ((pupd) <= PMUX_PULL_UP)) + +/* Defines whether a pin group is tristated or in normal operation */ +enum pmux_tristate { + PMUX_TRI_NORMAL = 0, + PMUX_TRI_TRISTATE = 1, +}; +/* return 1 if a pin_tristate_is in range */ +#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \ + && ((tristate) <= PMUX_TRI_TRISTATE)) + +enum pmux_pin_io { + PMUX_PIN_OUTPUT = 0, + PMUX_PIN_INPUT = 1, +}; +/* return 1 if a pin_io_is in range */ +#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \ + ((io) <= PMUX_PIN_INPUT)) + +enum pmux_pin_lock { + PMUX_PIN_LOCK_DEFAULT = 0, + PMUX_PIN_LOCK_DISABLE, + PMUX_PIN_LOCK_ENABLE, +}; +/* return 1 if a pin_lock is in range */ +#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \ + ((lock) <= PMUX_PIN_LOCK_ENABLE)) + +enum pmux_pin_od { + PMUX_PIN_OD_DEFAULT = 0, + PMUX_PIN_OD_DISABLE, + PMUX_PIN_OD_ENABLE, +}; +/* return 1 if a pin_od is in range */ +#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \ + ((od) <= PMUX_PIN_OD_ENABLE)) + +enum pmux_pin_ioreset { + PMUX_PIN_IO_RESET_DEFAULT = 0, + PMUX_PIN_IO_RESET_DISABLE, + PMUX_PIN_IO_RESET_ENABLE, +}; +/* return 1 if a pin_ioreset_is in range */ +#define pmux_pin_ioreset_isvalid(ioreset) \ + (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \ + ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE)) + +/* Available power domains used by pin groups */ +enum pmux_vddio { + PMUX_VDDIO_BB = 0, + PMUX_VDDIO_LCD, + PMUX_VDDIO_VI, + PMUX_VDDIO_UART, + PMUX_VDDIO_DDR, + PMUX_VDDIO_NAND, + PMUX_VDDIO_SYS, + PMUX_VDDIO_AUDIO, + PMUX_VDDIO_SD, + PMUX_VDDIO_CAM, + PMUX_VDDIO_GMI, + PMUX_VDDIO_PEXCTL, + PMUX_VDDIO_SDMMC1, + PMUX_VDDIO_SDMMC3, + PMUX_VDDIO_SDMMC4, + + PMUX_VDDIO_NONE +}; + +/* t30 pin drive group and pin mux registers */ +#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2) +#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \ + PDRIVE_PINGROUP_COUNT) +struct pmux_tri_ctlr { + uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ + uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */ + uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ + uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */ + uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */ + uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */ + uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ + + uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */ + + uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */ + uint pmt_reserved5[PMUX_OFFSET]; /* offset 0x3000 */ + uint pmt_ctl[PINGRP_COUNT]; /* pin mux/pupd/tristate regs */ +}; + +/* + * This defines the configuration for a pin, including the function assigned, + * pull up/down settings and tristate settings. Having set up one of these + * you can call pinmux_config_pingroup() to configure a pin in one step. Also + * available is pinmux_config_table() to configure a list of pins. + */ +struct pingroup_config { + enum pmux_pingrp pingroup; /* pin group PINGRP_... */ + enum pmux_func func; /* function to assign FUNC_... */ + enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ + enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ + enum pmux_pin_io io; /* input or output PMUX_PIN_... */ + enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ + enum pmux_pin_od od; /* open-drain or push-pull driver */ + enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ +}; + +/* Set a pin group to tristate */ +void pinmux_tristate_enable(enum pmux_pingrp pin); + +/* Set a pin group to normal (non tristate) */ +void pinmux_tristate_disable(enum pmux_pingrp pin); + +/* Set the pull up/down feature for a pin group */ +void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); + +/* Set the mux function for a pin group */ +void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); + +/* Set the complete configuration for a pin group */ +void pinmux_config_pingroup(struct pingroup_config *config); + +/* Set a pin group to tristate or normal */ +void pinmux_set_tristate(enum pmux_pingrp pin, int enable); + +/* Set a pin group as input or output */ +void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); + +/** + * Configuure a list of pin groups + * + * @param config List of config items + * @param len Number of config items in list + */ +void pinmux_config_table(struct pingroup_config *config, int len); + +#endif /* PINMUX_H */ |