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-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi19
-rw-r--r--arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts16
-rw-r--r--arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi77
-rw-r--r--arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi232
-rw-r--r--arch/arm/mach-imx/mx6/Kconfig11
6 files changed, 356 insertions, 0 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 457ccfe08ff..089dfb73a38 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -644,6 +644,7 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),)
dtb-y += \
imx6dl-aristainetos2c_7.dtb \
+ imx6dl-aristainetos2c_cslb_7.dtb \
imx6dl-brppt2.dtb \
imx6dl-cubox-i.dtb \
imx6dl-cubox-i-emmc-som-v15.dtb \
diff --git a/arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi
new file mode 100644
index 00000000000..b069debc1e3
--- /dev/null
+++ b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+ or X11
+/*
+ * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
+ */
+
+#include <imx6qdl-aristainetos2c_cslb-u-boot.dtsi>
+/ {
+ vdd_panel_reg: regulator-panel {
+ compatible = "regulator-fixed";
+ regulator-name = "panel_regulator";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
+
+&panel0 {
+ power-supply = <&vdd_panel_reg>;
+};
diff --git a/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts
new file mode 100644
index 00000000000..b40ddafeb97
--- /dev/null
+++ b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * support for the imx6 based aristainetos2c cslb board
+ *
+ * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
+ * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
+ *
+ */
+/dts-v1/;
+#include "imx6dl-aristainetos2_7.dtsi"
+#include "imx6qdl-aristainetos2c_cslb.dtsi"
+
+/ {
+ model = "aristainetos2c cslb i.MX6 Dual Lite Board 7";
+ compatible = "fsl,imx6dl";
+};
diff --git a/arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi
new file mode 100644
index 00000000000..8c2ed700751
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+ or X11
+/*
+ * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
+ */
+
+/ {
+ chosen {
+ u-boot,dm-pre-reloc;
+ stdout-path = &uart1;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ };
+};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_gpio {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart1 {
+ u-boot,dm-pre-reloc;
+};
+
+&iomuxc {
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-pre-reloc;
+};
+
+&backlight {
+ pwms = <&pwm1 0 300000>;
+ default-brightness-level = <2>;
+};
+
+/*
+ * allow switching write protect / reset pin by gpio,
+ * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot
+ */
+&gpio2 {
+ u-boot,dm-pre-reloc;
+
+ wp_spi_nor {
+ gpio-hog;
+ output-high;
+ gpios = <15 GPIO_ACTIVE_HIGH>;
+ };
+
+ reset_spi_nor {
+ gpio-hog;
+ output-high;
+ gpios = <28 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&gpio4 {
+ u-boot,dm-pre-reloc;
+};
+
+&ecspi1 {
+ u-boot,dm-pre-reloc;
+};
+
+&flash {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_ecspi1 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi
new file mode 100644
index 00000000000..c3724ec86fc
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * support for the imx6 based aristainetos2c-cslb board
+ *
+ * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
+ * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
+ *
+ */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/imx6qdl-clock.h>
+
+#include "imx6qdl-aristainetos2-common.dtsi"
+
+/ {
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio>;
+
+ LED_blue {
+ label = "led_blue";
+ gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
+ };
+
+ LED_green {
+ label = "led_green";
+ gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ LED_red {
+ label = "led_red";
+ gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ LED_yellow {
+ label = "led_yellow";
+ gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+ };
+
+ LED_blue_2 {
+ label = "led_blue2";
+ gpios = <&expander 15 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ LED_green_2 {
+ label = "led_green2";
+ gpios = <&expander 14 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ LED_red_2 {
+ label = "led_red2";
+ gpios = <&expander 12 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ LED_yellow_2 {
+ label = "led_yellow2";
+ gpios = <&expander 13 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ LED_ena {
+ label = "led_ena";
+ gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&ecspi1 {
+ fsl,spi-num-chipselects = <3>;
+ cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH
+ &gpio4 10 GPIO_ACTIVE_HIGH
+ &gpio4 11 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+ pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+ pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
+
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&ecspi4 {
+ fsl,spi-num-chipselects = <2>;
+ cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi4>;
+ status = "okay";
+};
+
+&i2c1 {
+ tpm@20 {
+ compatible = "infineon,slb9645tt";
+ reg = <0x20>;
+ };
+};
+
+&gpio7 {
+ eMMC_reset {
+ gpio-hog;
+ output-high;
+ gpios = <8 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ /* SS0# */
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
+ /* SS1# */
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1
+ /* SS2# */
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1
+ /* WP pin NOR Flash */
+ MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0
+ /* Flash nReset */
+ MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0
+ >;
+ };
+
+ pinctrl_ecspi4: ecspi4grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
+ MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ /* led enable */
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0
+ /* LCD power enable */
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0
+ /* led yellow */
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0
+ /* led red */
+ MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0
+ /* led green */
+ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0
+ /* led blue */
+ MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0
+ /* Profibus IRQ */
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
+ /* FPGA IRQ currently unused*/
+ MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0
+ /* Display reset because of clock failure */
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0
+ /* spi bus #2 SS driver enable */
+ MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0
+ /* RST_LOC# PHY reset input (has pull-down!)*/
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0
+ /* Touchscreen IRQ */
+ MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
+ /* PCIe reset */
+ MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0
+ /* make sure pin is GPIO and not ENET_REF_CLK */
+ MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0
+ /* TPM PP */
+ MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0
+ /* TPM Reset */
+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0
+ /* eMMC Reset# */
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+ MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+ /* SD1 card detect input */
+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
+ MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
+ MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
+ MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
+ >;
+ };
+};
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 9d6c3440642..513d007ce75 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -139,6 +139,17 @@ config TARGET_ARISTAINETOS2C
imply CMD_SATA
imply CMD_DM
+config TARGET_ARISTAINETOS2CCSLB
+ bool "Support aristainetos2-revC CSL"
+ depends on MX6DL
+ select BOARD_LATE_INIT
+ select SYS_I2C_MXC
+ select MXC_UART
+ select FEC_MXC
+ select DM
+ imply CMD_SATA
+ imply CMD_DM
+
config TARGET_CGTQMX6EVAL
bool "cgtqmx6eval"
depends on MX6QDL
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-16 07:31:01 +0000