diff options
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/dts/dragonboard820c-uboot.dtsi | 10 | ||||
-rw-r--r-- | arch/arm/dts/dragonboard820c.dts | 29 | ||||
-rw-r--r-- | arch/arm/dts/hi3798cv200-poplar.dts | 75 | ||||
-rw-r--r-- | arch/arm/dts/hi3798cv200.dtsi | 221 | ||||
-rw-r--r-- | arch/arm/dts/poplar-pinctrl.dtsi | 98 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-hi3798cv200/dwmmc.h | 12 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-omap2/Kconfig | 15 | ||||
-rw-r--r-- | arch/arm/mach-omap2/am33xx/Kconfig | 15 | ||||
-rw-r--r-- | arch/arm/mach-omap2/boot-common.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-snapdragon/Makefile | 5 | ||||
-rw-r--r-- | arch/arm/mach-snapdragon/clock-apq8096.c | 34 | ||||
-rw-r--r-- | arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h | 9 | ||||
-rw-r--r-- | arch/arm/mach-snapdragon/pinctrl-apq8096.c | 56 | ||||
-rw-r--r-- | arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 6 | ||||
-rw-r--r-- | arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-stm32mp/config.mk | 6 | ||||
-rw-r--r-- | arch/arm/mach-zynqmp/spl.c | 2 |
18 files changed, 536 insertions, 61 deletions
diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi b/arch/arm/dts/dragonboard820c-uboot.dtsi index d60aa04494d..8610d7ec37c 100644 --- a/arch/arm/dts/dragonboard820c-uboot.dtsi +++ b/arch/arm/dts/dragonboard820c-uboot.dtsi @@ -13,14 +13,22 @@ soc { u-boot,dm-pre-reloc; + qcom,tlmm@1010000 { + u-boot,dm-pre-reloc; + + uart { + u-boot,dm-pre-reloc; + }; + }; + clock-controller@300000 { u-boot,dm-pre-reloc; }; serial@75b0000 { u-boot,dm-pre-reloc; - }; }; + }; }; &pm8994_pon { diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts index ffad8e0e0ab..1114ddd7d3b 100644 --- a/arch/arm/dts/dragonboard820c.dts +++ b/arch/arm/dts/dragonboard820c.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "skeleton64.dtsi" +#include <dt-bindings/pinctrl/pinctrl-snapdragon.h> / { model = "Qualcomm Technologies, Inc. DB820c"; @@ -16,7 +17,7 @@ #size-cells = <2>; aliases { - serial0 = &blsp2_uart1; + serial0 = &blsp2_uart2; }; chosen { @@ -63,18 +64,32 @@ reg = <0x300000 0x90000>; }; - blsp2_uart1: serial@75b0000 { + pinctrl: qcom,tlmm@1010000 { + compatible = "qcom,tlmm-apq8096"; + reg = <0x1010000 0x400000>; + + blsp8_uart: uart { + function = "blsp_uart8"; + pins = "GPIO_4", "GPIO_5"; + drive-strength = <DRIVE_STRENGTH_8MA>; + bias-disable; + }; + }; + + blsp2_uart2: serial@75b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x75b0000 0x1000>; clock = <&gcc 4>; + pinctrl-names = "uart"; + pinctrl-0 = <&blsp8_uart>; }; sdhc2: sdhci@74a4900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x74a4900 0x314>, <0x74a4000 0x800>; - index = <0x0>; - bus-width = <4>; - clock = <&gcc 0>; + compatible = "qcom,sdhci-msm-v4"; + reg = <0x74a4900 0x314>, <0x74a4000 0x800>; + index = <0x0>; + bus-width = <4>; + clock = <&gcc 0>; clock-frequency = <200000000>; }; diff --git a/arch/arm/dts/hi3798cv200-poplar.dts b/arch/arm/dts/hi3798cv200-poplar.dts index 964326eae89..606ba55c7df 100644 --- a/arch/arm/dts/hi3798cv200-poplar.dts +++ b/arch/arm/dts/hi3798cv200-poplar.dts @@ -1,14 +1,17 @@ -// SPDX-License-Identifier: GPL-2.0 /* * DTS File for HiSilicon Poplar Development Board * * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * Released under the GPLv2 only. + * SPDX-License-Identifier: GPL-2.0 */ /dts-v1/; #include <dt-bindings/gpio/gpio.h> #include "hi3798cv200.dtsi" +#include "poplar-pinctrl.dtsi" / { model = "HiSilicon Poplar Development Board"; @@ -28,6 +31,13 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + leds { compatible = "gpio-leds"; @@ -59,6 +69,33 @@ default-state = "off"; }; }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "3V3_PCIE0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 7 0>; + enable-active-high; + }; +}; + +&ehci { + status = "okay"; +}; + +&emmc { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins_1 &emmc_pins_2 + &emmc_pins_3 &emmc_pins_4>; + fifo-depth = <256>; + clock-frequency = <200000000>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + bus-width = <8>; + status = "okay"; }; &gmac1 { @@ -76,17 +113,17 @@ &gpio1 { status = "okay"; - gpio-line-names = "LS-GPIO-E", "", + gpio-line-names = "GPIO-E", "", "", "", - "", "LS-GPIO-F", - "", "LS-GPIO-J"; + "", "GPIO-F", + "", "GPIO-J"; }; &gpio2 { status = "okay"; - gpio-line-names = "LS-GPIO-H", "LS-GPIO-I", - "LS-GPIO-L", "LS-GPIO-G", - "LS-GPIO-K", "", + gpio-line-names = "GPIO-H", "GPIO-I", + "GPIO-L", "GPIO-G", + "GPIO-K", "", "", ""; }; @@ -94,15 +131,15 @@ status = "okay"; gpio-line-names = "", "", "", "", - "LS-GPIO-C", "", - "", "LS-GPIO-B"; + "GPIO-C", "", + "", "GPIO-B"; }; &gpio4 { status = "okay"; gpio-line-names = "", "", "", "", - "", "LS-GPIO-D", + "", "GPIO-D", "", ""; }; @@ -110,7 +147,7 @@ status = "okay"; gpio-line-names = "", "USER-LED-1", "USER-LED-2", "", - "", "LS-GPIO-A", + "", "GPIO-A", "", ""; }; @@ -144,6 +181,22 @@ status = "okay"; }; +&ohci { + status = "okay"; +}; + +&pcie { + reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; + vpcie-supply = <®_pcie>; + status = "okay"; +}; + +&sd0 { + bus-width = <4>; + cap-sd-highspeed; + status = "okay"; +}; + &spi0 { status = "okay"; label = "LS-SPI0"; diff --git a/arch/arm/dts/hi3798cv200.dtsi b/arch/arm/dts/hi3798cv200.dtsi index 8b9c5ad05a1..7c0fddd7c8c 100644 --- a/arch/arm/dts/hi3798cv200.dtsi +++ b/arch/arm/dts/hi3798cv200.dtsi @@ -1,12 +1,16 @@ -// SPDX-License-Identifier: GPL-2.0 /* * DTS File for HiSilicon Hi3798cv200 SoC. * * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * Released under the GPLv2 only. + * SPDX-License-Identifier: GPL-2.0 */ #include <dt-bindings/clock/histb-clock.h> +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> #include <dt-bindings/reset/ti-syscon.h> / { @@ -104,6 +108,113 @@ #reset-cells = <2>; }; + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8a20000 0x1000>; + + usb2_phy1: usb2-phy@120 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + reg = <0x120 0x4>; + clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; + resets = <&crg 0xbc 4>; + #address-cells = <1>; + #size-cells = <0>; + + usb2_phy1_port0: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&crg 0xbc 8>; + }; + + usb2_phy1_port1: phy@1 { + reg = <1>; + #phy-cells = <0>; + resets = <&crg 0xbc 9>; + }; + }; + + usb2_phy2: usb2-phy@124 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + reg = <0x124 0x4>; + clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; + resets = <&crg 0xbc 6>; + #address-cells = <1>; + #size-cells = <0>; + + usb2_phy2_port0: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&crg 0xbc 10>; + }; + }; + + combphy0: phy@850 { + compatible = "hisilicon,hi3798cv200-combphy"; + reg = <0x850 0x8>; + #phy-cells = <1>; + clocks = <&crg HISTB_COMBPHY0_CLK>; + resets = <&crg 0x188 4>; + assigned-clocks = <&crg HISTB_COMBPHY0_CLK>; + assigned-clock-rates = <100000000>; + hisilicon,fixed-mode = <PHY_TYPE_USB3>; + }; + + combphy1: phy@858 { + compatible = "hisilicon,hi3798cv200-combphy"; + reg = <0x858 0x8>; + #phy-cells = <1>; + clocks = <&crg HISTB_COMBPHY1_CLK>; + resets = <&crg 0x188 12>; + assigned-clocks = <&crg HISTB_COMBPHY1_CLK>; + assigned-clock-rates = <100000000>; + hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; + }; + }; + + pmx0: pinconf@8a21000 { + compatible = "pinconf-single"; + reg = <0x8a21000 0x180>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + pinctrl-single,gpio-range = < + &range 0 8 2 /* GPIO 0 */ + &range 8 1 0 /* GPIO 1 */ + &range 9 4 2 + &range 13 1 0 + &range 14 1 1 + &range 15 1 0 + &range 16 5 0 /* GPIO 2 */ + &range 21 3 1 + &range 24 4 1 /* GPIO 3 */ + &range 28 2 2 + &range 86 1 1 + &range 87 1 0 + &range 30 4 2 /* GPIO 4 */ + &range 34 3 0 + &range 37 1 2 + &range 38 3 2 /* GPIO 6 */ + &range 41 5 0 + &range 46 8 1 /* GPIO 7 */ + &range 54 8 1 /* GPIO 8 */ + &range 64 7 1 /* GPIO 9 */ + &range 71 1 0 + &range 72 6 1 /* GPIO 10 */ + &range 78 1 0 + &range 79 1 1 + &range 80 6 1 /* GPIO 11 */ + &range 70 2 1 + &range 88 8 0 /* GPIO 12 */ + >; + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + }; + uart0: serial@8b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x8b00000 0x1000>; @@ -190,13 +301,30 @@ status = "disabled"; }; - emmc: mmc@9830000 { + sd0: mmc@9820000 { compatible = "snps,dw-mshc"; + reg = <0x9820000 0x10000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_SDIO0_CIU_CLK>, + <&crg HISTB_SDIO0_BIU_CLK>; + clock-names = "ciu", "biu"; + resets = <&crg 0x9c 4>; + reset-names = "reset"; + status = "disabled"; + }; + + emmc: mmc@9830000 { + compatible = "hisilicon,hi3798cv200-dw-mshc"; reg = <0x9830000 0x10000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg HISTB_MMC_CIU_CLK>, - <&crg HISTB_MMC_BIU_CLK>; - clock-names = "ciu", "biu"; + <&crg HISTB_MMC_BIU_CLK>, + <&crg HISTB_MMC_SAMPLE_CLK>, + <&crg HISTB_MMC_DRV_CLK>; + clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; + resets = <&crg 0xa0 4>; + reset-names = "reset"; + status = "disabled"; }; gpio0: gpio@8b20000 { @@ -207,6 +335,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 0 8>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -220,6 +349,13 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = < + &pmx0 0 8 1 + &pmx0 1 9 4 + &pmx0 5 13 1 + &pmx0 6 14 1 + &pmx0 7 15 1 + >; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -233,6 +369,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -246,6 +383,12 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = < + &pmx0 0 24 4 + &pmx0 4 28 2 + &pmx0 6 86 1 + &pmx0 7 87 1 + >; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -259,6 +402,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -285,6 +429,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -298,6 +443,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 46 8>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -311,6 +457,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 54 8>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -324,6 +471,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -337,6 +485,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -350,6 +499,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -363,6 +513,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 88 8>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -405,5 +556,67 @@ clocks = <&sysctrl HISTB_IR_CLK>; status = "disabled"; }; + + pcie: pcie@9860000 { + compatible = "hisilicon,hi3798cv200-pcie"; + reg = <0x9860000 0x1000>, + <0x0 0x2000>, + <0x2000000 0x01000000>; + reg-names = "control", "rc-dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0 15>; + num-lanes = <1>; + ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000 + 0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_PCIE_AUX_CLK>, + <&crg HISTB_PCIE_PIPE_CLK>, + <&crg HISTB_PCIE_SYS_CLK>, + <&crg HISTB_PCIE_BUS_CLK>; + clock-names = "aux", "pipe", "sys", "bus"; + resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>; + reset-names = "soft", "sys", "bus"; + phys = <&combphy1 PHY_TYPE_PCIE>; + phy-names = "phy"; + status = "disabled"; + }; + + ohci: ohci@9880000 { + compatible = "generic-ohci"; + reg = <0x9880000 0x10000>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_USB2_BUS_CLK>, + <&crg HISTB_USB2_12M_CLK>, + <&crg HISTB_USB2_48M_CLK>; + clock-names = "bus", "clk12", "clk48"; + resets = <&crg 0xb8 12>; + reset-names = "bus"; + phys = <&usb2_phy1_port0>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci: ehci@9890000 { + compatible = "generic-ehci"; + reg = <0x9890000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_USB2_BUS_CLK>, + <&crg HISTB_USB2_PHY_CLK>, + <&crg HISTB_USB2_UTMI_CLK>; + clock-names = "bus", "phy", "utmi"; + resets = <&crg 0xb8 12>, + <&crg 0xb8 16>, + <&crg 0xb8 13>; + reset-names = "bus", "phy", "utmi"; + phys = <&usb2_phy1_port0>; + phy-names = "usb"; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/poplar-pinctrl.dtsi b/arch/arm/dts/poplar-pinctrl.dtsi new file mode 100644 index 00000000000..7bb19e4b084 --- /dev/null +++ b/arch/arm/dts/poplar-pinctrl.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pinctrl dts file for HiSilicon Poplar board + * + * Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd. + */ + +#include <dt-bindings/pinctrl/hisi.h> + +/* value, enable bits, disable bits, mask */ +#define PINCTRL_PULLDOWN(value, enable, disable, mask) \ + (value << 13) (enable << 13) (disable << 13) (mask << 13) +#define PINCTRL_PULLUP(value, enable, disable, mask) \ + (value << 12) (enable << 12) (disable << 12) (mask << 12) +#define PINCTRL_SLEW_RATE(value, mask) (value << 8) (mask << 8) +#define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4) + +&pmx0 { + emmc_pins_1: emmc-pins-1 { + pinctrl-single,pins = < + 0x000 MUX_M2 + 0x004 MUX_M2 + 0x008 MUX_M2 + 0x00c MUX_M2 + 0x010 MUX_M2 + 0x014 MUX_M2 + 0x018 MUX_M2 + 0x01c MUX_M2 + 0x024 MUX_M2 + >; + pinctrl-single,bias-pulldown = < + PINCTRL_PULLDOWN(0, 1, 0, 1) + >; + pinctrl-single,bias-pullup = < + PINCTRL_PULLUP(0, 1, 0, 1) + >; + pinctrl-single,slew-rate = < + PINCTRL_SLEW_RATE(1, 1) + >; + pinctrl-single,drive-strength = < + PINCTRL_DRV_STRENGTH(0xb, 0xf) + >; + }; + + emmc_pins_2: emmc-pins-2 { + pinctrl-single,pins = < + 0x028 MUX_M2 + >; + pinctrl-single,bias-pulldown = < + PINCTRL_PULLDOWN(0, 1, 0, 1) + >; + pinctrl-single,bias-pullup = < + PINCTRL_PULLUP(0, 1, 0, 1) + >; + pinctrl-single,slew-rate = < + PINCTRL_SLEW_RATE(1, 1) + >; + pinctrl-single,drive-strength = < + PINCTRL_DRV_STRENGTH(0x9, 0xf) + >; + }; + + emmc_pins_3: emmc-pins-3 { + pinctrl-single,pins = < + 0x02c MUX_M2 + >; + pinctrl-single,bias-pulldown = < + PINCTRL_PULLDOWN(0, 1, 0, 1) + >; + pinctrl-single,bias-pullup = < + PINCTRL_PULLUP(0, 1, 0, 1) + >; + pinctrl-single,slew-rate = < + PINCTRL_SLEW_RATE(1, 1) + >; + pinctrl-single,drive-strength = < + PINCTRL_DRV_STRENGTH(3, 3) + >; + }; + + emmc_pins_4: emmc-pins-4 { + pinctrl-single,pins = < + 0x030 MUX_M2 + >; + pinctrl-single,bias-pulldown = < + PINCTRL_PULLDOWN(1, 1, 0, 1) + >; + pinctrl-single,bias-pullup = < + PINCTRL_PULLUP(0, 1, 0, 1) + >; + pinctrl-single,slew-rate = < + PINCTRL_SLEW_RATE(1, 1) + >; + pinctrl-single,drive-strength = < + PINCTRL_DRV_STRENGTH(3, 3) + >; + }; +}; diff --git a/arch/arm/include/asm/arch-hi3798cv200/dwmmc.h b/arch/arm/include/asm/arch-hi3798cv200/dwmmc.h deleted file mode 100644 index d08c20b36d3..00000000000 --- a/arch/arm/include/asm/arch-hi3798cv200/dwmmc.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2017 Linaro - * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> - */ - -#ifndef _HI3798cv200_DWMMC_H_ -#define _HI3798cv200_DWMMC_H_ - -int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width); - -#endif /* _HI3798cv200_DWMMC_H_ */ diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h index bb221e17e0e..b98b45cc817 100644 --- a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h @@ -11,7 +11,6 @@ #define REG_BASE_CRG 0xF8A22000 /* DEVICES */ -#define REG_BASE_MCI 0xF9830000 #define REG_BASE_UART0 0xF8B00000 #define HIOTG_BASE_ADDR 0xF98C0000 diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 58e545a45b4..d9bdcb355a1 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -167,6 +167,21 @@ config TI_SECURE_EMIF_PROTECTED_REGION_SIZE using hardware memory firewalls. This value must be smaller than the TI_SECURE_EMIF_TOTAL_REGION_SIZE value. +if AM43XX || AM33XX || OMAP54XX +config ISW_ENTRY_ADDR + hex "Address in memory or XIP address of bootloader entry point" + default 0x402F4000 if AM43XX + default 0x402F0400 if AM33XX + default 0x40301350 if OMAP54XX + help + After any reset, the boot ROM searches the boot media for a valid + boot image. For non-XIP devices, the ROM then copies the image into + internal memory. For all boot modes, after the ROM processes the + boot image it eventually computes the entry point address depending + on the device type (secure/non-secure), boot media (xip/non-xip) and + image headers. +endif + source "arch/arm/mach-omap2/omap3/Kconfig" source "arch/arm/mach-omap2/omap4/Kconfig" diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 57284c4ae12..4f15346c86b 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -275,21 +275,6 @@ config SPL_RTC_DDR_SUPPORT endif if AM43XX || AM33XX -config ISW_ENTRY_ADDR - hex "Address in memory or XIP flash of bootloader entry point" - default 0x402F4000 if AM43XX - default 0x402F0400 if AM33XX - help - After any reset, the boot ROM on the AM43XX SOC - searches the boot media for a valid boot image. - For non-XIP devices, the ROM then copies the - image into internal memory. - For all boot modes, after the ROM processes the - boot image it eventually computes the entry - point address depending on the device type - (secure/non-secure), boot media (xip/non-xip) and - image headers. - config PUB_ROM_DATA_SIZE hex "Size in bytes of the L3 SRAM reserved by ROM to store data" default 0x8400 diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index 176d4f67cbb..2db19227b92 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -108,7 +108,7 @@ void save_omap_boot_params(void) sys_boot_device = 1; break; #endif -#if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU_SUPPORT) +#if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU) case BOOT_DEVICE_DFU: sys_boot_device = 1; break; diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 2d940836002..709919fce4c 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -6,8 +6,9 @@ obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o -obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-apq8016.o -obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-snapdragon.o obj-y += misc.o obj-y += clock-snapdragon.o obj-y += dram.o +obj-y += pinctrl-snapdragon.o +obj-y += pinctrl-apq8016.o +obj-y += pinctrl-apq8096.o diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c index 628c38785b6..e5011be8f2e 100644 --- a/arch/arm/mach-snapdragon/clock-apq8096.c +++ b/arch/arm/mach-snapdragon/clock-apq8096.c @@ -34,6 +34,12 @@ static const struct pll_vote_clk gpll0_vote_clk = { .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0, }; +static struct vote_clk gcc_blsp2_ahb_clk = { + .cbcr_reg = BLSP2_AHB_CBCR, + .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE, + .vote_bit = BIT(15), +}; + static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) { int div = 3; @@ -47,6 +53,32 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) return rate; } +static const struct bcr_regs uart2_regs = { + .cfg_rcgr = BLSP2_UART2_APPS_CFG_RCGR, + .cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR, + .M = BLSP2_UART2_APPS_M, + .N = BLSP2_UART2_APPS_N, + .D = BLSP2_UART2_APPS_D, +}; + +static int clk_init_uart(struct msm_clk_priv *priv) +{ + /* Enable AHB clock */ + clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk); + + /* 7372800 uart block clock @ GPLL0 */ + clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625, + CFG_CLK_SRC_GPLL0); + + /* Vote for gpll0 clock */ + clk_enable_gpll0(priv->base, &gpll0_vote_clk); + + /* Enable core clk */ + clk_enable_cbc(priv->base + BLSP2_UART2_APPS_CBCR); + + return 0; +} + ulong msm_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -55,6 +87,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) case 0: /* SDC1 */ return clk_init_sdc(priv, rate); break; + case 4: /*UART2*/ + return clk_init_uart(priv); default: return 0; } diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h index 14febb6487f..36a902bd929 100644 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h @@ -15,6 +15,7 @@ /* Clocks: (from CLK_CTL_BASE) */ #define GPLL0_STATUS (0x0000) #define APCS_GPLL_ENA_VOTE (0x52000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004) #define SDCC2_BCR (0x14000) /* block reset */ #define SDCC2_APPS_CBCR (0x14004) /* branch control */ @@ -25,4 +26,12 @@ #define SDCC2_N (0x1401C) #define SDCC2_D (0x14020) +#define BLSP2_AHB_CBCR (0x25004) +#define BLSP2_UART2_APPS_CBCR (0x29004) +#define BLSP2_UART2_APPS_CMD_RCGR (0x2900C) +#define BLSP2_UART2_APPS_CFG_RCGR (0x29010) +#define BLSP2_UART2_APPS_M (0x29014) +#define BLSP2_UART2_APPS_N (0x29018) +#define BLSP2_UART2_APPS_D (0x2901C) + #endif diff --git a/arch/arm/mach-snapdragon/pinctrl-apq8096.c b/arch/arm/mach-snapdragon/pinctrl-apq8096.c new file mode 100644 index 00000000000..20a71c319b3 --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-apq8096.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm APQ8096 pinctrl + * + * (C) Copyright 2019 Ramon Fried <ramon.fried@gmail.com> + * + */ + +#include "pinctrl-snapdragon.h" +#include <common.h> + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN]; +static const char * const msm_pinctrl_pins[] = { + "SDC1_CLK", + "SDC1_CMD", + "SDC1_DATA", + "SDC2_CLK", + "SDC2_CMD", + "SDC2_DATA", + "SDC1_RCLK", +}; + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"blsp_uart8", 2}, +}; + +static const char *apq8096_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *apq8096_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + if (selector < 150) { + snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + return pin_name; + } else { + return msm_pinctrl_pins[selector - 150]; + } +} + +static unsigned int apq8096_get_function_mux(unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data apq8096_data = { + .pin_count = 157, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = apq8096_get_function_name, + .get_function_mux = apq8096_get_function_mux, + .get_pin_name = apq8096_get_pin_name, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index 5365ccdb70c..9ba8fdd7293 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -22,7 +22,7 @@ struct msm_pinctrl_priv { #define TLMM_GPIO_PULL_MASK GENMASK(1, 0) #define TLMM_FUNC_SEL_MASK GENMASK(5, 2) #define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) -#define TLMM_GPIO_ENABLE BIT(9) +#define TLMM_GPIO_DISABLE BIT(9) static const struct pinconf_param msm_conf_params[] = { { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 }, @@ -74,7 +74,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, struct msm_pinctrl_priv *priv = dev_get_priv(dev); clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), - TLMM_FUNC_SEL_MASK | TLMM_GPIO_ENABLE, + TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, priv->data->get_function_mux(func_selector) << 2); return 0; } @@ -113,8 +113,8 @@ static struct pinctrl_ops msm_pinctrl_ops = { }; static const struct udevice_id msm_pinctrl_ids[] = { - { .compatible = "qcom,tlmm-msm8916", .data = (ulong)&apq8016_data }, { .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data }, + { .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data }, { } }; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h index c47d988af4c..24f8863f59b 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h @@ -26,5 +26,6 @@ struct pinctrl_function { }; extern struct msm_pinctrl_data apq8016_data; +extern struct msm_pinctrl_data apq8096_data; #endif diff --git a/arch/arm/mach-stm32mp/config.mk b/arch/arm/mach-stm32mp/config.mk index cde5850e934..124729cd839 100644 --- a/arch/arm/mach-stm32mp/config.mk +++ b/arch/arm/mach-stm32mp/config.mk @@ -3,11 +3,11 @@ # Copyright (C) 2018, STMicroelectronics - All Rights Reserved # -ALL-$(CONFIG_SPL_BUILD) += spl/u-boot-spl.stm32 +ALL-$(CONFIG_SPL_BUILD) += u-boot-spl.stm32 MKIMAGEFLAGS_u-boot-spl.stm32 = -T stm32image -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -spl/u-boot-spl.stm32: MKIMAGEOUTPUT = spl/u-boot-spl.stm32.log +u-boot-spl.stm32: MKIMAGEOUTPUT = u-boot-spl.stm32.log -spl/u-boot-spl.stm32: spl/u-boot-spl.bin FORCE +u-boot-spl.stm32: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index 01f31d0f0ed..fb3955c93fd 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -93,7 +93,7 @@ u32 spl_boot_device(void) case EMMC_MODE: return BOOT_DEVICE_MMC1; #endif -#ifdef CONFIG_SPL_DFU_SUPPORT +#ifdef CONFIG_SPL_DFU case USB_MODE: return BOOT_DEVICE_DFU; #endif |