4 files changed, 9 insertions, 28 deletions
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index aef1a455ae0..d3bddb726af 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -17,21 +17,6 @@ config ROCKCHIP_RK3036
 	  and video codec support. Peripherals include Gigabit Ethernet,
 	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
 
-config ROCKCHIP_SPL_HDR
-	string "Header of rockchip's spl loader"
-	help
-	  Rockchip's bootrom requires the spl loader to start with a 4-bytes
-	  header. The content of this header depends on the chip type.
-
-config ROCKCHIP_MAX_SPL_SIZE
-	hex "Max size of rockchip's spl loader"
-	help
-	  Different chip may have different sram size. And if we want to jump
-	  back to the bootrom after spl, we may need to reserve some sram space
-	  for the bootrom.
-	  The max spl loader size should be sram size minus reserved
-	  size(if needed)
-
 config SYS_MALLOC_F
 	default y
 
diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig
index 95fb2b94633..cc038088472 100644
--- a/arch/arm/mach-rockchip/rk3036/Kconfig
+++ b/arch/arm/mach-rockchip/rk3036/Kconfig
@@ -3,21 +3,19 @@ if ROCKCHIP_RK3036
 config TARGET_EVB_RK3036
 	bool "EVB_RK3036"
 
+config TARGET_KYLIN_RK3036
+	bool "KYLIN_RK3036"
+
 config SYS_SOC
 	default "rockchip"
 
 config SYS_MALLOC_F_LEN
 	default 0x400
 
-config ROCKCHIP_SPL_HDR
-        default "RK30"
-
-config ROCKCHIP_MAX_SPL_SIZE
-        default 0x1000
-
 config ROCKCHIP_COMMON
 	bool "Support rk common fuction"
 
 source "board/evb_rk3036/evb_rk3036/Kconfig"
+source "board/kylin/kylin_rk3036/Kconfig"
 
 endif
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index 7a05e310d73..e3ca8700742 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -701,15 +701,19 @@ finish:
 static void sdram_all_config(struct rk3036_sdram_priv *priv)
 {
 	u32 os_reg = 0;
+	u32 cs1_row = 0;
 	struct rk3036_ddr_config config = priv->ddr_config;
 
+	if (config.rank > 1)
+		cs1_row = config.cs1_row - 13;
+
 	os_reg = config.ddr_type << DDR_TYPE_SHIFT |
 			0 << DDR_CHN_CNT_SHIFT |
 			(config.rank - 1) << DDR_RANK_CNT_SHIFT |
 			(config.col - 1) << DDR_COL_SHIFT |
 			(config.bank == 3 ? 0 : 1) << DDR_BANK_SHIFT |
 			(config.cs0_row - 13) << DDR_CS0_ROW_SHIFT |
-			(config.cs1_row - 13) << DDR_CS1_ROW_SHIFT |
+			cs1_row << DDR_CS1_ROW_SHIFT |
 			1 << DDR_BW_SHIFT | config.bw << DDR_DIE_BW_SHIFT;
 	writel(os_reg, &priv->grf->os_reg[1]);
 }
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index 3de3878cd6e..d0a72767c88 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -16,12 +16,6 @@ config TARGET_CHROMEBOOK_JERRY
 	  WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
 	  the keyboard and battery functions.
 
-config ROCKCHIP_SPL_HDR
-	default "RK32"
-
-config ROCKCHIP_MAX_SPL_SIZE
-	default 0x8000
-
 config SYS_SOC
 	default "rockchip"