diff options
Diffstat (limited to 'arch/arm')
23 files changed, 259 insertions, 20 deletions
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c index bee9318f5a..085649e712 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c @@ -46,7 +46,7 @@ void reset_cpu(ulong addr) int arch_cpu_init(void) { /* - * It might be necessary to flush data cache, if U-boot is loaded + * It might be necessary to flush data cache, if U-Boot is loaded * from kickstart bootloader, e.g. from S1L loader */ flush_dcache_all(); diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S index 4b8053e3f9..b21abc3752 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S @@ -41,5 +41,5 @@ lowlevel_init: orr r0, #0x00000004 str r0, [r1] - /* Return to U-boot via saved link register */ + /* Return to U-Boot via saved link register */ mov pc, lr diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 31d1c9e348..b7563edbe6 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -37,7 +37,7 @@ _monitor_vectors: /* * secure monitor handler - * U-boot calls this "software interrupt" in start.S + * U-Boot calls this "software interrupt" in start.S * This is executed on a "smc" instruction, we use a "smc #0" to switch * to non-secure state. * r0, r1, r2: passed to the callee diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 4fa72f7835..652d319a08 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -89,6 +89,7 @@ config TARGET_OMAP3_LOGIC select DM select DM_SERIAL select DM_GPIO + select SUPPORT_SPL config TARGET_NOKIA_RX51 bool "Nokia RX51" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 4cd84b0311..3d19bbfbe2 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -1,6 +1,6 @@ if ARM64 config ARMV8_MULTIENTRY - boolean "Enable multiple CPUs to enter into U-boot" + boolean "Enable multiple CPUs to enter into U-Boot" endif diff --git a/arch/arm/dts/k2g-evm.dts b/arch/arm/dts/k2g-evm.dts index de50e8f862..0ca36ef39a 100644 --- a/arch/arm/dts/k2g-evm.dts +++ b/arch/arm/dts/k2g-evm.dts @@ -19,3 +19,15 @@ stdout-path = &uart0; }; }; + +&mdio { + status = "okay"; + ethphy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "rgmii-id"; + }; +}; + +&gbe0 { + phy-handle = <ðphy0>; +}; diff --git a/arch/arm/dts/k2g-netcp.dtsi b/arch/arm/dts/k2g-netcp.dtsi new file mode 100644 index 0000000000..6f0ff863af --- /dev/null +++ b/arch/arm/dts/k2g-netcp.dtsi @@ -0,0 +1,151 @@ +/* + * Device Tree Source for Keystone 2 Galileo Netcp driver + * + * Copyright 2015 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +qmss: qmss@4020000 { + compatible = "ti,keystone-navigator-qmss-l"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */ + /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */ + clock-names = "nss_vclk"; + ranges; + queue-range = <0 0x80>; + linkram0 = <0x4020000 0x7ff>; + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x80>; + reg = <0x4100000 0x800>, + <0x4040000 0x100>, + <0x4080000 0x800>, + <0x40c0000 0x800>; + reg-names = "peek", "config", + "region", "push"; + }; + + }; + queue-pools { + qpend { + qpend-0 { + qrange = <77 8>; + interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04 + 0 311 0xf04 0 312 0xf04 0 313 0xf04 + 0 314 0xf04 0 315 0xf04>; + qalloc-by-id; + }; + }; + general-purpose { + gp-0 { + qrange = <112 8>; + }; + netcp-tx { + qrange = <5 8>; + qalloc-by-id; + }; + }; + }; + + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <1023 128>; /* num_desc desc_size */ + link-index = <0x400>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + #address-cells = <1>; + #size-cells = <1>; + /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */ + /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */ + clock-names = "nss_vclk"; + ranges; + ti,navigator-cloud-address = <0x40c0000 0x40c0000 0x40c0000 0x40c0000>; + + dma_gbe: dma_gbe@0 { + reg = <0x4010000 0x100>, + <0x4011000 0x2a0>, /* 21 Tx channels */ + <0x4012000 0x400>, /* 32 Rx channels */ + <0x4010100 0x80>, + <0x4013000 0x400>; /* 32 Rx flows */ + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; + +}; + +gbe_subsys: subsys@4200000 { + compatible = "syscon"; + reg = <0x4200000 0x100>; +}; + +netcp: netcp@4000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */ + /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */ + clock-names = "ethss_clk"; + + /* NetCP address range */ + ranges = <0 0x4000000 0x1000000>; + + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 0>, <&dma_gbe 5>; + ti,navigator-dma-names = "netrx0", "nettx"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + gbe@200000 { + label = "netcp-gbe"; + compatible = "ti,netcp-gbe-2"; + syscon-subsys = <&gbe_subsys>; + reg = <0x200100 0xe00>, <0x220000 0x20000>; + /* enable-ale; */ + tx-queue = <5>; + tx-channel = "nettx"; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <5>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <512 12>; + tx-pool = <511 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <77>; + tx-completion-queue = <78>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + }; + }; +}; diff --git a/arch/arm/dts/k2g.dtsi b/arch/arm/dts/k2g.dtsi index 6b79b163ff..bbc2cf91b9 100644 --- a/arch/arm/dts/k2g.dtsi +++ b/arch/arm/dts/k2g.dtsi @@ -68,5 +68,18 @@ interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>; }; + mdio: mdio@4200f00 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */ + /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */ + clock-names = "fck"; + reg = <0x04200f00 0x100>; + status = "disabled"; + bus_freq = <2500000>; + }; + + #include "k2g-netcp.dtsi" }; }; diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts index 469bd05e16..f62916da39 100644 --- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts @@ -59,7 +59,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ / { soc { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts index e0a972f4d2..dca408bb70 100644 --- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts @@ -61,7 +61,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ / { soc { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts index 02e74a7c3b..202a642a4d 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts @@ -66,7 +66,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ / { soc { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts index d46e827280..02a3362e74 100644 --- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts +++ b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts @@ -47,7 +47,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ / { soc { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts index 1f3aee928a..ff17945e90 100644 --- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts @@ -68,7 +68,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ &serial0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts index b58bf075ac..b5b6f65d36 100644 --- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts @@ -63,7 +63,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ / { soc { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts index a49215edae..c6c133aa19 100644 --- a/arch/arm/dts/uniphier-proxstream2-gentil.dts +++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts @@ -49,7 +49,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ / { soc { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts index 63bd3633bd..3703ad36a5 100644 --- a/arch/arm/dts/uniphier-proxstream2-vodka.dts +++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts @@ -45,7 +45,7 @@ status = "okay"; }; -/* for U-boot only */ +/* for U-Boot only */ / { soc { u-boot,dm-pre-reloc; diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_defs.h b/arch/arm/include/asm/arch-stm32f4/stm32_defs.h new file mode 100644 index 0000000000..29b98aecf4 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f4/stm32_defs.h @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STM32_DEFS_H__ +#define __STM32_DEFS_H__ +#include <asm/arch/stm32_periph.h> + +int clock_setup(enum periph_clock); + +#endif + diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_periph.h b/arch/arm/include/asm/arch-stm32f4/stm32_periph.h new file mode 100644 index 0000000000..a1af25cb58 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f4/stm32_periph.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals required for pinmux configuration. List will + * grow with support for more devices getting added. + * Numbering based on interrupt table. + * + */ +enum periph_id { + UART1_GPIOA_9_10 = 0, + UART2_GPIOD_5_6, +}; + +enum periph_clock { + USART1_CLOCK_CFG = 0, + USART2_CLOCK_CFG, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/mach-exynos/include/mach/spl.h b/arch/arm/mach-exynos/include/mach/spl.h index 0c480acb1a..a5d13fa7cb 100644 --- a/arch/arm/mach-exynos/include/mach/spl.h +++ b/arch/arm/mach-exynos/include/mach/spl.h @@ -42,10 +42,10 @@ struct spl_machine_param { u32 mem_iv_size; /* Memory channel interleaving size */ enum ddr_mode mem_type; /* Type of on-board memory */ /* - * U-boot size - The iROM mmc copy function used by the SPL takes a - * block count paramter to describe the u-boot size unlike the spi - * boot copy function which just uses the u-boot size directly. Align - * the u-boot size to block size (512 bytes) when populating the SPL + * U-Boot size - The iROM mmc copy function used by the SPL takes a + * block count paramter to describe the U-Boot size unlike the spi + * boot copy function which just uses the U-Boot size directly. Align + * the U-Boot size to block size (512 bytes) when populating the SPL * table only for mmc boot. */ u32 uboot_size; diff --git a/arch/arm/mach-exynos/sec_boot.S b/arch/arm/mach-exynos/sec_boot.S index dfc3455929..5dc216dce1 100644 --- a/arch/arm/mach-exynos/sec_boot.S +++ b/arch/arm/mach-exynos/sec_boot.S @@ -30,10 +30,10 @@ relocate_wait_code: * because that comes out to be the last 4KB of the iRAM * (Base Address - 0x02020000, Limit Address - 0x020740000). * - * U-boot and kernel are aware of this code and flags by the simple + * U-Boot and kernel are aware of this code and flags by the simple * fact that we are implementing a workaround in the last 4KB * of the iRAM and we have already defined these flag and address - * values in both kernel and U-boot for our use. + * values in both kernel and U-Boot for our use. */ code_base: b 1f diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c index c7f943eb6a..7df01021cd 100644 --- a/arch/arm/mach-exynos/spl_boot.c +++ b/arch/arm/mach-exynos/spl_boot.c @@ -177,7 +177,7 @@ static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr) #endif /* -* Copy U-boot from mmc to RAM: +* Copy U-Boot from mmc to RAM: * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains * Pointer to API (Data transfer from mmc to ram) */ diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S index 51a8b3c51b..3f38f36ff2 100644 --- a/arch/arm/mach-orion5x/lowlevel_init.S +++ b/arch/arm/mach-orion5x/lowlevel_init.S @@ -283,5 +283,5 @@ lowlevel_init: #endif /* CONFIG_SPL_BUILD */ - /* Return to U-boot via saved link register */ + /* Return to U-Boot via saved link register */ mov pc, lr diff --git a/arch/arm/mach-stm32/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c index 3deb17aa83..576d3e68ae 100644 --- a/arch/arm/mach-stm32/stm32f4/clock.c +++ b/arch/arm/mach-stm32/stm32f4/clock.c @@ -11,6 +11,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/stm32.h> +#include <asm/arch/stm32_periph.h> #define RCC_CR_HSION (1 << 0) #define RCC_CR_HSEON (1 << 16) @@ -50,6 +51,14 @@ #define RCC_APB1ENR_PWREN (1 << 28) +/* + * RCC USART specific definitions + */ +#define RCC_ENR_USART1EN (1 << 4) +#define RCC_ENR_USART2EN (1 << 17) +#define RCC_ENR_USART3EN (1 << 18) +#define RCC_ENR_USART6EN (1 << 5) + #define PWR_CR_VOS0 (1 << 14) #define PWR_CR_VOS1 (1 << 15) #define PWR_CR_VOS_MASK 0xC000 @@ -221,3 +230,14 @@ unsigned long clock_get(enum clock clck) break; } } + +void clock_setup(int peripheral) +{ + switch (peripheral) { + case USART1_CLOCK_CFG: + setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN); + break; + default: + break; + } +} |