5 files changed, 0 insertions, 199 deletions
diff --git a/arch/arm/mach-uniphier/pll/Makefile b/arch/arm/mach-uniphier/pll/Makefile
deleted file mode 100644
index db22ba4ae1..0000000000
--- a/arch/arm/mach-uniphier/pll/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= pll-init-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= pll-init-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= pll-init-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= pll-init-sld8.o
diff --git a/arch/arm/mach-uniphier/pll/pll-init-ld4.c b/arch/arm/mach-uniphier/pll/pll-init-ld4.c
deleted file mode 100644
index a40b30d0e0..0000000000
--- a/arch/arm/mach-uniphier/pll/pll-init-ld4.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Panasonic Corporation
- * Copyright (C) 2015-2016 Socionext Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-
-#undef DPLL_SSC_RATE_1PER
-
-int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd)
-{
-	unsigned int dram_freq = bd->dram_freq;
-	u32 tmp;
-
-	/*
-	 * Set Frequency
-	 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
-	 * to FOUT (DPLLCTRL.bit[29:20])
-	 */
-	tmp = readl(SC_DPLLCTRL);
-	tmp &= ~0x000f0000;
-	switch (dram_freq) {
-	case 1333:
-		tmp |= 0x000d0000;
-		break;
-	case 1600:
-		tmp |= 0x000c0000;
-		break;
-	default:
-		pr_err("Unsupported frequency");
-		return -EINVAL;
-	}
-
-#if defined(DPLL_SSC_RATE_1PER)
-	tmp &= ~SC_DPLLCTRL_SSC_RATE;
-#else
-	tmp |= SC_DPLLCTRL_SSC_RATE;
-#endif
-	writel(tmp, SC_DPLLCTRL);
-
-	tmp = readl(SC_DPLLCTRL2);
-	tmp |= SC_DPLLCTRL2_NRSTDS;
-	writel(tmp, SC_DPLLCTRL2);
-
-	/* Wait 500 usec until dpll gets stable */
-	udelay(500);
-
-	return 0;
-}
diff --git a/arch/arm/mach-uniphier/pll/pll-init-pro4.c b/arch/arm/mach-uniphier/pll/pll-init-pro4.c
deleted file mode 100644
index 3ac48d6365..0000000000
--- a/arch/arm/mach-uniphier/pll/pll-init-pro4.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Panasonic Corporation
- * Copyright (C) 2015-2016 Socionext Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-
-#undef DPLL_SSC_RATE_1PER
-
-int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd)
-{
-	unsigned int dram_freq = bd->dram_freq;
-	u32 tmp;
-
-	/*
-	 * Set Frequency
-	 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
-	 * to FOUT ( DPLLCTRL.bit[29:20] )
-	 */
-	tmp = readl(SC_DPLLCTRL);
-	tmp &= ~(0x000f0000);
-	switch (dram_freq) {
-	case 1333:
-		tmp |= 0x000d0000;
-		break;
-	case 1600:
-		tmp |= 0x000c0000;
-		break;
-	default:
-		pr_err("Unsupported frequency");
-		return -EINVAL;
-	}
-
-	/*
-	 * Set Moduration rate
-	 * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
-	 */
-#if defined(DPLL_SSC_RATE_1PER)
-	tmp &= ~0x00008000;
-#else
-	tmp |= 0x00008000;
-#endif
-	writel(tmp, SC_DPLLCTRL);
-
-	tmp = readl(SC_DPLLCTRL2);
-	tmp |= SC_DPLLCTRL2_NRSTDS;
-	writel(tmp, SC_DPLLCTRL2);
-
-	/* Wait until dpll gets stable */
-	udelay(500);
-
-	return 0;
-}
diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld3.c b/arch/arm/mach-uniphier/pll/pll-init-sld3.c
deleted file mode 100644
index 0eb310ceb8..0000000000
--- a/arch/arm/mach-uniphier/pll/pll-init-sld3.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include "../init.h"
-
-int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd)
-{
-	/* add pll init code here */
-	return 0;
-}
diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld8.c b/arch/arm/mach-uniphier/pll/pll-init-sld8.c
deleted file mode 100644
index 7faa5e85b6..0000000000
--- a/arch/arm/mach-uniphier/pll/pll-init-sld8.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Panasonic Corporation
- * Copyright (C) 2015-2016 Socionext Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-
-int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd)
-{
-	u32 tmp;
-	/*
-	 * Set DPLL SSC parameters for DPLLCTRL3
-	 * [23]    DIVN_TEST    0x1
-	 * [22:16] DIVN         0x50
-	 * [10]    FREFSEL_TEST 0x1
-	 * [9:8]   FREFSEL      0x2
-	 * [4]     ICPD_TEST    0x1
-	 * [3:0]   ICPD         0xb
-	 */
-	tmp = readl(SC_DPLLCTRL3);
-	tmp &= ~0x00ff0717;
-	tmp |= 0x00d0061b;
-	writel(tmp, SC_DPLLCTRL3);
-
-	/*
-	 * Set DPLL SSC parameters for DPLLCTRL
-	 *                    <-1%>          <-2%>
-	 * [29:20] SSC_UPCNT 132 (0x084)    132  (0x084)
-	 * [14:0]  SSC_dK    6335(0x18bf)   12710(0x31a6)
-	 */
-	tmp = readl(SC_DPLLCTRL);
-	tmp &= ~0x3ff07fff;
-#ifdef DPLL_SSC_RATE_1PER
-	tmp |= 0x084018bf;
-#else
-	tmp |= 0x084031a6;
-#endif
-	writel(tmp, SC_DPLLCTRL);
-
-	/*
-	 * Set DPLL SSC parameters for DPLLCTRL2
-	 * [31:29]  SSC_STEP     0
-	 * [27]     SSC_REG_REF  1
-	 * [26:20]  SSC_M        79     (0x4f)
-	 * [19:0]   SSC_K        964689 (0xeb851)
-	 */
-	tmp = readl(SC_DPLLCTRL2);
-	tmp &= ~0xefffffff;
-	tmp |= 0x0cfeb851;
-	writel(tmp, SC_DPLLCTRL2);
-
-	/* Wait 500 usec until dpll gets stable */
-	udelay(500);
-
-	return 0;
-}