diff options
Diffstat (limited to 'arch/arm/mach-socfpga/clock_manager_gen5.c')
| -rw-r--r-- | arch/arm/mach-socfpga/clock_manager_gen5.c | 211 |
1 files changed, 122 insertions, 89 deletions
diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c index 54a821a27f..8fa2760798 100644 --- a/arch/arm/mach-socfpga/clock_manager_gen5.c +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c @@ -10,23 +10,20 @@ #include <asm/arch/clock_manager.h> #include <wait_bit.h> -static const struct socfpga_clock_manager *clock_manager_base = - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; - /* * function to write the bypass register which requires a poll of the * busy bit */ static void cm_write_bypass(u32 val) { - writel(val, &clock_manager_base->bypass); + writel(val, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_BYPASS); cm_wait_for_fsm(); } /* function to write the ctrl register which requires a poll of the busy bit */ static void cm_write_ctrl(u32 val) { - writel(val, &clock_manager_base->ctrl); + writel(val, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_CTRL); cm_wait_for_fsm(); } @@ -80,8 +77,8 @@ int cm_basic_init(const struct cm_config * const cfg) * gatting off the rest of the periperal clocks. */ writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK & - readl(&clock_manager_base->per_pll.en), - &clock_manager_base->per_pll.en); + readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN), + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN); /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */ writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK | @@ -90,12 +87,12 @@ int cm_basic_init(const struct cm_config * const cfg) CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK | CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK | CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK, - &clock_manager_base->main_pll.en); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_EN); - writel(0, &clock_manager_base->sdr_pll.en); + writel(0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_EN); /* now we can gate off the rest of the peripheral clocks */ - writel(0, &clock_manager_base->per_pll.en); + writel(0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN); /* Put all plls in bypass */ cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL | @@ -104,13 +101,13 @@ int cm_basic_init(const struct cm_config * const cfg) /* Put all plls VCO registers back to reset value. */ writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE & ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->main_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO); writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE & ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->per_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE & ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->sdr_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); /* * The clocks to the flash devices and the L4_MAIN clocks can @@ -120,23 +117,26 @@ int cm_basic_init(const struct cm_config * const cfg) * after exiting safe mode but before ungating the clocks. */ writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE, - &clock_manager_base->per_pll.src); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC); writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE, - &clock_manager_base->main_pll.l4src); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC); /* read back for the required 5 us delay. */ - readl(&clock_manager_base->main_pll.vco); - readl(&clock_manager_base->per_pll.vco); - readl(&clock_manager_base->sdr_pll.vco); + readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO); + readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); + readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); /* * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN * with numerator and denominator. */ - writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); - writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); - writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); + writel(cfg->main_vco_base, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO); + writel(cfg->peri_vco_base, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); + writel(cfg->sdram_vco_base, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); /* * Time starts here. Must wait 7 us from @@ -145,44 +145,55 @@ int cm_basic_init(const struct cm_config * const cfg) end = timer_get_us() + 7; /* main mpu */ - writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); + writel(cfg->mpuclk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MPUCLK); /* altera group mpuclk */ - writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk); + writel(cfg->altera_grp_mpuclk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_ALTR_MPUCLK); /* main main clock */ - writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk); + writel(cfg->mainclk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINCLK); /* main for dbg */ - writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk); + writel(cfg->dbgatclk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_DBGATCLK); /* main for cfgs2fuser0clk */ writel(cfg->cfg2fuser0clk, - &clock_manager_base->main_pll.cfgs2fuser0clk); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK); /* Peri emac0 50 MHz default to RMII */ - writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk); + writel(cfg->emac0clk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EMAC0CLK); /* Peri emac1 50 MHz default to RMII */ - writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk); + writel(cfg->emac1clk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EMAC1CLK); /* Peri QSPI */ - writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk); + writel(cfg->mainqspiclk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINQSPICLK); - writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk); + writel(cfg->perqspiclk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERQSPICLK); /* Peri pernandsdmmcclk */ writel(cfg->mainnandsdmmcclk, - &clock_manager_base->main_pll.mainnandsdmmcclk); + socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK); writel(cfg->pernandsdmmcclk, - &clock_manager_base->per_pll.pernandsdmmcclk); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK); /* Peri perbaseclk */ - writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk); + writel(cfg->perbaseclk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERBASECLK); /* Peri s2fuser1clk */ - writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk); + writel(cfg->s2fuser1clk, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_S2FUSER1CLK); /* 7 us must have elapsed before we can enable the VCO */ while (timer_get_us() < end) @@ -191,101 +202,112 @@ int cm_basic_init(const struct cm_config * const cfg) /* Enable vco */ /* main pll vco */ writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, - &clock_manager_base->main_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO); /* periferal pll */ writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, - &clock_manager_base->per_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); /* sdram pll vco */ writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, - &clock_manager_base->sdr_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); /* L3 MP and L3 SP */ - writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv); + writel(cfg->maindiv, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINDIV); - writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv); + writel(cfg->dbgdiv, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_DBGDIV); - writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv); + writel(cfg->tracediv, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_TRACEDIV); /* L4 MP, L4 SP, can0, and can1 */ - writel(cfg->perdiv, &clock_manager_base->per_pll.div); + writel(cfg->perdiv, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_DIV); - writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv); + writel(cfg->gpiodiv, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_GPIODIV); cm_wait_for_lock(LOCKED_MASK); /* write the sdram clock counters before toggling outreset all */ writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK, - &clock_manager_base->sdr_pll.ddrdqsclk); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQSCLK); writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK, - &clock_manager_base->sdr_pll.ddr2xdqsclk); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK); writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK, - &clock_manager_base->sdr_pll.ddrdqclk); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQCLK); writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK, - &clock_manager_base->sdr_pll.s2fuser2clk); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_S2FUSER2CLK); /* * after locking, but before taking out of bypass * assert/deassert outresetall */ - u32 mainvco = readl(&clock_manager_base->main_pll.vco); + u32 mainvco = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_MAINPLL_VCO); /* assert main outresetall */ writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->main_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO); - u32 periphvco = readl(&clock_manager_base->per_pll.vco); + u32 periphvco = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_PERPLL_VCO); /* assert pheriph outresetall */ writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->per_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); /* assert sdram outresetall */ - writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN| - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL, - &clock_manager_base->sdr_pll.vco); + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN | + CLKMGR_SDRPLLGRP_VCO_OUTRESETALL, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); /* deassert main outresetall */ writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->main_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO); /* deassert pheriph outresetall */ writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->per_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); /* deassert sdram outresetall */ writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, - &clock_manager_base->sdr_pll.vco); + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); /* * now that we've toggled outreset all, all the clocks * are aligned nicely; so we can change any phase. */ ret = cm_write_with_phase(cfg->ddrdqsclk, - &clock_manager_base->sdr_pll.ddrdqsclk, + (const void *)(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_SDRPLL_DDRDQSCLK), CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK); if (ret) return ret; /* SDRAM DDR2XDQSCLK */ ret = cm_write_with_phase(cfg->ddr2xdqsclk, - &clock_manager_base->sdr_pll.ddr2xdqsclk, + (const void *)(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK), CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK); if (ret) return ret; ret = cm_write_with_phase(cfg->ddrdqclk, - &clock_manager_base->sdr_pll.ddrdqclk, + (const void *)(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_SDRPLL_DDRDQCLK), CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK); if (ret) return ret; ret = cm_write_with_phase(cfg->s2fuser2clk, - &clock_manager_base->sdr_pll.s2fuser2clk, + (const void *)(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_SDRPLL_S2FUSER2CLK), CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); if (ret) return ret; @@ -294,24 +316,28 @@ int cm_basic_init(const struct cm_config * const cfg) cm_write_bypass(0); /* clear safe mode */ - cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE); + cm_write_ctrl(readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_CTRL) | + CLKMGR_CTRL_SAFEMODE); /* * now that safe mode is clear with clocks gated * it safe to change the source mux for the flashes the the L4_MAIN */ - writel(cfg->persrc, &clock_manager_base->per_pll.src); - writel(cfg->l4src, &clock_manager_base->main_pll.l4src); + writel(cfg->persrc, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC); + writel(cfg->l4src, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC); /* Now ungate non-hw-managed clocks */ - writel(~0, &clock_manager_base->main_pll.en); - writel(~0, &clock_manager_base->per_pll.en); - writel(~0, &clock_manager_base->sdr_pll.en); + writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_EN); + writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN); + writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_EN); /* Clear the loss of lock bits (write 1 to clear) */ - writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK | - CLKMGR_INTER_MAINPLLLOST_MASK, - &clock_manager_base->inter); + writel(CLKMGR_INTER_SDRPLLLOST_MASK | + CLKMGR_INTER_PERPLLLOST_MASK | + CLKMGR_INTER_MAINPLLLOST_MASK, + socfpga_get_clkmgr_addr() + CLKMGR_GEN5_INTER); return 0; } @@ -321,7 +347,7 @@ static unsigned int cm_get_main_vco_clk_hz(void) u32 reg, clock; /* get the main VCO clock */ - reg = readl(&clock_manager_base->main_pll.vco); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO); clock = cm_get_osc_clk_hz(1); clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1; @@ -336,7 +362,7 @@ static unsigned int cm_get_per_vco_clk_hz(void) u32 reg, clock = 0; /* identify PER PLL clock source */ - reg = readl(&clock_manager_base->per_pll.vco); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >> CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET; if (reg == CLKMGR_VCO_SSRC_EOSC1) @@ -347,7 +373,7 @@ static unsigned int cm_get_per_vco_clk_hz(void) clock = cm_get_f2s_per_ref_clk_hz(); /* get the PER VCO clock */ - reg = readl(&clock_manager_base->per_pll.vco); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >> CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1; clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >> @@ -363,9 +389,9 @@ unsigned long cm_get_mpu_clk_hz(void) clock = cm_get_main_vco_clk_hz(); /* get the MPU clock */ - reg = readl(&clock_manager_base->altera.mpuclk); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_ALTR_MPUCLK); clock /= (reg + 1); - reg = readl(&clock_manager_base->main_pll.mpuclk); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MPUCLK); clock /= (reg + 1); return clock; } @@ -375,7 +401,7 @@ unsigned long cm_get_sdram_clk_hz(void) u32 reg, clock = 0; /* identify SDRAM PLL clock source */ - reg = readl(&clock_manager_base->sdr_pll.vco); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >> CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET; if (reg == CLKMGR_VCO_SSRC_EOSC1) @@ -386,14 +412,14 @@ unsigned long cm_get_sdram_clk_hz(void) clock = cm_get_f2s_sdr_ref_clk_hz(); /* get the SDRAM VCO clock */ - reg = readl(&clock_manager_base->sdr_pll.vco); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >> CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1; clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >> CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1; /* get the SDRAM (DDR_DQS) clock */ - reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQSCLK); reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >> CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET; clock /= (reg + 1); @@ -406,7 +432,7 @@ unsigned int cm_get_l4_sp_clk_hz(void) u32 reg, clock = 0; /* identify the source of L4 SP clock */ - reg = readl(&clock_manager_base->main_pll.l4src); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC); reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >> CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET; @@ -414,20 +440,23 @@ unsigned int cm_get_l4_sp_clk_hz(void) clock = cm_get_main_vco_clk_hz(); /* get the clock prior L4 SP divider (main clk) */ - reg = readl(&clock_manager_base->altera.mainclk); + reg = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_ALTR_MAINCLK); clock /= (reg + 1); - reg = readl(&clock_manager_base->main_pll.mainclk); + reg = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_MAINPLL_MAINCLK); clock /= (reg + 1); } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) { clock = cm_get_per_vco_clk_hz(); /* get the clock prior L4 SP divider (periph_base_clk) */ - reg = readl(&clock_manager_base->per_pll.perbaseclk); + reg = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_PERPLL_PERBASECLK); clock /= (reg + 1); } /* get the L4 SP clock which supplied to UART */ - reg = readl(&clock_manager_base->main_pll.maindiv); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINDIV); reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >> CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET; clock = clock / (1 << reg); @@ -440,7 +469,7 @@ unsigned int cm_get_mmc_controller_clk_hz(void) u32 reg, clock = 0; /* identify the source of MMC clock */ - reg = readl(&clock_manager_base->per_pll.src); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC); reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >> CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET; @@ -450,13 +479,15 @@ unsigned int cm_get_mmc_controller_clk_hz(void) clock = cm_get_main_vco_clk_hz(); /* get the SDMMC clock */ - reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk); + reg = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK); clock /= (reg + 1); } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) { clock = cm_get_per_vco_clk_hz(); /* get the SDMMC clock */ - reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk); + reg = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK); clock /= (reg + 1); } @@ -470,7 +501,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void) u32 reg, clock = 0; /* identify the source of QSPI clock */ - reg = readl(&clock_manager_base->per_pll.src); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC); reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >> CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET; @@ -480,13 +511,15 @@ unsigned int cm_get_qspi_controller_clk_hz(void) clock = cm_get_main_vco_clk_hz(); /* get the qspi clock */ - reg = readl(&clock_manager_base->main_pll.mainqspiclk); + reg = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_MAINPLL_MAINQSPICLK); clock /= (reg + 1); } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) { clock = cm_get_per_vco_clk_hz(); /* get the qspi clock */ - reg = readl(&clock_manager_base->per_pll.perqspiclk); + reg = readl(socfpga_get_clkmgr_addr() + + CLKMGR_GEN5_PERPLL_PERQSPICLK); clock /= (reg + 1); } @@ -500,7 +533,7 @@ unsigned int cm_get_spi_controller_clk_hz(void) clock = cm_get_per_vco_clk_hz(); /* get the clock prior L4 SP divider (periph_base_clk) */ - reg = readl(&clock_manager_base->per_pll.perbaseclk); + reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERBASECLK); clock /= (reg + 1); return clock; |