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-rw-r--r--arch/arm/mach-snapdragon/Makefile2
-rw-r--r--arch/arm/mach-snapdragon/clock-apq8016.c5
-rw-r--r--arch/arm/mach-snapdragon/clock-apq8096.c5
-rw-r--r--arch/arm/mach-snapdragon/clock-qcs404.c40
-rw-r--r--arch/arm/mach-snapdragon/clock-sdm845.c5
-rw-r--r--arch/arm/mach-snapdragon/clock-snapdragon.c7
-rw-r--r--arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h17
-rw-r--r--arch/arm/mach-snapdragon/pinctrl-snapdragon.c39
8 files changed, 113 insertions, 7 deletions
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index 0d31f10f68..cbaaf23f6b 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -16,6 +16,6 @@ obj-y += pinctrl-snapdragon.o
obj-y += pinctrl-apq8016.o
obj-y += pinctrl-apq8096.o
obj-y += pinctrl-qcs404.o
-obj-$(CONFIG_SDM845) += pinctrl-sdm845.o
+obj-y += pinctrl-sdm845.o
obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o
obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c b/arch/arm/mach-snapdragon/clock-apq8016.c
index 6e4a0ccb90..23a37a1714 100644
--- a/arch/arm/mach-snapdragon/clock-apq8016.c
+++ b/arch/arm/mach-snapdragon/clock-apq8016.c
@@ -111,3 +111,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
return 0;
}
}
+
+int msm_enable(struct clk *clk)
+{
+ return 0;
+}
diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c
index e5011be8f2..66184596d5 100644
--- a/arch/arm/mach-snapdragon/clock-apq8096.c
+++ b/arch/arm/mach-snapdragon/clock-apq8096.c
@@ -93,3 +93,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
return 0;
}
}
+
+int msm_enable(struct clk *clk)
+{
+ return 0;
+}
diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c b/arch/arm/mach-snapdragon/clock-qcs404.c
index bb8a6fe067..6fe92afe8d 100644
--- a/arch/arm/mach-snapdragon/clock-qcs404.c
+++ b/arch/arm/mach-snapdragon/clock-qcs404.c
@@ -47,6 +47,14 @@ static struct pll_vote_clk gpll0_vote_clk = {
.vote_bit = BIT(0),
};
+static const struct bcr_regs usb30_master_regs = {
+ .cfg_rcgr = USB30_MASTER_CFG_RCGR,
+ .cmd_rcgr = USB30_MASTER_CMD_RCGR,
+ .M = USB30_MASTER_M,
+ .N = USB30_MASTER_N,
+ .D = USB30_MASTER_D,
+};
+
ulong msm_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -77,3 +85,35 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
return 0;
}
+
+int msm_enable(struct clk *clk)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case GCC_USB30_MASTER_CLK:
+ clk_enable_cbc(priv->base + USB30_MASTER_CBCR);
+ clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0,
+ CFG_CLK_SRC_GPLL0);
+ break;
+ case GCC_SYS_NOC_USB3_CLK:
+ clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR);
+ break;
+ case GCC_USB30_SLEEP_CLK:
+ clk_enable_cbc(priv->base + USB30_SLEEP_CBCR);
+ break;
+ case GCC_USB30_MOCK_UTMI_CLK:
+ clk_enable_cbc(priv->base + USB30_MOCK_UTMI_CBCR);
+ break;
+ case GCC_USB_HS_PHY_CFG_AHB_CLK:
+ clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
+ break;
+ case GCC_USB2A_PHY_SLEEP_CLK:
+ clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
+ break;
+ default:
+ return 0;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c b/arch/arm/mach-snapdragon/clock-sdm845.c
index f69be80898..d6df0365af 100644
--- a/arch/arm/mach-snapdragon/clock-sdm845.c
+++ b/arch/arm/mach-snapdragon/clock-sdm845.c
@@ -91,3 +91,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
return 0;
}
}
+
+int msm_enable(struct clk *clk)
+{
+ return 0;
+}
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c
index 5652d2fa36..fda7098274 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.c
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.c
@@ -20,6 +20,7 @@
#define CBCR_BRANCH_OFF_BIT BIT(31)
extern ulong msm_set_rate(struct clk *clk, ulong rate);
+extern int msm_enable(struct clk *clk);
/* Enable clock controlled by CBC soft macro */
void clk_enable_cbc(phys_addr_t cbcr)
@@ -126,8 +127,14 @@ static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
return msm_set_rate(clk, rate);
}
+static int msm_clk_enable(struct clk *clk)
+{
+ return msm_enable(clk);
+}
+
static struct clk_ops msm_clk_ops = {
.set_rate = msm_clk_set_rate,
+ .enable = msm_clk_enable,
};
static const struct udevice_id msm_clk_ids[] = {
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
index 4dc96b9fbc..e448faad2d 100644
--- a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
@@ -37,4 +37,21 @@
#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018)
#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C)
+/* USB-3.0 controller clock control registers */
+#define SYS_NOC_USB3_CBCR (0x26014)
+#define USB30_BCR (0x39000)
+#define USB3PHY_BCR (0x39008)
+#define USB30_MASTER_CBCR (0x3900C)
+#define USB30_SLEEP_CBCR (0x39010)
+#define USB30_MOCK_UTMI_CBCR (0x39014)
+#define USB30_MOCK_UTMI_CMD_RCGR (0x3901C)
+#define USB30_MOCK_UTMI_CFG_RCGR (0x39020)
+#define USB30_MASTER_CMD_RCGR (0x39028)
+#define USB30_MASTER_CFG_RCGR (0x3902C)
+#define USB30_MASTER_M (0x39030)
+#define USB30_MASTER_N (0x39034)
+#define USB30_MASTER_D (0x39038)
+#define USB2A_PHY_SLEEP_CBCR (0x4102C)
+#define USB_HS_PHY_CFG_AHB_CBCR (0x41030)
+
#endif
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
index c2148a5d0a..ab884ab6bf 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
@@ -10,6 +10,8 @@
#include <dm.h>
#include <errno.h>
#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
#include <dm/pinctrl.h>
#include <linux/bitops.h>
#include "pinctrl-snapdragon.h"
@@ -113,13 +115,37 @@ static struct pinctrl_ops msm_pinctrl_ops = {
.get_function_name = msm_get_function_name,
};
+static int msm_pinctrl_bind(struct udevice *dev)
+{
+ ofnode node = dev_ofnode(dev);
+ const char *name;
+ int ret;
+
+ ofnode_get_property(node, "gpio-controller", &ret);
+ if (ret < 0)
+ return 0;
+
+ /* Get the name of gpio node */
+ name = ofnode_get_name(node);
+ if (!name)
+ return -EINVAL;
+
+ /* Bind gpio node */
+ ret = device_bind_driver_to_node(dev, "gpio_msm",
+ name, node, NULL);
+ if (ret)
+ return ret;
+
+ dev_dbg(dev, "bind %s\n", name);
+
+ return 0;
+}
+
static const struct udevice_id msm_pinctrl_ids[] = {
- { .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data },
- { .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data },
-#ifdef CONFIG_SDM845
- { .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data },
-#endif
- { .compatible = "qcom,tlmm-qcs404", .data = (ulong)&qcs404_data },
+ { .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data },
+ { .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data },
+ { .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data },
+ { .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data },
{ }
};
@@ -130,4 +156,5 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = {
.priv_auto = sizeof(struct msm_pinctrl_priv),
.ops = &msm_pinctrl_ops,
.probe = msm_pinctrl_probe,
+ .bind = msm_pinctrl_bind,
};
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-01 22:12:17 +0000