diff options
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/apb_misc.h (renamed from arch/arm/include/asm/arch-tegra20/apb_misc.h) | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/board.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/pinmux.h | 185 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/usb.h | 223 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra114/pinmux.h | 836 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra114/usb.h | 156 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra124/pinmux.h | 866 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra124/usb.h | 268 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra20/pinmux.h | 372 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra20/usb.h | 155 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra30/pinmux.h | 963 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra30/usb.h | 168 |
12 files changed, 1455 insertions, 2740 deletions
diff --git a/arch/arm/include/asm/arch-tegra20/apb_misc.h b/arch/arm/include/asm/arch-tegra/apb_misc.h index f314f5acc38..a5bc092ffdc 100644 --- a/arch/arm/include/asm/arch-tegra20/apb_misc.h +++ b/arch/arm/include/asm/arch-tegra/apb_misc.h @@ -11,6 +11,8 @@ struct apb_misc_pp_ctlr { u32 reserved0[2]; u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */ + u32 reserved1[6]; /* 0x0c .. 0x20 */ + u32 cfg_ctl; /* 0x24 */ }; /* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */ diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h index 0e698644a0a..ff773646cbe 100644 --- a/arch/arm/include/asm/arch-tegra/board.h +++ b/arch/arm/include/asm/arch-tegra/board.h @@ -24,6 +24,7 @@ void gpio_early_init(void); /* overrideable GPIO config */ * an empty stub function will be called. */ +void pinmux_init(void); /* overrideable general pinmux setup */ void pin_mux_usb(void); /* overrideable USB pinmux setup */ void pin_mux_spi(void); /* overrideable SPI pinmux setup */ void pin_mux_nand(void); /* overrideable NAND pinmux setup */ diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h new file mode 100644 index 00000000000..035159d6653 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -0,0 +1,185 @@ +/* + * (C) Copyright 2010-2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA_PINMUX_H_ +#define _TEGRA_PINMUX_H_ + +#include <asm/arch/tegra.h> + +/* The pullup/pulldown state of a pin group */ +enum pmux_pull { + PMUX_PULL_NORMAL = 0, + PMUX_PULL_DOWN, + PMUX_PULL_UP, +}; + +/* Defines whether a pin group is tristated or in normal operation */ +enum pmux_tristate { + PMUX_TRI_NORMAL = 0, + PMUX_TRI_TRISTATE = 1, +}; + +#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC +enum pmux_pin_io { + PMUX_PIN_OUTPUT = 0, + PMUX_PIN_INPUT = 1, + PMUX_PIN_NONE, +}; + +enum pmux_pin_lock { + PMUX_PIN_LOCK_DEFAULT = 0, + PMUX_PIN_LOCK_DISABLE, + PMUX_PIN_LOCK_ENABLE, +}; + +enum pmux_pin_od { + PMUX_PIN_OD_DEFAULT = 0, + PMUX_PIN_OD_DISABLE, + PMUX_PIN_OD_ENABLE, +}; + +enum pmux_pin_ioreset { + PMUX_PIN_IO_RESET_DEFAULT = 0, + PMUX_PIN_IO_RESET_DISABLE, + PMUX_PIN_IO_RESET_ENABLE, +}; + +#ifdef TEGRA_PMX_HAS_RCV_SEL +enum pmux_pin_rcv_sel { + PMUX_PIN_RCV_SEL_DEFAULT = 0, + PMUX_PIN_RCV_SEL_NORMAL, + PMUX_PIN_RCV_SEL_HIGH, +}; +#endif /* TEGRA_PMX_HAS_RCV_SEL */ +#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */ + +/* + * This defines the configuration for a pin, including the function assigned, + * pull up/down settings and tristate settings. Having set up one of these + * you can call pinmux_config_pingroup() to configure a pin in one step. Also + * available is pinmux_config_table() to configure a list of pins. + */ +struct pmux_pingrp_config { + u32 pingrp:16; /* pin group PMUX_PINGRP_... */ + u32 func:8; /* function to assign PMUX_FUNC_... */ + u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/ + u32 tristate:2; /* tristate or normal PMUX_TRI_... */ +#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC + u32 io:2; /* input or output PMUX_PIN_... */ + u32 lock:2; /* lock enable/disable PMUX_PIN... */ + u32 od:2; /* open-drain or push-pull driver */ + u32 ioreset:2; /* input/output reset PMUX_PIN... */ +#ifdef TEGRA_PMX_HAS_RCV_SEL + u32 rcv_sel:2; /* select between High and Normal */ + /* VIL/VIH receivers */ +#endif +#endif +}; + +/* Set the mux function for a pin group */ +void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); + +/* Set the pull up/down feature for a pin group */ +void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); + +/* Set a pin group to tristate */ +void pinmux_tristate_enable(enum pmux_pingrp pin); + +/* Set a pin group to normal (non tristate) */ +void pinmux_tristate_disable(enum pmux_pingrp pin); + +#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC +/* Set a pin group as input or output */ +void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); +#endif + +/** + * Configure a list of pin groups + * + * @param config List of config items + * @param len Number of config items in list + */ +void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, + int len); + +#ifdef TEGRA_PMX_HAS_DRVGRPS + +#define PMUX_SLWF_MIN 0 +#define PMUX_SLWF_MAX 3 +#define PMUX_SLWF_NONE -1 + +#define PMUX_SLWR_MIN 0 +#define PMUX_SLWR_MAX 3 +#define PMUX_SLWR_NONE -1 + +#define PMUX_DRVUP_MIN 0 +#define PMUX_DRVUP_MAX 127 +#define PMUX_DRVUP_NONE -1 + +#define PMUX_DRVDN_MIN 0 +#define PMUX_DRVDN_MAX 127 +#define PMUX_DRVDN_NONE -1 + +/* Defines a pin group cfg's low-power mode select */ +enum pmux_lpmd { + PMUX_LPMD_X8 = 0, + PMUX_LPMD_X4, + PMUX_LPMD_X2, + PMUX_LPMD_X, + PMUX_LPMD_NONE = -1, +}; + +/* Defines whether a pin group cfg's schmidt is enabled or not */ +enum pmux_schmt { + PMUX_SCHMT_DISABLE = 0, + PMUX_SCHMT_ENABLE = 1, + PMUX_SCHMT_NONE = -1, +}; + +/* Defines whether a pin group cfg's high-speed mode is enabled or not */ +enum pmux_hsm { + PMUX_HSM_DISABLE = 0, + PMUX_HSM_ENABLE = 1, + PMUX_HSM_NONE = -1, +}; + +/* + * This defines the configuration for a pin group's pad control config + */ +struct pmux_drvgrp_config { + u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */ + u32 slwf:3; /* falling edge slew */ + u32 slwr:3; /* rising edge slew */ + u32 drvup:8; /* pull-up drive strength */ + u32 drvdn:8; /* pull-down drive strength */ + u32 lpmd:3; /* low-power mode selection */ + u32 schmt:2; /* schmidt enable */ + u32 hsm:2; /* high-speed mode enable */ +}; + +/** + * Set the GP pad configs + * + * @param config List of config items + * @param len Number of config items in list + */ +void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, + int len); + +#endif /* TEGRA_PMX_HAS_DRVGRPS */ + +struct pmux_pingrp_desc { + u8 funcs[4]; +#if defined(CONFIG_TEGRA20) + u8 ctl_id; + u8 pull_id; +#endif /* CONFIG_TEGRA20 */ +}; + +extern const struct pmux_pingrp_desc *tegra_soc_pingroups; + +#endif /* _TEGRA_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h index a1efd07c7d9..ceb7bcd9cfb 100644 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ b/arch/arm/include/asm/arch-tegra/usb.h @@ -8,6 +8,189 @@ #ifndef _TEGRA_USB_H_ #define _TEGRA_USB_H_ +/* USB Controller (USBx_CONTROLLER_) regs */ +struct usb_ctlr { + /* 0x000 */ + uint id; + uint reserved0; + uint host; + uint device; + + /* 0x010 */ + uint txbuf; + uint rxbuf; + uint reserved1[2]; + + /* 0x020 */ + uint reserved2[56]; + + /* 0x100 */ + u16 cap_length; + u16 hci_version; + uint hcs_params; + uint hcc_params; + uint reserved3[5]; + + /* 0x120 */ + uint dci_version; + uint dcc_params; + uint reserved4[2]; + +#ifdef CONFIG_TEGRA20 + /* 0x130 */ + uint reserved4_2[4]; + + /* 0x140 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x150 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint async_tt_sts; + + /* 0x160 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; /* is this port_sc1 on some controllers? */ + uint icusb_ctrl; + + /* 0x170 */ + uint ulpi_viewport; + uint reserved7; + uint endpt_nak; + uint endpt_nak_enable; + + /* 0x180 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x1a0 */ + uint reserved9; + uint otgsc; + uint usb_mode; + uint endpt_setup_stat; + + /* 0x1b0 */ + uint reserved10[20]; + + /* 0x200 */ + uint reserved11[0x80]; +#else + /* 0x130 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x140 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint reserved5_1; + + /* 0x150 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; + uint icusb_ctrl; + + /* 0x160 */ + uint ulpi_viewport; + uint reserved7[3]; + + /* 0x170 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x190 */ + uint reserved9[8]; + + /* 0x1b0 */ + uint reserved10; + uint hostpc1_devlc; + uint reserved10_1[2]; + + /* 0x1c0 */ + uint reserved10_2[4]; + + /* 0x1d0 */ + uint reserved10_3[4]; + + /* 0x1e0 */ + uint reserved10_4[4]; + + /* 0x1f0 */ + uint reserved10_5; + uint otgsc; + uint usb_mode; + uint reserved10_6; + + /* 0x200 */ + uint endpt_nak; + uint endpt_nak_enable; + uint endpt_setup_stat; + uint reserved11_1[0x7D]; +#endif + + /* 0x400 */ + uint susp_ctrl; + uint phy_vbus_sensors; + uint phy_vbus_wakeup_id; + uint phy_alt_vbus_sys; + +#ifdef CONFIG_TEGRA20 + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[4]; + + /* 0x424 */ + uint ulpi_timing_ctrl_0; + uint ulpi_timing_ctrl_1; + uint reserved13[53]; +#else + + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[3]; + + /* 0x420 */ + uint reserved13[56]; +#endif + + /* 0x500 */ + uint reserved14[64 * 3]; + + /* 0x800 */ + uint utmip_pll_cfg0; + uint utmip_pll_cfg1; + uint utmip_xcvr_cfg0; + uint utmip_bias_cfg0; + + /* 0x810 */ + uint utmip_hsrx_cfg0; + uint utmip_hsrx_cfg1; + uint utmip_fslsrx_cfg0; + uint utmip_fslsrx_cfg1; + + /* 0x820 */ + uint utmip_tx_cfg0; + uint utmip_misc_cfg0; + uint utmip_misc_cfg1; + uint utmip_debounce_cfg0; + + /* 0x830 */ + uint utmip_bat_chrg_cfg0; + uint utmip_spare_cfg0; + uint utmip_xcvr_cfg1; + uint utmip_bias_cfg1; +}; + /* USB1_LEGACY_CTRL */ #define USB1_NO_LEGACY_MODE 1 @@ -24,22 +207,46 @@ #define USB_PHY_CLK_VALID (1 << 7) #define USB_SUSP_CLR (1 << 5) +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) /* USB2_IF_USB_SUSP_CTRL_0 */ #define ULPI_PHY_ENB (1 << 13) +/* USB2_IF_ULPI_TIMING_CTRL_0 */ +#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) +#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) + +/* USB2_IF_ULPI_TIMING_CTRL_1 */ +#define ULPI_DATA_TRIMMER_LOAD (1 << 0) +#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) +#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) +#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) +#define ULPI_DIR_TRIMMER_LOAD (1 << 24) +#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) +#endif + /* USBx_UTMIP_MISC_CFG0 */ #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) /* USBx_UTMIP_MISC_CFG1 */ +#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) + +/* + * Tegra 3 and later: Moved to Clock and Reset register space, see + * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 + */ #define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 #define UTMIP_PLLU_STABLE_COUNT_MASK \ (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) +/* + * Tegra 3 and later: Moved to Clock and Reset register space, see + * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 + */ #define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 #define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) -#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) /* USBx_UTMIP_PLL_CFG1_0 */ +/* Tegra 3 and later: Moved to Clock and Reset register space */ #define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 #define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) @@ -91,11 +298,23 @@ /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ #define IC_ENB1 (1 << 3) -/* PORTSC1, USB1, defined for Tegra20 */ +#ifdef CONFIG_TEGRA20 +/* PORTSC1, USB1 */ #define PTS1_SHIFT 31 #define PTS1_MASK (1 << PTS1_SHIFT) #define STS1 (1 << 30) +/* PORTSC, USB2, USB3 */ +#define PTS_SHIFT 30 +#define PTS_MASK (3U << PTS_SHIFT) +#define STS (1 << 29) +#else +/* USB2D_HOSTPC1_DEVLC_0 */ +#define PTS_SHIFT 29 +#define PTS_MASK (0x7U << PTS_SHIFT) +#define STS (1 << 28) +#endif + #define PTS_UTMI 0 #define PTS_RESERVED 1 #define PTS_ULPI 2 diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index 9c22c08b6e3..c1cb3ef16b1 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -1,616 +1,320 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA114_PINMUX_H_ #define _TEGRA114_PINMUX_H_ -/* - * Pin groups which we adjust. There are three basic attributes of each pin - * group which use this enum: - * - * - function - * - pullup / pulldown - * - tristate or normal - */ enum pmux_pingrp { - PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */ - PINGRP_ULPI_DATA1, - PINGRP_ULPI_DATA2, - PINGRP_ULPI_DATA3, - PINGRP_ULPI_DATA4, - PINGRP_ULPI_DATA5, - PINGRP_ULPI_DATA6, - PINGRP_ULPI_DATA7, - PINGRP_ULPI_CLK, - PINGRP_ULPI_DIR, - PINGRP_ULPI_NXT, - PINGRP_ULPI_STP, - PINGRP_DAP3_FS, - PINGRP_DAP3_DIN, - PINGRP_DAP3_DOUT, - PINGRP_DAP3_SCLK, - PINGRP_GPIO_PV0, - PINGRP_GPIO_PV1, - PINGRP_SDMMC1_CLK, - PINGRP_SDMMC1_CMD, - PINGRP_SDMMC1_DAT3, - PINGRP_SDMMC1_DAT2, - PINGRP_SDMMC1_DAT1, - PINGRP_SDMMC1_DAT0, - PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3, - PINGRP_CLK2_REQ, - PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41, - PINGRP_DDC_SCL, - PINGRP_DDC_SDA, - PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19, - PINGRP_UART2_TXD, - PINGRP_UART2_RTS_N, - PINGRP_UART2_CTS_N, - PINGRP_UART3_TXD, - PINGRP_UART3_RXD, - PINGRP_UART3_CTS_N, - PINGRP_UART3_RTS_N, - PINGRP_GPIO_PU0, - PINGRP_GPIO_PU1, - PINGRP_GPIO_PU2, - PINGRP_GPIO_PU3, - PINGRP_GPIO_PU4, - PINGRP_GPIO_PU5, - PINGRP_GPIO_PU6, - PINGRP_GEN1_I2C_SDA, - PINGRP_GEN1_I2C_SCL, - PINGRP_DAP4_FS, - PINGRP_DAP4_DIN, - PINGRP_DAP4_DOUT, - PINGRP_DAP4_SCLK, - PINGRP_CLK3_OUT, - PINGRP_CLK3_REQ, - PINGRP_GMI_WP_N, - PINGRP_GMI_IORDY, - PINGRP_GMI_WAIT, - PINGRP_GMI_ADV_N, - PINGRP_GMI_CLK, - PINGRP_GMI_CS0_N, - PINGRP_GMI_CS1_N, - PINGRP_GMI_CS2_N, - PINGRP_GMI_CS3_N, - PINGRP_GMI_CS4_N, - PINGRP_GMI_CS6_N, - PINGRP_GMI_CS7_N, - PINGRP_GMI_AD0, - PINGRP_GMI_AD1, - PINGRP_GMI_AD2, - PINGRP_GMI_AD3, - PINGRP_GMI_AD4, - PINGRP_GMI_AD5, - PINGRP_GMI_AD6, - PINGRP_GMI_AD7, - PINGRP_GMI_AD8, - PINGRP_GMI_AD9, - PINGRP_GMI_AD10, - PINGRP_GMI_AD11, - PINGRP_GMI_AD12, - PINGRP_GMI_AD13, - PINGRP_GMI_AD14, - PINGRP_GMI_AD15, - PINGRP_GMI_A16, - PINGRP_GMI_A17, - PINGRP_GMI_A18, - PINGRP_GMI_A19, - PINGRP_GMI_WR_N, - PINGRP_GMI_OE_N, - PINGRP_GMI_DQS, - PINGRP_GMI_RST_N, - PINGRP_GEN2_I2C_SCL, - PINGRP_GEN2_I2C_SDA, - PINGRP_SDMMC4_CLK, - PINGRP_SDMMC4_CMD, - PINGRP_SDMMC4_DAT0, - PINGRP_SDMMC4_DAT1, - PINGRP_SDMMC4_DAT2, - PINGRP_SDMMC4_DAT3, - PINGRP_SDMMC4_DAT4, - PINGRP_SDMMC4_DAT5, - PINGRP_SDMMC4_DAT6, - PINGRP_SDMMC4_DAT7, - PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2, - PINGRP_GPIO_PCC1, - PINGRP_GPIO_PBB0, - PINGRP_CAM_I2C_SCL, - PINGRP_CAM_I2C_SDA, - PINGRP_GPIO_PBB3, - PINGRP_GPIO_PBB4, - PINGRP_GPIO_PBB5, - PINGRP_GPIO_PBB6, - PINGRP_GPIO_PBB7, - PINGRP_GPIO_PCC2, - PINGRP_JTAG_RTCK, - PINGRP_PWR_I2C_SCL, - PINGRP_PWR_I2C_SDA, - PINGRP_KB_ROW0, - PINGRP_KB_ROW1, - PINGRP_KB_ROW2, - PINGRP_KB_ROW3, - PINGRP_KB_ROW4, - PINGRP_KB_ROW5, - PINGRP_KB_ROW6, - PINGRP_KB_ROW7, - PINGRP_KB_ROW8, - PINGRP_KB_ROW9, - PINGRP_KB_ROW10, - PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6, - PINGRP_KB_COL1, - PINGRP_KB_COL2, - PINGRP_KB_COL3, - PINGRP_KB_COL4, - PINGRP_KB_COL5, - PINGRP_KB_COL6, - PINGRP_KB_COL7, - PINGRP_CLK_32K_OUT, - PINGRP_SYS_CLK_REQ, - PINGRP_CORE_PWR_REQ, - PINGRP_CPU_PWR_REQ, - PINGRP_PWR_INT_N, - PINGRP_CLK_32K_IN, - PINGRP_OWR, - PINGRP_DAP1_FS, - PINGRP_DAP1_DIN, - PINGRP_DAP1_DOUT, - PINGRP_DAP1_SCLK, - PINGRP_CLK1_REQ, - PINGRP_CLK1_OUT, - PINGRP_SPDIF_IN, - PINGRP_SPDIF_OUT, - PINGRP_DAP2_FS, - PINGRP_DAP2_DIN, - PINGRP_DAP2_DOUT, - PINGRP_DAP2_SCLK, - PINGRP_DVFS_PWM, - PINGRP_GPIO_X1_AUD, - PINGRP_GPIO_X3_AUD, - PINGRP_DVFS_CLK, - PINGRP_GPIO_X4_AUD, - PINGRP_GPIO_X5_AUD, - PINGRP_GPIO_X6_AUD, - PINGRP_GPIO_X7_AUD, - PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3, - PINGRP_SDMMC3_CMD, - PINGRP_SDMMC3_DAT0, - PINGRP_SDMMC3_DAT1, - PINGRP_SDMMC3_DAT2, - PINGRP_SDMMC3_DAT3, - PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */ - PINGRP_SDMMC1_WP_N, - PINGRP_SDMMC3_CD_N, - PINGRP_GPIO_W2_AUD, - PINGRP_GPIO_W3_AUD, - PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */ - PINGRP_USB_VBUS_EN1, - PINGRP_SDMMC3_CLK_LB_IN, - PINGRP_SDMMC3_CLK_LB_OUT, - PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2, - PINGRP_COUNT, + PMUX_PINGRP_ULPI_DATA0_PO1, + PMUX_PINGRP_ULPI_DATA1_PO2, + PMUX_PINGRP_ULPI_DATA2_PO3, + PMUX_PINGRP_ULPI_DATA3_PO4, + PMUX_PINGRP_ULPI_DATA4_PO5, + PMUX_PINGRP_ULPI_DATA5_PO6, + PMUX_PINGRP_ULPI_DATA6_PO7, + PMUX_PINGRP_ULPI_DATA7_PO0, + PMUX_PINGRP_ULPI_CLK_PY0, + PMUX_PINGRP_ULPI_DIR_PY1, + PMUX_PINGRP_ULPI_NXT_PY2, + PMUX_PINGRP_ULPI_STP_PY3, + PMUX_PINGRP_DAP3_FS_PP0, + PMUX_PINGRP_DAP3_DIN_PP1, + PMUX_PINGRP_DAP3_DOUT_PP2, + PMUX_PINGRP_DAP3_SCLK_PP3, + PMUX_PINGRP_PV0, + PMUX_PINGRP_PV1, + PMUX_PINGRP_SDMMC1_CLK_PZ0, + PMUX_PINGRP_SDMMC1_CMD_PZ1, + PMUX_PINGRP_SDMMC1_DAT3_PY4, + PMUX_PINGRP_SDMMC1_DAT2_PY5, + PMUX_PINGRP_SDMMC1_DAT1_PY6, + PMUX_PINGRP_SDMMC1_DAT0_PY7, + PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4), + PMUX_PINGRP_CLK2_REQ_PCC5, + PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4), + PMUX_PINGRP_DDC_SCL_PV4, + PMUX_PINGRP_DDC_SDA_PV5, + PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4), + PMUX_PINGRP_UART2_TXD_PC2, + PMUX_PINGRP_UART2_RTS_N_PJ6, + PMUX_PINGRP_UART2_CTS_N_PJ5, + PMUX_PINGRP_UART3_TXD_PW6, + PMUX_PINGRP_UART3_RXD_PW7, + PMUX_PINGRP_UART3_CTS_N_PA1, + PMUX_PINGRP_UART3_RTS_N_PC0, + PMUX_PINGRP_PU0, + PMUX_PINGRP_PU1, + PMUX_PINGRP_PU2, + PMUX_PINGRP_PU3, + PMUX_PINGRP_PU4, + PMUX_PINGRP_PU5, + PMUX_PINGRP_PU6, + PMUX_PINGRP_GEN1_I2C_SDA_PC5, + PMUX_PINGRP_GEN1_I2C_SCL_PC4, + PMUX_PINGRP_DAP4_FS_PP4, + PMUX_PINGRP_DAP4_DIN_PP5, + PMUX_PINGRP_DAP4_DOUT_PP6, + PMUX_PINGRP_DAP4_SCLK_PP7, + PMUX_PINGRP_CLK3_OUT_PEE0, + PMUX_PINGRP_CLK3_REQ_PEE1, + PMUX_PINGRP_GMI_WP_N_PC7, + PMUX_PINGRP_GMI_IORDY_PI5, + PMUX_PINGRP_GMI_WAIT_PI7, + PMUX_PINGRP_GMI_ADV_N_PK0, + PMUX_PINGRP_GMI_CLK_PK1, + PMUX_PINGRP_GMI_CS0_N_PJ0, + PMUX_PINGRP_GMI_CS1_N_PJ2, + PMUX_PINGRP_GMI_CS2_N_PK3, + PMUX_PINGRP_GMI_CS3_N_PK4, + PMUX_PINGRP_GMI_CS4_N_PK2, + PMUX_PINGRP_GMI_CS6_N_PI3, + PMUX_PINGRP_GMI_CS7_N_PI6, + PMUX_PINGRP_GMI_AD0_PG0, + PMUX_PINGRP_GMI_AD1_PG1, + PMUX_PINGRP_GMI_AD2_PG2, + PMUX_PINGRP_GMI_AD3_PG3, + PMUX_PINGRP_GMI_AD4_PG4, + PMUX_PINGRP_GMI_AD5_PG5, + PMUX_PINGRP_GMI_AD6_PG6, + PMUX_PINGRP_GMI_AD7_PG7, + PMUX_PINGRP_GMI_AD8_PH0, + PMUX_PINGRP_GMI_AD9_PH1, + PMUX_PINGRP_GMI_AD10_PH2, + PMUX_PINGRP_GMI_AD11_PH3, + PMUX_PINGRP_GMI_AD12_PH4, + PMUX_PINGRP_GMI_AD13_PH5, + PMUX_PINGRP_GMI_AD14_PH6, + PMUX_PINGRP_GMI_AD15_PH7, + PMUX_PINGRP_GMI_A16_PJ7, + PMUX_PINGRP_GMI_A17_PB0, + PMUX_PINGRP_GMI_A18_PB1, + PMUX_PINGRP_GMI_A19_PK7, + PMUX_PINGRP_GMI_WR_N_PI0, + PMUX_PINGRP_GMI_OE_N_PI1, + PMUX_PINGRP_GMI_DQS_P_PJ3, + PMUX_PINGRP_GMI_RST_N_PI4, + PMUX_PINGRP_GEN2_I2C_SCL_PT5, + PMUX_PINGRP_GEN2_I2C_SDA_PT6, + PMUX_PINGRP_SDMMC4_CLK_PCC4, + PMUX_PINGRP_SDMMC4_CMD_PT7, + PMUX_PINGRP_SDMMC4_DAT0_PAA0, + PMUX_PINGRP_SDMMC4_DAT1_PAA1, + PMUX_PINGRP_SDMMC4_DAT2_PAA2, + PMUX_PINGRP_SDMMC4_DAT3_PAA3, + PMUX_PINGRP_SDMMC4_DAT4_PAA4, + PMUX_PINGRP_SDMMC4_DAT5_PAA5, + PMUX_PINGRP_SDMMC4_DAT6_PAA6, + PMUX_PINGRP_SDMMC4_DAT7_PAA7, + PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4), + PMUX_PINGRP_PCC1, + PMUX_PINGRP_PBB0, + PMUX_PINGRP_CAM_I2C_SCL_PBB1, + PMUX_PINGRP_CAM_I2C_SDA_PBB2, + PMUX_PINGRP_PBB3, + PMUX_PINGRP_PBB4, + PMUX_PINGRP_PBB5, + PMUX_PINGRP_PBB6, + PMUX_PINGRP_PBB7, + PMUX_PINGRP_PCC2, + PMUX_PINGRP_JTAG_RTCK, + PMUX_PINGRP_PWR_I2C_SCL_PZ6, + PMUX_PINGRP_PWR_I2C_SDA_PZ7, + PMUX_PINGRP_KB_ROW0_PR0, + PMUX_PINGRP_KB_ROW1_PR1, + PMUX_PINGRP_KB_ROW2_PR2, + PMUX_PINGRP_KB_ROW3_PR3, + PMUX_PINGRP_KB_ROW4_PR4, + PMUX_PINGRP_KB_ROW5_PR5, + PMUX_PINGRP_KB_ROW6_PR6, + PMUX_PINGRP_KB_ROW7_PR7, + PMUX_PINGRP_KB_ROW8_PS0, + PMUX_PINGRP_KB_ROW9_PS1, + PMUX_PINGRP_KB_ROW10_PS2, + PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4), + PMUX_PINGRP_KB_COL1_PQ1, + PMUX_PINGRP_KB_COL2_PQ2, + PMUX_PINGRP_KB_COL3_PQ3, + PMUX_PINGRP_KB_COL4_PQ4, + PMUX_PINGRP_KB_COL5_PQ5, + PMUX_PINGRP_KB_COL6_PQ6, + PMUX_PINGRP_KB_COL7_PQ7, + PMUX_PINGRP_CLK_32K_OUT_PA0, + PMUX_PINGRP_SYS_CLK_REQ_PZ5, + PMUX_PINGRP_CORE_PWR_REQ, + PMUX_PINGRP_CPU_PWR_REQ, + PMUX_PINGRP_PWR_INT_N, + PMUX_PINGRP_CLK_32K_IN, + PMUX_PINGRP_OWR, + PMUX_PINGRP_DAP1_FS_PN0, + PMUX_PINGRP_DAP1_DIN_PN1, + PMUX_PINGRP_DAP1_DOUT_PN2, + PMUX_PINGRP_DAP1_SCLK_PN3, + PMUX_PINGRP_CLK1_REQ_PEE2, + PMUX_PINGRP_CLK1_OUT_PW4, + PMUX_PINGRP_SPDIF_IN_PK6, + PMUX_PINGRP_SPDIF_OUT_PK5, + PMUX_PINGRP_DAP2_FS_PA2, + PMUX_PINGRP_DAP2_DIN_PA4, + PMUX_PINGRP_DAP2_DOUT_PA5, + PMUX_PINGRP_DAP2_SCLK_PA3, + PMUX_PINGRP_DVFS_PWM_PX0, + PMUX_PINGRP_GPIO_X1_AUD_PX1, + PMUX_PINGRP_GPIO_X3_AUD_PX3, + PMUX_PINGRP_DVFS_CLK_PX2, + PMUX_PINGRP_GPIO_X4_AUD_PX4, + PMUX_PINGRP_GPIO_X5_AUD_PX5, + PMUX_PINGRP_GPIO_X6_AUD_PX6, + PMUX_PINGRP_GPIO_X7_AUD_PX7, + PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4), + PMUX_PINGRP_SDMMC3_CMD_PA7, + PMUX_PINGRP_SDMMC3_DAT0_PB7, + PMUX_PINGRP_SDMMC3_DAT1_PB6, + PMUX_PINGRP_SDMMC3_DAT2_PB5, + PMUX_PINGRP_SDMMC3_DAT3_PB4, + PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4), + PMUX_PINGRP_SDMMC1_WP_N_PV3, + PMUX_PINGRP_SDMMC3_CD_N_PV2, + PMUX_PINGRP_GPIO_W2_AUD_PW2, + PMUX_PINGRP_GPIO_W3_AUD_PW3, + PMUX_PINGRP_USB_VBUS_EN0_PN4, + PMUX_PINGRP_USB_VBUS_EN1_PN5, + PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5, + PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4, + PMUX_PINGRP_GMI_CLK_LB, + PMUX_PINGRP_RESET_OUT_N, + PMUX_PINGRP_COUNT, }; -enum pdrive_pingrp { - PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */ - PDRIVE_PINGROUP_AO2, - PDRIVE_PINGROUP_AT1, - PDRIVE_PINGROUP_AT2, - PDRIVE_PINGROUP_AT3, - PDRIVE_PINGROUP_AT4, - PDRIVE_PINGROUP_AT5, - PDRIVE_PINGROUP_CDEV1, - PDRIVE_PINGROUP_CDEV2, - PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */ - PDRIVE_PINGROUP_DAP2, - PDRIVE_PINGROUP_DAP3, - PDRIVE_PINGROUP_DAP4, - PDRIVE_PINGROUP_DBG, - PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */ - PDRIVE_PINGROUP_SPI, - PDRIVE_PINGROUP_UAA, - PDRIVE_PINGROUP_UAB, - PDRIVE_PINGROUP_UART2, - PDRIVE_PINGROUP_UART3, - PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */ - PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */ - PDRIVE_PINGROUP_GMA, - PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */ - PDRIVE_PINGROUP_GMF, - PDRIVE_PINGROUP_GMG, - PDRIVE_PINGROUP_GMH, - PDRIVE_PINGROUP_OWR, - PDRIVE_PINGROUP_UAD, - PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */ - PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */ - PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */ - PDRIVE_PINGROUP_DAP5, - PDRIVE_PINGROUP_VBUS, - PDRIVE_PINGROUP_AO3, - PDRIVE_PINGROUP_HVC, - PDRIVE_PINGROUP_SDIO4, - PDRIVE_PINGROUP_AO0, - PDRIVE_PINGROUP_COUNT, +enum pmux_drvgrp { + PMUX_DRVGRP_AO1, + PMUX_DRVGRP_AO2, + PMUX_DRVGRP_AT1, + PMUX_DRVGRP_AT2, + PMUX_DRVGRP_AT3, + PMUX_DRVGRP_AT4, + PMUX_DRVGRP_AT5, + PMUX_DRVGRP_CDEV1, + PMUX_DRVGRP_CDEV2, + PMUX_DRVGRP_DAP1 = (0x28 / 4), + PMUX_DRVGRP_DAP2, + PMUX_DRVGRP_DAP3, + PMUX_DRVGRP_DAP4, + PMUX_DRVGRP_DBG, + PMUX_DRVGRP_SDIO3 = (0x48 / 4), + PMUX_DRVGRP_SPI, + PMUX_DRVGRP_UAA, + PMUX_DRVGRP_UAB, + PMUX_DRVGRP_UART2, + PMUX_DRVGRP_UART3, + PMUX_DRVGRP_SDIO1 = (0x84 / 4), + PMUX_DRVGRP_DDC = (0x94 / 4), + PMUX_DRVGRP_GMA, + PMUX_DRVGRP_GME = (0xa8 / 4), + PMUX_DRVGRP_GMF, + PMUX_DRVGRP_GMG, + PMUX_DRVGRP_GMH, + PMUX_DRVGRP_OWR, + PMUX_DRVGRP_UDA, + PMUX_DRVGRP_DEV3 = (0xc4 / 4), + PMUX_DRVGRP_CEC = (0xd0 / 4), + PMUX_DRVGRP_AT6 = (0x12c / 4), + PMUX_DRVGRP_DAP5, + PMUX_DRVGRP_USB_VBUS_EN, + PMUX_DRVGRP_AO3, + PMUX_DRVGRP_HV0, + PMUX_DRVGRP_SDIO4, + PMUX_DRVGRP_AO0, + PMUX_DRVGRP_COUNT, }; -/* - * Functions which can be assigned to each of the pin groups. The values here - * bear no relation to the values programmed into pinmux registers and are - * purely a convenience. The translation is done through a table search. - */ enum pmux_func { - PMUX_FUNC_AHB_CLK, - PMUX_FUNC_APB_CLK, - PMUX_FUNC_AUDIO_SYNC, - PMUX_FUNC_CRT, - PMUX_FUNC_DAP1, - PMUX_FUNC_DAP2, - PMUX_FUNC_DAP3, - PMUX_FUNC_DAP4, - PMUX_FUNC_DAP5, - PMUX_FUNC_DISPA, - PMUX_FUNC_DISPB, - PMUX_FUNC_EMC_TEST0_DLL, - PMUX_FUNC_EMC_TEST1_DLL, - PMUX_FUNC_GMI, - PMUX_FUNC_GMI_INT, - PMUX_FUNC_HDMI, - PMUX_FUNC_I2C1, - PMUX_FUNC_I2C2, - PMUX_FUNC_I2C3, - PMUX_FUNC_IDE, - PMUX_FUNC_KBC, - PMUX_FUNC_MIO, - PMUX_FUNC_MIPI_HS, - PMUX_FUNC_NAND, - PMUX_FUNC_OSC, - PMUX_FUNC_OWR, - PMUX_FUNC_PCIE, - PMUX_FUNC_PLLA_OUT, - PMUX_FUNC_PLLC_OUT1, - PMUX_FUNC_PLLM_OUT1, - PMUX_FUNC_PLLP_OUT2, - PMUX_FUNC_PLLP_OUT3, - PMUX_FUNC_PLLP_OUT4, - PMUX_FUNC_PWM, - PMUX_FUNC_PWR_INTR, - PMUX_FUNC_PWR_ON, - PMUX_FUNC_RTCK, - PMUX_FUNC_SDMMC1, - PMUX_FUNC_SDMMC2, - PMUX_FUNC_SDMMC3, - PMUX_FUNC_SDMMC4, - PMUX_FUNC_SFLASH, - PMUX_FUNC_SPDIF, - PMUX_FUNC_SPI1, - PMUX_FUNC_SPI2, - PMUX_FUNC_SPI2_ALT, - PMUX_FUNC_SPI3, - PMUX_FUNC_SPI4, - PMUX_FUNC_TRACE, - PMUX_FUNC_TWC, - PMUX_FUNC_UARTA, - PMUX_FUNC_UARTB, - PMUX_FUNC_UARTC, - PMUX_FUNC_UARTD, - PMUX_FUNC_UARTE, - PMUX_FUNC_ULPI, - PMUX_FUNC_VI, - PMUX_FUNC_VI_SENSOR_CLK, - PMUX_FUNC_XIO, - /* End of Tegra2 MUX selectors */ PMUX_FUNC_BLINK, PMUX_FUNC_CEC, + PMUX_FUNC_CLDVFS, + PMUX_FUNC_CLK, PMUX_FUNC_CLK12, + PMUX_FUNC_CPU, PMUX_FUNC_DAP, - PMUX_FUNC_DAPSDMMC2, - PMUX_FUNC_DDR, + PMUX_FUNC_DAP1, + PMUX_FUNC_DAP2, PMUX_FUNC_DEV3, + PMUX_FUNC_DISPLAYA, + PMUX_FUNC_DISPLAYA_ALT, + PMUX_FUNC_DISPLAYB, PMUX_FUNC_DTV, - PMUX_FUNC_VI_ALT1, - PMUX_FUNC_VI_ALT2, - PMUX_FUNC_VI_ALT3, PMUX_FUNC_EMC_DLL, PMUX_FUNC_EXTPERIPH1, PMUX_FUNC_EXTPERIPH2, PMUX_FUNC_EXTPERIPH3, + PMUX_FUNC_GMI, PMUX_FUNC_GMI_ALT, PMUX_FUNC_HDA, PMUX_FUNC_HSI, + PMUX_FUNC_I2C1, + PMUX_FUNC_I2C2, + PMUX_FUNC_I2C3, PMUX_FUNC_I2C4, - PMUX_FUNC_I2C5, PMUX_FUNC_I2CPWR, PMUX_FUNC_I2S0, PMUX_FUNC_I2S1, PMUX_FUNC_I2S2, PMUX_FUNC_I2S3, PMUX_FUNC_I2S4, + PMUX_FUNC_IRDA, + PMUX_FUNC_KBC, + PMUX_FUNC_NAND, PMUX_FUNC_NAND_ALT, - PMUX_FUNC_POPSDIO4, - PMUX_FUNC_POPSDMMC4, + PMUX_FUNC_OWR, + PMUX_FUNC_PMI, PMUX_FUNC_PWM0, PMUX_FUNC_PWM1, PMUX_FUNC_PWM2, PMUX_FUNC_PWM3, - PMUX_FUNC_SATA, + PMUX_FUNC_PWRON, + PMUX_FUNC_RESET_OUT_N, + PMUX_FUNC_RTCK, + PMUX_FUNC_SDMMC1, + PMUX_FUNC_SDMMC2, + PMUX_FUNC_SDMMC3, + PMUX_FUNC_SDMMC4, + PMUX_FUNC_SOC, + PMUX_FUNC_SPDIF, + PMUX_FUNC_SPI1, + PMUX_FUNC_SPI2, + PMUX_FUNC_SPI3, + PMUX_FUNC_SPI4, PMUX_FUNC_SPI5, PMUX_FUNC_SPI6, PMUX_FUNC_SYSCLK, + PMUX_FUNC_TRACE, + PMUX_FUNC_UARTA, + PMUX_FUNC_UARTB, + PMUX_FUNC_UARTC, + PMUX_FUNC_UARTD, + PMUX_FUNC_ULPI, + PMUX_FUNC_USB, PMUX_FUNC_VGP1, PMUX_FUNC_VGP2, PMUX_FUNC_VGP3, PMUX_FUNC_VGP4, PMUX_FUNC_VGP5, PMUX_FUNC_VGP6, - /* End of Tegra3 MUX selectors */ - PMUX_FUNC_USB, - PMUX_FUNC_SOC, - PMUX_FUNC_CPU, - PMUX_FUNC_CLK, - PMUX_FUNC_PWRON, - PMUX_FUNC_PMI, - PMUX_FUNC_CLDVFS, - PMUX_FUNC_RESET_OUT_N, - /* End of Tegra114 MUX selectors */ - - PMUX_FUNC_SAFE, - PMUX_FUNC_MAX, - - PMUX_FUNC_INVALID = 0x4000, - PMUX_FUNC_RSVD1 = 0x8000, - PMUX_FUNC_RSVD2 = 0x8001, - PMUX_FUNC_RSVD3 = 0x8002, - PMUX_FUNC_RSVD4 = 0x8003, -}; - -/* return 1 if a pmux_func is in range */ -#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \ - || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4))) - -/* return 1 if a pingrp is in range */ -#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT)) - -/* The pullup/pulldown state of a pin group */ -enum pmux_pull { - PMUX_PULL_NORMAL = 0, - PMUX_PULL_DOWN, - PMUX_PULL_UP, -}; -/* return 1 if a pin_pupd_is in range */ -#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \ - ((pupd) <= PMUX_PULL_UP)) - -/* Defines whether a pin group is tristated or in normal operation */ -enum pmux_tristate { - PMUX_TRI_NORMAL = 0, - PMUX_TRI_TRISTATE = 1, -}; -/* return 1 if a pin_tristate_is in range */ -#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \ - && ((tristate) <= PMUX_TRI_TRISTATE)) - -enum pmux_pin_io { - PMUX_PIN_OUTPUT = 0, - PMUX_PIN_INPUT = 1, - PMUX_PIN_NONE, -}; -/* return 1 if a pin_io_is in range */ -#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \ - ((io) <= PMUX_PIN_INPUT)) - -enum pmux_pin_lock { - PMUX_PIN_LOCK_DEFAULT = 0, - PMUX_PIN_LOCK_DISABLE, - PMUX_PIN_LOCK_ENABLE, -}; -/* return 1 if a pin_lock is in range */ -#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \ - ((lock) <= PMUX_PIN_LOCK_ENABLE)) - -enum pmux_pin_od { - PMUX_PIN_OD_DEFAULT = 0, - PMUX_PIN_OD_DISABLE, - PMUX_PIN_OD_ENABLE, -}; -/* return 1 if a pin_od is in range */ -#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \ - ((od) <= PMUX_PIN_OD_ENABLE)) - -enum pmux_pin_ioreset { - PMUX_PIN_IO_RESET_DEFAULT = 0, - PMUX_PIN_IO_RESET_DISABLE, - PMUX_PIN_IO_RESET_ENABLE, -}; -/* return 1 if a pin_ioreset_is in range */ -#define pmux_pin_ioreset_isvalid(ioreset) \ - (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \ - ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE)) - -enum pmux_pin_rcv_sel { - PMUX_PIN_RCV_SEL_DEFAULT = 0, - PMUX_PIN_RCV_SEL_NORMAL, - PMUX_PIN_RCV_SEL_HIGH, -}; -/* return 1 if a pin_rcv_sel_is in range */ -#define pmux_pin_rcv_sel_isvalid(rcv_sel) \ - (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \ - ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH)) - -/* Available power domains used by pin groups */ -enum pmux_vddio { - PMUX_VDDIO_BB = 0, - PMUX_VDDIO_LCD, - PMUX_VDDIO_VI, - PMUX_VDDIO_UART, - PMUX_VDDIO_DDR, - PMUX_VDDIO_NAND, - PMUX_VDDIO_SYS, - PMUX_VDDIO_AUDIO, - PMUX_VDDIO_SD, - PMUX_VDDIO_CAM, - PMUX_VDDIO_GMI, - PMUX_VDDIO_PEXCTL, - PMUX_VDDIO_SDMMC1, - PMUX_VDDIO_SDMMC3, - PMUX_VDDIO_SDMMC4, - - PMUX_VDDIO_NONE -}; - -#define PGRP_SLWF_NONE -1 -#define PGRP_SLWF_MAX 3 -#define PGRP_SLWR_NONE PGRP_SLWF_NONE -#define PGRP_SLWR_MAX PGRP_SLWF_MAX - -#define PGRP_DRVUP_NONE -1 -#define PGRP_DRVUP_MAX 127 -#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE -#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX - -#define PGRP_SCHMT_NONE -1 -#define PGRP_HSM_NONE PGRP_SCHMT_NONE - -/* return 1 if a padgrp is in range */ -#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT)) - -/* return 1 if a slew-rate rising/falling edge value is in range */ -#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \ - (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX))) - -/* return 1 if a driver output pull-up/down strength code value is in range */ -#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \ - (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX))) - -/* return 1 if a low-power mode value is in range */ -#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \ - (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X))) - -/* Defines a pin group cfg's low-power mode select */ -enum pgrp_lpmd { - PGRP_LPMD_X8 = 0, - PGRP_LPMD_X4, - PGRP_LPMD_X2, - PGRP_LPMD_X, - PGRP_LPMD_NONE = -1, -}; - -/* Defines whether a pin group cfg's schmidt is enabled or not */ -enum pgrp_schmt { - PGRP_SCHMT_DISABLE = 0, - PGRP_SCHMT_ENABLE = 1, -}; - -/* Defines whether a pin group cfg's high-speed mode is enabled or not */ -enum pgrp_hsm { - PGRP_HSM_DISABLE = 0, - PGRP_HSM_ENABLE = 1, -}; - -/* - * This defines the configuration for a pin group's pad control config - */ -struct padctrl_config { - enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */ - int slwf; /* falling edge slew */ - int slwr; /* rising edge slew */ - int drvup; /* pull-up drive strength */ - int drvdn; /* pull-down drive strength */ - enum pgrp_lpmd lpmd; /* low-power mode selection */ - enum pgrp_schmt schmt; /* schmidt enable */ - enum pgrp_hsm hsm; /* high-speed mode enable */ -}; - -/* t114 pin drive group and pin mux registers */ -#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2) -#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \ - PDRIVE_PINGROUP_COUNT) -struct pmux_tri_ctlr { - uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ - uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */ - uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ - uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */ - uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */ - uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */ - uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ - - uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */ - - uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */ - uint pmt_reserved5[PMUX_OFFSET]; - uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */ -}; - -/* - * This defines the configuration for a pin, including the function assigned, - * pull up/down settings and tristate settings. Having set up one of these - * you can call pinmux_config_pingroup() to configure a pin in one step. Also - * available is pinmux_config_table() to configure a list of pins. - */ -struct pingroup_config { - enum pmux_pingrp pingroup; /* pin group PINGRP_... */ - enum pmux_func func; /* function to assign FUNC_... */ - enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ - enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ - enum pmux_pin_io io; /* input or output PMUX_PIN_... */ - enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ - enum pmux_pin_od od; /* open-drain or push-pull driver */ - enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ - enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */ - /* VIL/VIH receivers */ + PMUX_FUNC_VI, + PMUX_FUNC_VI_ALT1, + PMUX_FUNC_VI_ALT3, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_RSVD4, + PMUX_FUNC_COUNT, }; -/* Set a pin group to tristate */ -void pinmux_tristate_enable(enum pmux_pingrp pin); - -/* Set a pin group to normal (non tristate) */ -void pinmux_tristate_disable(enum pmux_pingrp pin); - -/* Set the pull up/down feature for a pin group */ -void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); - -/* Set the mux function for a pin group */ -void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); - -/* Set the complete configuration for a pin group */ -void pinmux_config_pingroup(struct pingroup_config *config); - -/* Set a pin group to tristate or normal */ -void pinmux_set_tristate(enum pmux_pingrp pin, int enable); - -/* Set a pin group as input or output */ -void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); - -/** - * Configure a list of pin groups - * - * @param config List of config items - * @param len Number of config items in list - */ -void pinmux_config_table(struct pingroup_config *config, int len); - -/* Set a group of pins from a table */ -void pinmux_init(void); - -/** - * Set the GP pad configs - * - * @param config List of config items - * @param len Number of config items in list - */ -void padgrp_config_table(struct padctrl_config *config, int len); +#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC +#define TEGRA_PMX_HAS_RCV_SEL +#define TEGRA_PMX_HAS_DRVGRPS +#include <asm/arch-tegra/pinmux.h> -#endif /* _TEGRA114_PINMUX_H_ */ +#endif /* _TEGRA114_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/usb.h b/arch/arm/include/asm/arch-tegra114/usb.h deleted file mode 100644 index d46048c8ced..00000000000 --- a/arch/arm/include/asm/arch-tegra114/usb.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2013 NVIDIA Corporation - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA114_USB_H_ -#define _TEGRA114_USB_H_ - -/* USB Controller (USBx_CONTROLLER_) regs */ -struct usb_ctlr { - /* 0x000 */ - uint id; - uint reserved0; - uint host; - uint device; - - /* 0x010 */ - uint txbuf; - uint rxbuf; - uint reserved1[2]; - - /* 0x020 */ - uint reserved2[56]; - - /* 0x100 */ - u16 cap_length; - u16 hci_version; - uint hcs_params; - uint hcc_params; - uint reserved3[5]; - - /* 0x120 */ - uint dci_version; - uint dcc_params; - uint reserved4[2]; - - /* 0x130 */ - uint usb_cmd; - uint usb_sts; - uint usb_intr; - uint frindex; - - /* 0x140 */ - uint reserved5; - uint periodic_list_base; - uint async_list_addr; - uint reserved5_1; - - /* 0x150 */ - uint burst_size; - uint tx_fill_tuning; - uint reserved6; - uint icusb_ctrl; - - /* 0x160 */ - uint ulpi_viewport; - uint reserved7[3]; - - /* 0x170 */ - uint reserved; - uint port_sc1; - uint reserved8[6]; - - /* 0x190 */ - uint reserved9[8]; - - /* 0x1b0 */ - uint reserved10; - uint hostpc1_devlc; - uint reserved10_1[2]; - - /* 0x1c0 */ - uint reserved10_2[4]; - - /* 0x1d0 */ - uint reserved10_3[4]; - - /* 0x1e0 */ - uint reserved10_4[4]; - - /* 0x1f0 */ - uint reserved10_5; - uint otgsc; - uint usb_mode; - uint reserved10_6; - - /* 0x200 */ - uint endpt_nak; - uint endpt_nak_enable; - uint endpt_setup_stat; - uint reserved11_1[0x7D]; - - /* 0x400 */ - uint susp_ctrl; - uint phy_vbus_sensors; - uint phy_vbus_wakeup_id; - uint phy_alt_vbus_sys; - - /* 0x410 */ - uint usb1_legacy_ctrl; - uint reserved12[3]; - - /* 0x420 */ - uint reserved13[56]; - - /* 0x500 */ - uint reserved14[64 * 3]; - - /* 0x800 */ - uint utmip_pll_cfg0; - uint utmip_pll_cfg1; - uint utmip_xcvr_cfg0; - uint utmip_bias_cfg0; - - /* 0x810 */ - uint utmip_hsrx_cfg0; - uint utmip_hsrx_cfg1; - uint utmip_fslsrx_cfg0; - uint utmip_fslsrx_cfg1; - - /* 0x820 */ - uint utmip_tx_cfg0; - uint utmip_misc_cfg0; - uint utmip_misc_cfg1; - uint utmip_debounce_cfg0; - - /* 0x830 */ - uint utmip_bat_chrg_cfg0; - uint utmip_spare_cfg0; - uint utmip_xcvr_cfg1; - uint utmip_bias_cfg1; -}; - -/* USB2D_HOSTPC1_DEVLC_0 */ -#define PTS_SHIFT 29 -#define PTS_MASK (0x7U << PTS_SHIFT) - -#define STS (1 << 28) -#endif /* _TEGRA114_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h index 9662e2b8aa5..c49801c21d0 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -1,620 +1,342 @@ /* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> + * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA124_PINMUX_H_ #define _TEGRA124_PINMUX_H_ -/* - * Pin groups which we adjust. There are three basic attributes of each pin - * group which use this enum: - * - * - function - * - pullup / pulldown - * - tristate or normal - */ enum pmux_pingrp { - PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */ - PINGRP_ULPI_DATA1, - PINGRP_ULPI_DATA2, - PINGRP_ULPI_DATA3, - PINGRP_ULPI_DATA4, - PINGRP_ULPI_DATA5, - PINGRP_ULPI_DATA6, - PINGRP_ULPI_DATA7, - PINGRP_ULPI_CLK, - PINGRP_ULPI_DIR, - PINGRP_ULPI_NXT, - PINGRP_ULPI_STP, - PINGRP_DAP3_FS, - PINGRP_DAP3_DIN, - PINGRP_DAP3_DOUT, - PINGRP_DAP3_SCLK, - PINGRP_GPIO_PV0, - PINGRP_GPIO_PV1, - PINGRP_SDMMC1_CLK, - PINGRP_SDMMC1_CMD, - PINGRP_SDMMC1_DAT3, - PINGRP_SDMMC1_DAT2, - PINGRP_SDMMC1_DAT1, - PINGRP_SDMMC1_DAT0, - PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3, - PINGRP_CLK2_REQ, - PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41, - PINGRP_DDC_SCL, - PINGRP_DDC_SDA, - PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19, - PINGRP_UART2_TXD, - PINGRP_UART2_RTS_N, - PINGRP_UART2_CTS_N, - PINGRP_UART3_TXD, - PINGRP_UART3_RXD, - PINGRP_UART3_CTS_N, - PINGRP_UART3_RTS_N, - PINGRP_GPIO_PU0, - PINGRP_GPIO_PU1, - PINGRP_GPIO_PU2, - PINGRP_GPIO_PU3, - PINGRP_GPIO_PU4, - PINGRP_GPIO_PU5, - PINGRP_GPIO_PU6, - PINGRP_GEN1_I2C_SDA, - PINGRP_GEN1_I2C_SCL, - PINGRP_DAP4_FS, - PINGRP_DAP4_DIN, - PINGRP_DAP4_DOUT, - PINGRP_DAP4_SCLK, - PINGRP_CLK3_OUT, - PINGRP_CLK3_REQ, - /* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */ - PINGRP_GPIO_PC7, /* offset 0x31c0 */ - PINGRP_GPIO_PI5, - PINGRP_GPIO_PI7, - PINGRP_GPIO_PK0, - PINGRP_GPIO_PK1, - PINGRP_GPIO_PJ0, - PINGRP_GPIO_PJ2, - PINGRP_GPIO_PK3, - PINGRP_GPIO_PK4, - PINGRP_GPIO_PK2, - PINGRP_GPIO_PI3, - PINGRP_GPIO_PI6, - PINGRP_GPIO_PG0, - PINGRP_GPIO_PG1, - PINGRP_GPIO_PG2, - PINGRP_GPIO_PG3, - PINGRP_GPIO_PG4, - PINGRP_GPIO_PG5, - PINGRP_GPIO_PG6, - PINGRP_GPIO_PG7, - PINGRP_GPIO_PH0, - PINGRP_GPIO_PH1, - PINGRP_GPIO_PH2, - PINGRP_GPIO_PH3, - PINGRP_GPIO_PH4, - PINGRP_GPIO_PH5, - PINGRP_GPIO_PH6, - PINGRP_GPIO_PH7, - PINGRP_GPIO_PJ7, - PINGRP_GPIO_PB0, - PINGRP_GPIO_PB1, - PINGRP_GPIO_PK7, - PINGRP_GPIO_PI0, - PINGRP_GPIO_PI1, - PINGRP_GPIO_PI2, - PINGRP_GPIO_PI4, /* offset 0x324c */ - PINGRP_GEN2_I2C_SCL, - PINGRP_GEN2_I2C_SDA, - PINGRP_SDMMC4_CLK, - PINGRP_SDMMC4_CMD, - PINGRP_SDMMC4_DAT0, - PINGRP_SDMMC4_DAT1, - PINGRP_SDMMC4_DAT2, - PINGRP_SDMMC4_DAT3, - PINGRP_SDMMC4_DAT4, - PINGRP_SDMMC4_DAT5, - PINGRP_SDMMC4_DAT6, - PINGRP_SDMMC4_DAT7, - PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2, - PINGRP_GPIO_PCC1, - PINGRP_GPIO_PBB0, - PINGRP_CAM_I2C_SCL, - PINGRP_CAM_I2C_SDA, - PINGRP_GPIO_PBB3, - PINGRP_GPIO_PBB4, - PINGRP_GPIO_PBB5, - PINGRP_GPIO_PBB6, - PINGRP_GPIO_PBB7, - PINGRP_GPIO_PCC2, - PINGRP_JTAG_RTCK, - PINGRP_PWR_I2C_SCL, - PINGRP_PWR_I2C_SDA, - PINGRP_KB_ROW0, - PINGRP_KB_ROW1, - PINGRP_KB_ROW2, - PINGRP_KB_ROW3, - PINGRP_KB_ROW4, - PINGRP_KB_ROW5, - PINGRP_KB_ROW6, - PINGRP_KB_ROW7, - PINGRP_KB_ROW8, - PINGRP_KB_ROW9, - PINGRP_KB_ROW10, - PINGRP_KB_ROW11, - PINGRP_KB_ROW12, - PINGRP_KB_ROW13, - PINGRP_KB_ROW14, - PINGRP_KB_ROW15, - PINGRP_KB_COL0, /* offset 0x32fc */ - PINGRP_KB_COL1, - PINGRP_KB_COL2, - PINGRP_KB_COL3, - PINGRP_KB_COL4, - PINGRP_KB_COL5, - PINGRP_KB_COL6, - PINGRP_KB_COL7, - PINGRP_CLK_32K_OUT, - PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2, /* offset 0x3324 */ - PINGRP_CPU_PWR_REQ, - PINGRP_PWR_INT_N, - PINGRP_CLK_32K_IN, - PINGRP_OWR, - PINGRP_DAP1_FS, - PINGRP_DAP1_DIN, - PINGRP_DAP1_DOUT, - PINGRP_DAP1_SCLK, - PINGRP_CLK1_REQ, - PINGRP_CLK1_OUT, - PINGRP_SPDIF_IN, - PINGRP_SPDIF_OUT, - PINGRP_DAP2_FS, - PINGRP_DAP2_DIN, - PINGRP_DAP2_DOUT, - PINGRP_DAP2_SCLK, - PINGRP_DVFS_PWM, - PINGRP_GPIO_X1_AUD, - PINGRP_GPIO_X3_AUD, - PINGRP_DVFS_CLK, - PINGRP_GPIO_X4_AUD, - PINGRP_GPIO_X5_AUD, - PINGRP_GPIO_X6_AUD, - PINGRP_GPIO_X7_AUD, - PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3, - PINGRP_SDMMC3_CMD, - PINGRP_SDMMC3_DAT0, - PINGRP_SDMMC3_DAT1, - PINGRP_SDMMC3_DAT2, - PINGRP_SDMMC3_DAT3, - PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */ - PINGRP_PEX_L0_CLKREQ, - PINGRP_PEX_WAKE, - PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2, - PINGRP_PEX_L1_CLKREQ, - PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */ - PINGRP_SDMMC1_WP_N, - PINGRP_SDMMC3_CD_N, - PINGRP_GPIO_W2_AUD, - PINGRP_GPIO_W3_AUD, - PINGRP_USB_VBUS_EN0, - PINGRP_USB_VBUS_EN1, - PINGRP_SDMMC3_CLK_LB_IN, - PINGRP_SDMMC3_CLK_LB_OUT, - PINGRP_GMI_CLK_LB, - PINGRP_RESET_OUT_N, - PINGRP_KB_ROW16, /* offset 0x340c */ - PINGRP_KB_ROW17, - PINGRP_USB_VBUS_EN2, - PINGRP_GPIO_PFF2, - PINGRP_DP_HPD, /* last reg offset = 0x3430 */ - PINGRP_COUNT, + PMUX_PINGRP_ULPI_DATA0_PO1, + PMUX_PINGRP_ULPI_DATA1_PO2, + PMUX_PINGRP_ULPI_DATA2_PO3, + PMUX_PINGRP_ULPI_DATA3_PO4, + PMUX_PINGRP_ULPI_DATA4_PO5, + PMUX_PINGRP_ULPI_DATA5_PO6, + PMUX_PINGRP_ULPI_DATA6_PO7, + PMUX_PINGRP_ULPI_DATA7_PO0, + PMUX_PINGRP_ULPI_CLK_PY0, + PMUX_PINGRP_ULPI_DIR_PY1, + PMUX_PINGRP_ULPI_NXT_PY2, + PMUX_PINGRP_ULPI_STP_PY3, + PMUX_PINGRP_DAP3_FS_PP0, + PMUX_PINGRP_DAP3_DIN_PP1, + PMUX_PINGRP_DAP3_DOUT_PP2, + PMUX_PINGRP_DAP3_SCLK_PP3, + PMUX_PINGRP_PV0, + PMUX_PINGRP_PV1, + PMUX_PINGRP_SDMMC1_CLK_PZ0, + PMUX_PINGRP_SDMMC1_CMD_PZ1, + PMUX_PINGRP_SDMMC1_DAT3_PY4, + PMUX_PINGRP_SDMMC1_DAT2_PY5, + PMUX_PINGRP_SDMMC1_DAT1_PY6, + PMUX_PINGRP_SDMMC1_DAT0_PY7, + PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4), + PMUX_PINGRP_CLK2_REQ_PCC5, + PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4), + PMUX_PINGRP_DDC_SCL_PV4, + PMUX_PINGRP_DDC_SDA_PV5, + PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4), + PMUX_PINGRP_UART2_TXD_PC2, + PMUX_PINGRP_UART2_RTS_N_PJ6, + PMUX_PINGRP_UART2_CTS_N_PJ5, + PMUX_PINGRP_UART3_TXD_PW6, + PMUX_PINGRP_UART3_RXD_PW7, + PMUX_PINGRP_UART3_CTS_N_PA1, + PMUX_PINGRP_UART3_RTS_N_PC0, + PMUX_PINGRP_PU0, + PMUX_PINGRP_PU1, + PMUX_PINGRP_PU2, + PMUX_PINGRP_PU3, + PMUX_PINGRP_PU4, + PMUX_PINGRP_PU5, + PMUX_PINGRP_PU6, + PMUX_PINGRP_GEN1_I2C_SDA_PC5, + PMUX_PINGRP_GEN1_I2C_SCL_PC4, + PMUX_PINGRP_DAP4_FS_PP4, + PMUX_PINGRP_DAP4_DIN_PP5, + PMUX_PINGRP_DAP4_DOUT_PP6, + PMUX_PINGRP_DAP4_SCLK_PP7, + PMUX_PINGRP_CLK3_OUT_PEE0, + PMUX_PINGRP_CLK3_REQ_PEE1, + PMUX_PINGRP_PC7, + PMUX_PINGRP_PI5, + PMUX_PINGRP_PI7, + PMUX_PINGRP_PK0, + PMUX_PINGRP_PK1, + PMUX_PINGRP_PJ0, + PMUX_PINGRP_PJ2, + PMUX_PINGRP_PK3, + PMUX_PINGRP_PK4, + PMUX_PINGRP_PK2, + PMUX_PINGRP_PI3, + PMUX_PINGRP_PI6, + PMUX_PINGRP_PG0, + PMUX_PINGRP_PG1, + PMUX_PINGRP_PG2, + PMUX_PINGRP_PG3, + PMUX_PINGRP_PG4, + PMUX_PINGRP_PG5, + PMUX_PINGRP_PG6, + PMUX_PINGRP_PG7, + PMUX_PINGRP_PH0, + PMUX_PINGRP_PH1, + PMUX_PINGRP_PH2, + PMUX_PINGRP_PH3, + PMUX_PINGRP_PH4, + PMUX_PINGRP_PH5, + PMUX_PINGRP_PH6, + PMUX_PINGRP_PH7, + PMUX_PINGRP_PJ7, + PMUX_PINGRP_PB0, + PMUX_PINGRP_PB1, + PMUX_PINGRP_PK7, + PMUX_PINGRP_PI0, + PMUX_PINGRP_PI1, + PMUX_PINGRP_PI2, + PMUX_PINGRP_PI4, + PMUX_PINGRP_GEN2_I2C_SCL_PT5, + PMUX_PINGRP_GEN2_I2C_SDA_PT6, + PMUX_PINGRP_SDMMC4_CLK_PCC4, + PMUX_PINGRP_SDMMC4_CMD_PT7, + PMUX_PINGRP_SDMMC4_DAT0_PAA0, + PMUX_PINGRP_SDMMC4_DAT1_PAA1, + PMUX_PINGRP_SDMMC4_DAT2_PAA2, + PMUX_PINGRP_SDMMC4_DAT3_PAA3, + PMUX_PINGRP_SDMMC4_DAT4_PAA4, + PMUX_PINGRP_SDMMC4_DAT5_PAA5, + PMUX_PINGRP_SDMMC4_DAT6_PAA6, + PMUX_PINGRP_SDMMC4_DAT7_PAA7, + PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4), + PMUX_PINGRP_PCC1, + PMUX_PINGRP_PBB0, + PMUX_PINGRP_CAM_I2C_SCL_PBB1, + PMUX_PINGRP_CAM_I2C_SDA_PBB2, + PMUX_PINGRP_PBB3, + PMUX_PINGRP_PBB4, + PMUX_PINGRP_PBB5, + PMUX_PINGRP_PBB6, + PMUX_PINGRP_PBB7, + PMUX_PINGRP_PCC2, + PMUX_PINGRP_JTAG_RTCK, + PMUX_PINGRP_PWR_I2C_SCL_PZ6, + PMUX_PINGRP_PWR_I2C_SDA_PZ7, + PMUX_PINGRP_KB_ROW0_PR0, + PMUX_PINGRP_KB_ROW1_PR1, + PMUX_PINGRP_KB_ROW2_PR2, + PMUX_PINGRP_KB_ROW3_PR3, + PMUX_PINGRP_KB_ROW4_PR4, + PMUX_PINGRP_KB_ROW5_PR5, + PMUX_PINGRP_KB_ROW6_PR6, + PMUX_PINGRP_KB_ROW7_PR7, + PMUX_PINGRP_KB_ROW8_PS0, + PMUX_PINGRP_KB_ROW9_PS1, + PMUX_PINGRP_KB_ROW10_PS2, + PMUX_PINGRP_KB_ROW11_PS3, + PMUX_PINGRP_KB_ROW12_PS4, + PMUX_PINGRP_KB_ROW13_PS5, + PMUX_PINGRP_KB_ROW14_PS6, + PMUX_PINGRP_KB_ROW15_PS7, + PMUX_PINGRP_KB_COL0_PQ0, + PMUX_PINGRP_KB_COL1_PQ1, + PMUX_PINGRP_KB_COL2_PQ2, + PMUX_PINGRP_KB_COL3_PQ3, + PMUX_PINGRP_KB_COL4_PQ4, + PMUX_PINGRP_KB_COL5_PQ5, + PMUX_PINGRP_KB_COL6_PQ6, + PMUX_PINGRP_KB_COL7_PQ7, + PMUX_PINGRP_CLK_32K_OUT_PA0, + PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4), + PMUX_PINGRP_CPU_PWR_REQ, + PMUX_PINGRP_PWR_INT_N, + PMUX_PINGRP_CLK_32K_IN, + PMUX_PINGRP_OWR, + PMUX_PINGRP_DAP1_FS_PN0, + PMUX_PINGRP_DAP1_DIN_PN1, + PMUX_PINGRP_DAP1_DOUT_PN2, + PMUX_PINGRP_DAP1_SCLK_PN3, + PMUX_PINGRP_DAP_MCLK1_REQ_PEE2, + PMUX_PINGRP_DAP_MCLK1_PW4, + PMUX_PINGRP_SPDIF_IN_PK6, + PMUX_PINGRP_SPDIF_OUT_PK5, + PMUX_PINGRP_DAP2_FS_PA2, + PMUX_PINGRP_DAP2_DIN_PA4, + PMUX_PINGRP_DAP2_DOUT_PA5, + PMUX_PINGRP_DAP2_SCLK_PA3, + PMUX_PINGRP_DVFS_PWM_PX0, + PMUX_PINGRP_GPIO_X1_AUD_PX1, + PMUX_PINGRP_GPIO_X3_AUD_PX3, + PMUX_PINGRP_DVFS_CLK_PX2, + PMUX_PINGRP_GPIO_X4_AUD_PX4, + PMUX_PINGRP_GPIO_X5_AUD_PX5, + PMUX_PINGRP_GPIO_X6_AUD_PX6, + PMUX_PINGRP_GPIO_X7_AUD_PX7, + PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4), + PMUX_PINGRP_SDMMC3_CMD_PA7, + PMUX_PINGRP_SDMMC3_DAT0_PB7, + PMUX_PINGRP_SDMMC3_DAT1_PB6, + PMUX_PINGRP_SDMMC3_DAT2_PB5, + PMUX_PINGRP_SDMMC3_DAT3_PB4, + PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4), + PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2, + PMUX_PINGRP_PEX_WAKE_N_PDD3, + PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4), + PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6, + PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4), + PMUX_PINGRP_SDMMC1_WP_N_PV3, + PMUX_PINGRP_SDMMC3_CD_N_PV2, + PMUX_PINGRP_GPIO_W2_AUD_PW2, + PMUX_PINGRP_GPIO_W3_AUD_PW3, + PMUX_PINGRP_USB_VBUS_EN0_PN4, + PMUX_PINGRP_USB_VBUS_EN1_PN5, + PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5, + PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4, + PMUX_PINGRP_GMI_CLK_LB, + PMUX_PINGRP_RESET_OUT_N, + PMUX_PINGRP_KB_ROW16_PT0, + PMUX_PINGRP_KB_ROW17_PT1, + PMUX_PINGRP_USB_VBUS_EN2_PFF1, + PMUX_PINGRP_PFF2, + PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4), + PMUX_PINGRP_COUNT, }; -enum pdrive_pingrp { - PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */ - PDRIVE_PINGROUP_AO2, - PDRIVE_PINGROUP_AT1, - PDRIVE_PINGROUP_AT2, - PDRIVE_PINGROUP_AT3, - PDRIVE_PINGROUP_AT4, - PDRIVE_PINGROUP_AT5, - PDRIVE_PINGROUP_CDEV1, - PDRIVE_PINGROUP_CDEV2, - PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */ - PDRIVE_PINGROUP_DAP2, - PDRIVE_PINGROUP_DAP3, - PDRIVE_PINGROUP_DAP4, - PDRIVE_PINGROUP_DBG, - PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */ - PDRIVE_PINGROUP_SPI, - PDRIVE_PINGROUP_UAA, - PDRIVE_PINGROUP_UAB, - PDRIVE_PINGROUP_UART2, - PDRIVE_PINGROUP_UART3, - PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */ - PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */ - PDRIVE_PINGROUP_GMA, - PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */ - PDRIVE_PINGROUP_GMF, - PDRIVE_PINGROUP_GMG, - PDRIVE_PINGROUP_GMH, - PDRIVE_PINGROUP_OWR, - PDRIVE_PINGROUP_UAD, - PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */ - PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */ - PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */ - PDRIVE_PINGROUP_DAP5, - PDRIVE_PINGROUP_VBUS, - PDRIVE_PINGROUP_AO3, - PDRIVE_PINGROUP_HVC, - PDRIVE_PINGROUP_SDIO4, - PDRIVE_PINGROUP_AO0, - PDRIVE_PINGROUP_COUNT, +enum pmux_drvgrp { + PMUX_DRVGRP_AO1, + PMUX_DRVGRP_AO2, + PMUX_DRVGRP_AT1, + PMUX_DRVGRP_AT2, + PMUX_DRVGRP_AT3, + PMUX_DRVGRP_AT4, + PMUX_DRVGRP_AT5, + PMUX_DRVGRP_CDEV1, + PMUX_DRVGRP_CDEV2, + PMUX_DRVGRP_DAP1 = (0x28 / 4), + PMUX_DRVGRP_DAP2, + PMUX_DRVGRP_DAP3, + PMUX_DRVGRP_DAP4, + PMUX_DRVGRP_DBG, + PMUX_DRVGRP_SDIO3 = (0x48 / 4), + PMUX_DRVGRP_SPI, + PMUX_DRVGRP_UAA, + PMUX_DRVGRP_UAB, + PMUX_DRVGRP_UART2, + PMUX_DRVGRP_UART3, + PMUX_DRVGRP_SDIO1 = (0x84 / 4), + PMUX_DRVGRP_DDC = (0x94 / 4), + PMUX_DRVGRP_GMA, + PMUX_DRVGRP_GME = (0xa8 / 4), + PMUX_DRVGRP_GMF, + PMUX_DRVGRP_GMG, + PMUX_DRVGRP_GMH, + PMUX_DRVGRP_OWR, + PMUX_DRVGRP_UDA, + PMUX_DRVGRP_GPV, + PMUX_DRVGRP_DEV3, + PMUX_DRVGRP_CEC = (0xd0 / 4), + PMUX_DRVGRP_AT6 = (0x12c / 4), + PMUX_DRVGRP_DAP5, + PMUX_DRVGRP_USB_VBUS_EN, + PMUX_DRVGRP_AO3 = (0x140 / 4), + PMUX_DRVGRP_AO0 = (0x148 / 4), + PMUX_DRVGRP_HV0, + PMUX_DRVGRP_SDIO4 = (0x15c / 4), + PMUX_DRVGRP_AO4, + PMUX_DRVGRP_COUNT, }; -/* - * Functions which can be assigned to each of the pin groups. The values here - * bear no relation to the values programmed into pinmux registers and are - * purely a convenience. The translation is done through a table search. - */ enum pmux_func { - PMUX_FUNC_AHB_CLK, - PMUX_FUNC_APB_CLK, - PMUX_FUNC_AUDIO_SYNC, - PMUX_FUNC_CRT, - PMUX_FUNC_DAP1, - PMUX_FUNC_DAP2, - PMUX_FUNC_DAP3, - PMUX_FUNC_DAP4, - PMUX_FUNC_DAP5, - PMUX_FUNC_DISPA, - PMUX_FUNC_DISPB, - PMUX_FUNC_EMC_TEST0_DLL, - PMUX_FUNC_EMC_TEST1_DLL, - PMUX_FUNC_GMI, - PMUX_FUNC_GMI_INT, - PMUX_FUNC_HDMI, - PMUX_FUNC_I2C1, - PMUX_FUNC_I2C2, - PMUX_FUNC_I2C3, - PMUX_FUNC_IDE, - PMUX_FUNC_KBC, - PMUX_FUNC_MIO, - PMUX_FUNC_MIPI_HS, - PMUX_FUNC_NAND, - PMUX_FUNC_OSC, - PMUX_FUNC_OWR, - PMUX_FUNC_PCIE, - PMUX_FUNC_PLLA_OUT, - PMUX_FUNC_PLLC_OUT1, - PMUX_FUNC_PLLM_OUT1, - PMUX_FUNC_PLLP_OUT2, - PMUX_FUNC_PLLP_OUT3, - PMUX_FUNC_PLLP_OUT4, - PMUX_FUNC_PWM, - PMUX_FUNC_PWR_INTR, - PMUX_FUNC_PWR_ON, - PMUX_FUNC_RTCK, - PMUX_FUNC_SDMMC1, - PMUX_FUNC_SDMMC2, - PMUX_FUNC_SDMMC3, - PMUX_FUNC_SDMMC4, - PMUX_FUNC_SFLASH, - PMUX_FUNC_SPDIF, - PMUX_FUNC_SPI1, - PMUX_FUNC_SPI2, - PMUX_FUNC_SPI2_ALT, - PMUX_FUNC_SPI3, - PMUX_FUNC_SPI4, - PMUX_FUNC_TRACE, - PMUX_FUNC_TWC, - PMUX_FUNC_UARTA, - PMUX_FUNC_UARTB, - PMUX_FUNC_UARTC, - PMUX_FUNC_UARTD, - PMUX_FUNC_UARTE, - PMUX_FUNC_ULPI, - PMUX_FUNC_VI, - PMUX_FUNC_VI_SENSOR_CLK, - PMUX_FUNC_XIO, - /* End of Tegra2 MUX selectors */ PMUX_FUNC_BLINK, + PMUX_FUNC_CCLA, PMUX_FUNC_CEC, + PMUX_FUNC_CLDVFS, + PMUX_FUNC_CLK, PMUX_FUNC_CLK12, + PMUX_FUNC_CPU, PMUX_FUNC_DAP, - PMUX_FUNC_DAPSDMMC2, - PMUX_FUNC_DDR, + PMUX_FUNC_DAP1, + PMUX_FUNC_DAP2, PMUX_FUNC_DEV3, + PMUX_FUNC_DISPLAYA, + PMUX_FUNC_DISPLAYA_ALT, + PMUX_FUNC_DISPLAYB, + PMUX_FUNC_DP, PMUX_FUNC_DTV, - PMUX_FUNC_VI_ALT1, - PMUX_FUNC_VI_ALT2, - PMUX_FUNC_VI_ALT3, - PMUX_FUNC_EMC_DLL, PMUX_FUNC_EXTPERIPH1, PMUX_FUNC_EXTPERIPH2, PMUX_FUNC_EXTPERIPH3, + PMUX_FUNC_GMI, PMUX_FUNC_GMI_ALT, PMUX_FUNC_HDA, PMUX_FUNC_HSI, + PMUX_FUNC_I2C1, + PMUX_FUNC_I2C2, + PMUX_FUNC_I2C3, PMUX_FUNC_I2C4, - PMUX_FUNC_I2C5, PMUX_FUNC_I2CPWR, PMUX_FUNC_I2S0, PMUX_FUNC_I2S1, PMUX_FUNC_I2S2, PMUX_FUNC_I2S3, PMUX_FUNC_I2S4, - PMUX_FUNC_NAND_ALT, - PMUX_FUNC_POPSDIO4, - PMUX_FUNC_POPSDMMC4, + PMUX_FUNC_IRDA, + PMUX_FUNC_KBC, + PMUX_FUNC_OWR, + PMUX_FUNC_PE, + PMUX_FUNC_PE0, + PMUX_FUNC_PE1, + PMUX_FUNC_PMI, PMUX_FUNC_PWM0, PMUX_FUNC_PWM1, PMUX_FUNC_PWM2, PMUX_FUNC_PWM3, + PMUX_FUNC_PWRON, + PMUX_FUNC_RESET_OUT_N, + PMUX_FUNC_RTCK, PMUX_FUNC_SATA, + PMUX_FUNC_SDMMC1, + PMUX_FUNC_SDMMC2, + PMUX_FUNC_SDMMC3, + PMUX_FUNC_SDMMC4, + PMUX_FUNC_SOC, + PMUX_FUNC_SPDIF, + PMUX_FUNC_SPI1, + PMUX_FUNC_SPI2, + PMUX_FUNC_SPI3, + PMUX_FUNC_SPI4, PMUX_FUNC_SPI5, PMUX_FUNC_SPI6, - PMUX_FUNC_SYSCLK, + PMUX_FUNC_SYS, + PMUX_FUNC_TMDS, + PMUX_FUNC_TRACE, + PMUX_FUNC_UARTA, + PMUX_FUNC_UARTB, + PMUX_FUNC_UARTC, + PMUX_FUNC_UARTD, + PMUX_FUNC_ULPI, + PMUX_FUNC_USB, PMUX_FUNC_VGP1, PMUX_FUNC_VGP2, PMUX_FUNC_VGP3, PMUX_FUNC_VGP4, PMUX_FUNC_VGP5, PMUX_FUNC_VGP6, - /* End of Tegra3 MUX selectors */ - PMUX_FUNC_USB, - PMUX_FUNC_SOC, - PMUX_FUNC_CPU, - PMUX_FUNC_CLK, - PMUX_FUNC_PWRON, - PMUX_FUNC_PMI, - PMUX_FUNC_CLDVFS, - PMUX_FUNC_RESET_OUT_N, - /* End of Tegra114 MUX selectors */ - - PMUX_FUNC_SAFE, - PMUX_FUNC_MAX, - - PMUX_FUNC_INVALID = 0x4000, - PMUX_FUNC_RSVD1 = 0x8000, - PMUX_FUNC_RSVD2 = 0x8001, - PMUX_FUNC_RSVD3 = 0x8002, - PMUX_FUNC_RSVD4 = 0x8003, -}; - -/* return 1 if a pmux_func is in range */ -#define pmux_func_isvalid(func) \ - ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) || \ - (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4))) - -/* return 1 if a pingrp is in range */ -#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT)) - -/* The pullup/pulldown state of a pin group */ -enum pmux_pull { - PMUX_PULL_NORMAL = 0, - PMUX_PULL_DOWN, - PMUX_PULL_UP, -}; -/* return 1 if a pin_pupd_is in range */ -#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \ - ((pupd) <= PMUX_PULL_UP)) - -/* Defines whether a pin group is tristated or in normal operation */ -enum pmux_tristate { - PMUX_TRI_NORMAL = 0, - PMUX_TRI_TRISTATE = 1, -}; -/* return 1 if a pin_tristate_is in range */ -#define pmux_pin_tristate_isvalid(tristate) \ - (((tristate) >= PMUX_TRI_NORMAL) && \ - ((tristate) <= PMUX_TRI_TRISTATE)) - -enum pmux_pin_io { - PMUX_PIN_OUTPUT = 0, - PMUX_PIN_INPUT = 1, - PMUX_PIN_NONE, -}; -/* return 1 if a pin_io_is in range */ -#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \ - ((io) <= PMUX_PIN_INPUT)) - -enum pmux_pin_lock { - PMUX_PIN_LOCK_DEFAULT = 0, - PMUX_PIN_LOCK_DISABLE, - PMUX_PIN_LOCK_ENABLE, -}; -/* return 1 if a pin_lock is in range */ -#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \ - ((lock) <= PMUX_PIN_LOCK_ENABLE)) - -enum pmux_pin_od { - PMUX_PIN_OD_DEFAULT = 0, - PMUX_PIN_OD_DISABLE, - PMUX_PIN_OD_ENABLE, -}; -/* return 1 if a pin_od is in range */ -#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \ - ((od) <= PMUX_PIN_OD_ENABLE)) - -enum pmux_pin_ioreset { - PMUX_PIN_IO_RESET_DEFAULT = 0, - PMUX_PIN_IO_RESET_DISABLE, - PMUX_PIN_IO_RESET_ENABLE, -}; -/* return 1 if a pin_ioreset_is in range */ -#define pmux_pin_ioreset_isvalid(ioreset) \ - (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \ - ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE)) - -enum pmux_pin_rcv_sel { - PMUX_PIN_RCV_SEL_DEFAULT = 0, - PMUX_PIN_RCV_SEL_NORMAL, - PMUX_PIN_RCV_SEL_HIGH, -}; -/* return 1 if a pin_rcv_sel_is in range */ -#define pmux_pin_rcv_sel_isvalid(rcv_sel) \ - (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \ - ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH)) - -/* Available power domains used by pin groups */ -enum pmux_vddio { - PMUX_VDDIO_BB = 0, - PMUX_VDDIO_LCD, - PMUX_VDDIO_VI, - PMUX_VDDIO_UART, - PMUX_VDDIO_DDR, - PMUX_VDDIO_NAND, - PMUX_VDDIO_SYS, - PMUX_VDDIO_AUDIO, - PMUX_VDDIO_SD, - PMUX_VDDIO_CAM, - PMUX_VDDIO_GMI, - PMUX_VDDIO_PEXCTL, - PMUX_VDDIO_SDMMC1, - PMUX_VDDIO_SDMMC3, - PMUX_VDDIO_SDMMC4, - - PMUX_VDDIO_NONE -}; - -#define PGRP_SLWF_NONE -1 -#define PGRP_SLWF_MAX 3 -#define PGRP_SLWR_NONE PGRP_SLWF_NONE -#define PGRP_SLWR_MAX PGRP_SLWF_MAX - -#define PGRP_DRVUP_NONE -1 -#define PGRP_DRVUP_MAX 127 -#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE -#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX - -#define PGRP_SCHMT_NONE -1 -#define PGRP_HSM_NONE PGRP_SCHMT_NONE - -/* return 1 if a padgrp is in range */ -#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT)) - -/* return 1 if a slew-rate rising/falling edge value is in range */ -#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \ - (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX))) - -/* return 1 if a driver output pull-up/down strength code value is in range */ -#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \ - (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX))) - -/* return 1 if a low-power mode value is in range */ -#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \ - (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X))) - -/* Defines a pin group cfg's low-power mode select */ -enum pgrp_lpmd { - PGRP_LPMD_X8 = 0, - PGRP_LPMD_X4, - PGRP_LPMD_X2, - PGRP_LPMD_X, - PGRP_LPMD_NONE = -1, -}; - -/* Defines whether a pin group cfg's schmidt is enabled or not */ -enum pgrp_schmt { - PGRP_SCHMT_DISABLE = 0, - PGRP_SCHMT_ENABLE = 1, -}; - -/* Defines whether a pin group cfg's high-speed mode is enabled or not */ -enum pgrp_hsm { - PGRP_HSM_DISABLE = 0, - PGRP_HSM_ENABLE = 1, -}; - -/* - * This defines the configuration for a pin group's pad control config - */ -struct padctrl_config { - enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */ - int slwf; /* falling edge slew */ - int slwr; /* rising edge slew */ - int drvup; /* pull-up drive strength */ - int drvdn; /* pull-down drive strength */ - enum pgrp_lpmd lpmd; /* low-power mode selection */ - enum pgrp_schmt schmt; /* schmidt enable */ - enum pgrp_hsm hsm; /* high-speed mode enable */ -}; - -/* Tegra124 pin drive group and pin mux registers */ -#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2) -#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \ - PDRIVE_PINGROUP_COUNT) -struct pmux_tri_ctlr { - uint pmt_reserved0[9]; /* ABP_MISC_PP_ offsets 00-20 */ - uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ - - uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */ - - uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */ - uint pmt_reserved5[PMUX_OFFSET]; - uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */ -}; - -/* - * This defines the configuration for a pin, including the function assigned, - * pull up/down settings and tristate settings. Having set up one of these - * you can call pinmux_config_pingroup() to configure a pin in one step. Also - * available is pinmux_config_table() to configure a list of pins. - */ -struct pingroup_config { - enum pmux_pingrp pingroup; /* pin group PINGRP_... */ - enum pmux_func func; /* function to assign FUNC_... */ - enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ - enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ - enum pmux_pin_io io; /* input or output PMUX_PIN_... */ - enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ - enum pmux_pin_od od; /* open-drain or push-pull driver */ - enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ - enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */ - /* VIL/VIH receivers */ + PMUX_FUNC_VI, + PMUX_FUNC_VI_ALT1, + PMUX_FUNC_VI_ALT3, + PMUX_FUNC_VIMCLK2, + PMUX_FUNC_VIMCLK2_ALT, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_RSVD4, + PMUX_FUNC_COUNT, }; -/* Set a pin group to tristate */ -void pinmux_tristate_enable(enum pmux_pingrp pin); - -/* Set a pin group to normal (non tristate) */ -void pinmux_tristate_disable(enum pmux_pingrp pin); - -/* Set the pull up/down feature for a pin group */ -void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); - -/* Set the mux function for a pin group */ -void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); - -/* Set the complete configuration for a pin group */ -void pinmux_config_pingroup(struct pingroup_config *config); - -/* Set a pin group to tristate or normal */ -void pinmux_set_tristate(enum pmux_pingrp pin, int enable); - -/* Set a pin group as input or output */ -void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); - -/** - * Configure a list of pin groups - * - * @param config List of config items - * @param len Number of config items in list - */ -void pinmux_config_table(struct pingroup_config *config, int len); - -/* Set a group of pins from a table */ -void pinmux_init(void); - -/** - * Set the GP pad configs - * - * @param config List of config items - * @param len Number of config items in list - */ -void padgrp_config_table(struct padctrl_config *config, int len); +#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC +#define TEGRA_PMX_HAS_RCV_SEL +#define TEGRA_PMX_HAS_DRVGRPS +#include <asm/arch-tegra/pinmux.h> -#endif /* _TEGRA124_PINMUX_H_ */ +#endif /* _TEGRA124_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/usb.h b/arch/arm/include/asm/arch-tegra124/usb.h deleted file mode 100644 index 7a2d7859d92..00000000000 --- a/arch/arm/include/asm/arch-tegra124/usb.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_USB_H_ -#define _TEGRA124_USB_H_ - - -/* USB Controller (USBx_CONTROLLER_) regs */ -struct usb_ctlr { - /* 0x000 */ - uint id; - uint reserved0; - uint host; - uint device; - - /* 0x010 */ - uint txbuf; - uint rxbuf; - uint reserved1[2]; - - /* 0x020 */ - uint reserved2[56]; - - /* 0x100 */ - u16 cap_length; - u16 hci_version; - uint hcs_params; - uint hcc_params; - uint reserved3[5]; - - /* 0x120 */ - uint dci_version; - uint dcc_params; - uint reserved4[2]; - - /* 0x130 */ - uint usb_cmd; - uint usb_sts; - uint usb_intr; - uint frindex; - - /* 0x140 */ - uint reserved5; - uint periodic_list_base; - uint async_list_addr; - uint reserved5_1; - - /* 0x150 */ - uint burst_size; - uint tx_fill_tuning; - uint reserved6; - uint icusb_ctrl; - - /* 0x160 */ - uint ulpi_viewport; - uint reserved7; - uint reserved7_0; - uint reserved7_1; - - /* 0x170 */ - uint reserved; - uint port_sc1; - uint reserved8[6]; - - /* 0x190 */ - uint reserved9[8]; - - /* 0x1b0 */ - uint reserved10; - uint hostpc1_devlc; - uint reserved10_1[2]; - - /* 0x1c0 */ - uint reserved10_2[4]; - - /* 0x1d0 */ - uint reserved10_3[4]; - - /* 0x1e0 */ - uint reserved10_4[4]; - - /* 0x1f0 */ - uint reserved10_5; - uint otgsc; - uint usb_mode; - uint reserved10_6; - - /* 0x200 */ - uint endpt_nak; - uint endpt_nak_enable; - uint endpt_setup_stat; - uint reserved11_1[0x7D]; - - /* 0x400 */ - uint susp_ctrl; - uint phy_vbus_sensors; - uint phy_vbus_wakeup_id; - uint phy_alt_vbus_sys; - - /* 0x410 */ - uint usb1_legacy_ctrl; - uint reserved12[3]; - - /* 0x420 */ - uint reserved13[56]; - - /* 0x500 */ - uint reserved14[64 * 3]; - - /* 0x800 */ - uint utmip_pll_cfg0; - uint utmip_pll_cfg1; - uint utmip_xcvr_cfg0; - uint utmip_bias_cfg0; - - /* 0x810 */ - uint utmip_hsrx_cfg0; - uint utmip_hsrx_cfg1; - uint utmip_fslsrx_cfg0; - uint utmip_fslsrx_cfg1; - - /* 0x820 */ - uint utmip_tx_cfg0; - uint utmip_misc_cfg0; - uint utmip_misc_cfg1; - uint utmip_debounce_cfg0; - - /* 0x830 */ - uint utmip_bat_chrg_cfg0; - uint utmip_spare_cfg0; - uint utmip_xcvr_cfg1; - uint utmip_bias_cfg1; -}; - -/* USB1_LEGACY_CTRL */ -#define USB1_NO_LEGACY_MODE 1 - -#define VBUS_SENSE_CTL_SHIFT 1 -#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT) -#define VBUS_SENSE_CTL_VBUS_WAKEUP 0 -#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1 -#define VBUS_SENSE_CTL_AB_SESS_VLD 2 -#define VBUS_SENSE_CTL_A_SESS_VLD 3 - -/* USBx_IF_USB_SUSP_CTRL_0 */ -#define UTMIP_PHY_ENB (1 << 12) -#define UTMIP_RESET (1 << 11) -#define USB_PHY_CLK_VALID (1 << 7) -#define USB_SUSP_CLR (1 << 5) - -/* USBx_UTMIP_MISC_CFG0 */ -#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) - -/* USBx_UTMIP_MISC_CFG1 */ -#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) - -/* Moved to Clock and Reset register space */ -#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 -#define UTMIP_PLLU_STABLE_COUNT_MASK \ - (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) -/* Moved to Clock and Reset register space */ -#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 -#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ - (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) - -/* USBx_UTMIP_PLL_CFG1_0 */ -/* Moved to Clock and Reset register space */ -#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 -#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ - (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) -#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 -#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff - -/* USBx_UTMIP_BIAS_CFG0_0 */ -#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24) -#define UTMIP_OTGPD (1 << 11) -#define UTMIP_BIASPD (1 << 10) -#define UTMIP_HSDISCON_LEVEL_SHIFT 2 -#define UTMIP_HSDISCON_LEVEL_MASK \ - (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT) -#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0 -#define UTMIP_HSSQUELCH_LEVEL_MASK \ - (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT) - -/* USBx_UTMIP_BIAS_CFG1_0 */ -#define UTMIP_FORCE_PDTRK_POWERDOWN 1 -#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 -#define UTMIP_BIAS_PDTRK_COUNT_MASK \ - (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) - -/* USBx_UTMIP_DEBOUNCE_CFG0_0 */ -#define UTMIP_DEBOUNCE_CFG0_SHIFT 0 -#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff - -/* USBx_UTMIP_TX_CFG0_0 */ -#define UTMIP_FS_PREAMBLE_J (1 << 19) - -/* USBx_UTMIP_BAT_CHRG_CFG0_0 */ -#define UTMIP_PD_CHRG 1 - -/* USBx_UTMIP_SPARE_CFG0_0 */ -#define FUSE_SETUP_SEL (1 << 3) - -/* USBx_UTMIP_HSRX_CFG0_0 */ -#define UTMIP_IDLE_WAIT_SHIFT 15 -#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT) -#define UTMIP_ELASTIC_LIMIT_SHIFT 10 -#define UTMIP_ELASTIC_LIMIT_MASK \ - (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT) - -/* USBx_UTMIP_HSRX_CFG0_1 */ -#define UTMIP_HS_SYNC_START_DLY_SHIFT 1 -#define UTMIP_HS_SYNC_START_DLY_MASK \ - (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT) - -/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ -#define IC_ENB1 (1 << 3) - -/* PORTSC1, USB1, defined for Tegra20 to avoid compiling error */ -#define PTS1_SHIFT 31 -#define PTS1_MASK (1 << PTS1_SHIFT) -#define STS1 (1 << 30) - -/* USB2D_HOSTPC1_DEVLC_0 */ -#define PTS_SHIFT 29 -#define PTS_MASK (0x7U << PTS_SHIFT) -#define PTS_UTMI 0 -#define PTS_RESERVED 1 -#define PTS_ULPI 2 -#define PTS_ICUSB_SER 3 -#define PTS_HSIC 4 - -#define STS (1 << 28) - -/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ -#define WKOC (1 << 22) -#define WKDS (1 << 21) -#define WKCN (1 << 20) - -/* USBx_UTMIP_XCVR_CFG0_0 */ -#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) -#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) -#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) -#define UTMIP_XCVR_LSBIAS_SE (1 << 21) -#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25 -#define UTMIP_XCVR_HSSLEW_MSB_MASK \ - (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT) -#define UTMIP_XCVR_SETUP_MSB_SHIFT 22 -#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT) -#define UTMIP_XCVR_SETUP_SHIFT 0 -#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT) - -/* USBx_UTMIP_XCVR_CFG1_0 */ -#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18 -#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \ - (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT) -#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) -#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) - -/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ -#define VBUS_VLD_STS (1 << 26) - -#endif /* _TEGRA124_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h index 05925df861d..11c0104ff3e 100644 --- a/arch/arm/include/asm/arch-tegra20/pinmux.h +++ b/arch/arm/include/asm/arch-tegra20/pinmux.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _PINMUX_H_ -#define _PINMUX_H_ +#ifndef _TEGRA20_PINMUX_H_ +#define _TEGRA20_PINMUX_H_ /* * Pin groups which we adjust. There are three basic attributes of each pin @@ -18,148 +18,146 @@ */ enum pmux_pingrp { /* APB_MISC_PP_TRISTATE_REG_A_0 */ - PINGRP_ATA, - PINGRP_ATB, - PINGRP_ATC, - PINGRP_ATD, - PINGRP_CDEV1, - PINGRP_CDEV2, - PINGRP_CSUS, - PINGRP_DAP1, - - PINGRP_DAP2, - PINGRP_DAP3, - PINGRP_DAP4, - PINGRP_DTA, - PINGRP_DTB, - PINGRP_DTC, - PINGRP_DTD, - PINGRP_DTE, - - PINGRP_GPU, - PINGRP_GPV, - PINGRP_I2CP, - PINGRP_IRTX, - PINGRP_IRRX, - PINGRP_KBCB, - PINGRP_KBCA, - PINGRP_PMC, - - PINGRP_PTA, - PINGRP_RM, - PINGRP_KBCE, - PINGRP_KBCF, - PINGRP_GMA, - PINGRP_GMC, - PINGRP_SDIO1, - PINGRP_OWC, + PMUX_PINGRP_ATA, + PMUX_PINGRP_ATB, + PMUX_PINGRP_ATC, + PMUX_PINGRP_ATD, + PMUX_PINGRP_CDEV1, + PMUX_PINGRP_CDEV2, + PMUX_PINGRP_CSUS, + PMUX_PINGRP_DAP1, + + PMUX_PINGRP_DAP2, + PMUX_PINGRP_DAP3, + PMUX_PINGRP_DAP4, + PMUX_PINGRP_DTA, + PMUX_PINGRP_DTB, + PMUX_PINGRP_DTC, + PMUX_PINGRP_DTD, + PMUX_PINGRP_DTE, + + PMUX_PINGRP_GPU, + PMUX_PINGRP_GPV, + PMUX_PINGRP_I2CP, + PMUX_PINGRP_IRTX, + PMUX_PINGRP_IRRX, + PMUX_PINGRP_KBCB, + PMUX_PINGRP_KBCA, + PMUX_PINGRP_PMC, + + PMUX_PINGRP_PTA, + PMUX_PINGRP_RM, + PMUX_PINGRP_KBCE, + PMUX_PINGRP_KBCF, + PMUX_PINGRP_GMA, + PMUX_PINGRP_GMC, + PMUX_PINGRP_SDIO1, + PMUX_PINGRP_OWC, /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ - PINGRP_GME, - PINGRP_SDC, - PINGRP_SDD, - PINGRP_RESERVED0, - PINGRP_SLXA, - PINGRP_SLXC, - PINGRP_SLXD, - PINGRP_SLXK, - - PINGRP_SPDI, - PINGRP_SPDO, - PINGRP_SPIA, - PINGRP_SPIB, - PINGRP_SPIC, - PINGRP_SPID, - PINGRP_SPIE, - PINGRP_SPIF, - - PINGRP_SPIG, - PINGRP_SPIH, - PINGRP_UAA, - PINGRP_UAB, - PINGRP_UAC, - PINGRP_UAD, - PINGRP_UCA, - PINGRP_UCB, - - PINGRP_RESERVED1, - PINGRP_ATE, - PINGRP_KBCC, - PINGRP_RESERVED2, - PINGRP_RESERVED3, - PINGRP_GMB, - PINGRP_GMD, - PINGRP_DDC, + PMUX_PINGRP_GME, + PMUX_PINGRP_SDC, + PMUX_PINGRP_SDD, + PMUX_PINGRP_RESERVED0, + PMUX_PINGRP_SLXA, + PMUX_PINGRP_SLXC, + PMUX_PINGRP_SLXD, + PMUX_PINGRP_SLXK, + + PMUX_PINGRP_SPDI, + PMUX_PINGRP_SPDO, + PMUX_PINGRP_SPIA, + PMUX_PINGRP_SPIB, + PMUX_PINGRP_SPIC, + PMUX_PINGRP_SPID, + PMUX_PINGRP_SPIE, + PMUX_PINGRP_SPIF, + + PMUX_PINGRP_SPIG, + PMUX_PINGRP_SPIH, + PMUX_PINGRP_UAA, + PMUX_PINGRP_UAB, + PMUX_PINGRP_UAC, + PMUX_PINGRP_UAD, + PMUX_PINGRP_UCA, + PMUX_PINGRP_UCB, + + PMUX_PINGRP_RESERVED1, + PMUX_PINGRP_ATE, + PMUX_PINGRP_KBCC, + PMUX_PINGRP_RESERVED2, + PMUX_PINGRP_RESERVED3, + PMUX_PINGRP_GMB, + PMUX_PINGRP_GMD, + PMUX_PINGRP_DDC, /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */ - PINGRP_LD0, - PINGRP_LD1, - PINGRP_LD2, - PINGRP_LD3, - PINGRP_LD4, - PINGRP_LD5, - PINGRP_LD6, - PINGRP_LD7, - - PINGRP_LD8, - PINGRP_LD9, - PINGRP_LD10, - PINGRP_LD11, - PINGRP_LD12, - PINGRP_LD13, - PINGRP_LD14, - PINGRP_LD15, - - PINGRP_LD16, - PINGRP_LD17, - PINGRP_LHP0, - PINGRP_LHP1, - PINGRP_LHP2, - PINGRP_LVP0, - PINGRP_LVP1, - PINGRP_HDINT, - - PINGRP_LM0, - PINGRP_LM1, - PINGRP_LVS, - PINGRP_LSC0, - PINGRP_LSC1, - PINGRP_LSCK, - PINGRP_LDC, - PINGRP_LCSN, + PMUX_PINGRP_LD0, + PMUX_PINGRP_LD1, + PMUX_PINGRP_LD2, + PMUX_PINGRP_LD3, + PMUX_PINGRP_LD4, + PMUX_PINGRP_LD5, + PMUX_PINGRP_LD6, + PMUX_PINGRP_LD7, + + PMUX_PINGRP_LD8, + PMUX_PINGRP_LD9, + PMUX_PINGRP_LD10, + PMUX_PINGRP_LD11, + PMUX_PINGRP_LD12, + PMUX_PINGRP_LD13, + PMUX_PINGRP_LD14, + PMUX_PINGRP_LD15, + + PMUX_PINGRP_LD16, + PMUX_PINGRP_LD17, + PMUX_PINGRP_LHP0, + PMUX_PINGRP_LHP1, + PMUX_PINGRP_LHP2, + PMUX_PINGRP_LVP0, + PMUX_PINGRP_LVP1, + PMUX_PINGRP_HDINT, + + PMUX_PINGRP_LM0, + PMUX_PINGRP_LM1, + PMUX_PINGRP_LVS, + PMUX_PINGRP_LSC0, + PMUX_PINGRP_LSC1, + PMUX_PINGRP_LSCK, + PMUX_PINGRP_LDC, + PMUX_PINGRP_LCSN, /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */ - PINGRP_LSPI, - PINGRP_LSDA, - PINGRP_LSDI, - PINGRP_LPW0, - PINGRP_LPW1, - PINGRP_LPW2, - PINGRP_LDI, - PINGRP_LHS, - - PINGRP_LPP, - PINGRP_RESERVED4, - PINGRP_KBCD, - PINGRP_GPU7, - PINGRP_DTF, - PINGRP_UDA, - PINGRP_CRTP, - PINGRP_SDB, + PMUX_PINGRP_LSPI, + PMUX_PINGRP_LSDA, + PMUX_PINGRP_LSDI, + PMUX_PINGRP_LPW0, + PMUX_PINGRP_LPW1, + PMUX_PINGRP_LPW2, + PMUX_PINGRP_LDI, + PMUX_PINGRP_LHS, + + PMUX_PINGRP_LPP, + PMUX_PINGRP_RESERVED4, + PMUX_PINGRP_KBCD, + PMUX_PINGRP_GPU7, + PMUX_PINGRP_DTF, + PMUX_PINGRP_UDA, + PMUX_PINGRP_CRTP, + PMUX_PINGRP_SDB, /* these pin groups only have pullup and pull down control */ - PINGRP_FIRST_NO_MUX, - PINGRP_CK32 = PINGRP_FIRST_NO_MUX, - PINGRP_DDRC, - PINGRP_PMCA, - PINGRP_PMCB, - PINGRP_PMCC, - PINGRP_PMCD, - PINGRP_PMCE, - PINGRP_XM2C, - PINGRP_XM2D, - - PINGRP_COUNT, + PMUX_PINGRP_CK32, + PMUX_PINGRP_DDRC, + PMUX_PINGRP_PMCA, + PMUX_PINGRP_PMCB, + PMUX_PINGRP_PMCC, + PMUX_PINGRP_PMCD, + PMUX_PINGRP_PMCE, + PMUX_PINGRP_XM2C, + PMUX_PINGRP_XM2D, + PMUX_PINGRP_COUNT, }; /* @@ -227,111 +225,13 @@ enum pmux_func { PMUX_FUNC_VI, PMUX_FUNC_VI_SENSOR_CLK, PMUX_FUNC_XIO, - PMUX_FUNC_SAFE, - - /* These don't have a name, but can be used in the table */ PMUX_FUNC_RSVD1, PMUX_FUNC_RSVD2, PMUX_FUNC_RSVD3, PMUX_FUNC_RSVD4, - PMUX_FUNC_RSVD, /* Not valid and should not be used */ - PMUX_FUNC_COUNT, - - PMUX_FUNC_NONE = -1, -}; - -/* return 1 if a pmux_func is in range */ -#define pmux_func_isvalid(func) ((func) >= 0 && (func) < PMUX_FUNC_COUNT && \ - (func) != PMUX_FUNC_RSVD) - -/* The pullup/pulldown state of a pin group */ -enum pmux_pull { - PMUX_PULL_NORMAL = 0, - PMUX_PULL_DOWN, - PMUX_PULL_UP, -}; - -/* Defines whether a pin group is tristated or in normal operation */ -enum pmux_tristate { - PMUX_TRI_NORMAL = 0, - PMUX_TRI_TRISTATE = 1, -}; - -/* Available power domains used by pin groups */ -enum pmux_vddio { - PMUX_VDDIO_BB = 0, - PMUX_VDDIO_LCD, - PMUX_VDDIO_VI, - PMUX_VDDIO_UART, - PMUX_VDDIO_DDR, - PMUX_VDDIO_NAND, - PMUX_VDDIO_SYS, - PMUX_VDDIO_AUDIO, - PMUX_VDDIO_SD, - - PMUX_VDDIO_NONE -}; - -enum { - PMUX_TRISTATE_REGS = 4, - PMUX_MUX_REGS = 7, - PMUX_PULL_REGS = 5, -}; - -/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */ -struct pmux_tri_ctlr { - uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ - uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */ - uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ - uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */ - uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */ - uint pmt_tri[PMUX_TRISTATE_REGS];/* _TRI_STATE_REG_A/B/C/D_0 14-20 */ - uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ - - uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */ - - uint pmt_ctl[PMUX_MUX_REGS]; /* _PIN_MUX_CTL_A-G_0, offset 80 */ - uint pmt_reserved4; /* ABP_MISC_PP_ reserved offset 9c */ - uint pmt_pull[PMUX_PULL_REGS]; /* APB_MISC_PP_PULLUPDOWN_REG_A-E */ -}; - -/* - * This defines the configuration for a pin, including the function assigned, - * pull up/down settings and tristate settings. Having set up one of these - * you can call pinmux_config_pingroup() to configure a pin in one step. Also - * available is pinmux_config_table() to configure a list of pins. - */ -struct pingroup_config { - enum pmux_pingrp pingroup; /* pin group PINGRP_... */ - enum pmux_func func; /* function to assign FUNC_... */ - enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ - enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ }; -/* Set a pin group to tristate */ -void pinmux_tristate_enable(enum pmux_pingrp pin); - -/* Set a pin group to normal (non tristate) */ -void pinmux_tristate_disable(enum pmux_pingrp pin); - -/* Set the pull up/down feature for a pin group */ -void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); - -/* Set the mux function for a pin group */ -void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); - -/* Set the complete configuration for a pin group */ -void pinmux_config_pingroup(const struct pingroup_config *config); - -void pinmux_set_tristate(enum pmux_pingrp pin, int enable); - -/** - * Configuure a list of pin groups - * - * @param config List of config items - * @param len Number of config items in list - */ -void pinmux_config_table(const struct pingroup_config *config, int len); +#include <asm/arch-tegra/pinmux.h> -#endif /* PINMUX_H */ +#endif /* _TEGRA20_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/usb.h b/arch/arm/include/asm/arch-tegra20/usb.h deleted file mode 100644 index 3d94cc73b8b..00000000000 --- a/arch/arm/include/asm/arch-tegra20/usb.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2013 NVIDIA Corporation - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA20_USB_H_ -#define _TEGRA20_USB_H_ - -/* USB Controller (USBx_CONTROLLER_) regs */ -struct usb_ctlr { - /* 0x000 */ - uint id; - uint reserved0; - uint host; - uint device; - - /* 0x010 */ - uint txbuf; - uint rxbuf; - uint reserved1[2]; - - /* 0x020 */ - uint reserved2[56]; - - /* 0x100 */ - u16 cap_length; - u16 hci_version; - uint hcs_params; - uint hcc_params; - uint reserved3[5]; - - /* 0x120 */ - uint dci_version; - uint dcc_params; - uint reserved4[6]; - - /* 0x140 */ - uint usb_cmd; - uint usb_sts; - uint usb_intr; - uint frindex; - - /* 0x150 */ - uint reserved5; - uint periodic_list_base; - uint async_list_addr; - uint async_tt_sts; - - /* 0x160 */ - uint burst_size; - uint tx_fill_tuning; - uint reserved6; /* is this port_sc1 on some controllers? */ - uint icusb_ctrl; - - /* 0x170 */ - uint ulpi_viewport; - uint reserved7; - uint endpt_nak; - uint endpt_nak_enable; - - /* 0x180 */ - uint reserved; - uint port_sc1; - uint reserved8[6]; - - /* 0x1a0 */ - uint reserved9; - uint otgsc; - uint usb_mode; - uint endpt_setup_stat; - - /* 0x1b0 */ - uint reserved10[20]; - - /* 0x200 */ - uint reserved11[0x80]; - - /* 0x400 */ - uint susp_ctrl; - uint phy_vbus_sensors; - uint phy_vbus_wakeup_id; - uint phy_alt_vbus_sys; - - /* 0x410 */ - uint usb1_legacy_ctrl; - uint reserved12[4]; - - /* 0x424 */ - uint ulpi_timing_ctrl_0; - uint ulpi_timing_ctrl_1; - uint reserved13[53]; - - /* 0x500 */ - uint reserved14[64 * 3]; - - /* 0x800 */ - uint utmip_pll_cfg0; - uint utmip_pll_cfg1; - uint utmip_xcvr_cfg0; - uint utmip_bias_cfg0; - - /* 0x810 */ - uint utmip_hsrx_cfg0; - uint utmip_hsrx_cfg1; - uint utmip_fslsrx_cfg0; - uint utmip_fslsrx_cfg1; - - /* 0x820 */ - uint utmip_tx_cfg0; - uint utmip_misc_cfg0; - uint utmip_misc_cfg1; - uint utmip_debounce_cfg0; - - /* 0x830 */ - uint utmip_bat_chrg_cfg0; - uint utmip_spare_cfg0; - uint utmip_xcvr_cfg1; - uint utmip_bias_cfg1; -}; - -/* USB2_IF_ULPI_TIMING_CTRL_0 */ -#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) -#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) - -/* USB2_IF_ULPI_TIMING_CTRL_1 */ -#define ULPI_DATA_TRIMMER_LOAD (1 << 0) -#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) -#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) -#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) -#define ULPI_DIR_TRIMMER_LOAD (1 << 24) -#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) - -/* PORTSC, USB2, USB3 */ -#define PTS_SHIFT 30 -#define PTS_MASK (3U << PTS_SHIFT) - -#define STS (1 << 29) -#endif /* _TEGRA20_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h index a9e1b462c4a..6d83061dc1e 100644 --- a/arch/arm/include/asm/arch-tegra30/pinmux.h +++ b/arch/arm/include/asm/arch-tegra30/pinmux.h @@ -1,668 +1,397 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA30_PINMUX_H_ #define _TEGRA30_PINMUX_H_ -/* - * Pin groups which we adjust. There are three basic attributes of each pin - * group which use this enum: - * - * - function - * - pullup / pulldown - * - tristate or normal - */ enum pmux_pingrp { - PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */ - PINGRP_ULPI_DATA1, - PINGRP_ULPI_DATA2, - PINGRP_ULPI_DATA3, - PINGRP_ULPI_DATA4, - PINGRP_ULPI_DATA5, - PINGRP_ULPI_DATA6, - PINGRP_ULPI_DATA7, - PINGRP_ULPI_CLK, - PINGRP_ULPI_DIR, - PINGRP_ULPI_NXT, - PINGRP_ULPI_STP, - PINGRP_DAP3_FS, - PINGRP_DAP3_DIN, - PINGRP_DAP3_DOUT, - PINGRP_DAP3_SCLK, - PINGRP_GPIO_PV0, - PINGRP_GPIO_PV1, - PINGRP_SDMMC1_CLK, - PINGRP_SDMMC1_CMD, - PINGRP_SDMMC1_DAT3, - PINGRP_SDMMC1_DAT2, - PINGRP_SDMMC1_DAT1, - PINGRP_SDMMC1_DAT0, - PINGRP_GPIO_PV2, - PINGRP_GPIO_PV3, - PINGRP_CLK2_OUT, - PINGRP_CLK2_REQ, - PINGRP_LCD_PWR1, - PINGRP_LCD_PWR2, - PINGRP_LCD_SDIN, - PINGRP_LCD_SDOUT, - PINGRP_LCD_WR_N, - PINGRP_LCD_CS0_N, - PINGRP_LCD_DC0, - PINGRP_LCD_SCK, - PINGRP_LCD_PWR0, - PINGRP_LCD_PCLK, - PINGRP_LCD_DE, - PINGRP_LCD_HSYNC, - PINGRP_LCD_VSYNC, - PINGRP_LCD_D0, - PINGRP_LCD_D1, - PINGRP_LCD_D2, - PINGRP_LCD_D3, - PINGRP_LCD_D4, - PINGRP_LCD_D5, - PINGRP_LCD_D6, - PINGRP_LCD_D7, - PINGRP_LCD_D8, - PINGRP_LCD_D9, - PINGRP_LCD_D10, - PINGRP_LCD_D11, - PINGRP_LCD_D12, - PINGRP_LCD_D13, - PINGRP_LCD_D14, - PINGRP_LCD_D15, - PINGRP_LCD_D16, - PINGRP_LCD_D17, - PINGRP_LCD_D18, - PINGRP_LCD_D19, - PINGRP_LCD_D20, - PINGRP_LCD_D21, - PINGRP_LCD_D22, - PINGRP_LCD_D23, - PINGRP_LCD_CS1_N, - PINGRP_LCD_M1, - PINGRP_LCD_DC1, - PINGRP_HDMI_INT, - PINGRP_DDC_SCL, - PINGRP_DDC_SDA, - PINGRP_CRT_HSYNC, - PINGRP_CRT_VSYNC, - PINGRP_VI_D0, - PINGRP_VI_D1, - PINGRP_VI_D2, - PINGRP_VI_D3, - PINGRP_VI_D4, - PINGRP_VI_D5, - PINGRP_VI_D6, - PINGRP_VI_D7, - PINGRP_VI_D8, - PINGRP_VI_D9, - PINGRP_VI_D10, - PINGRP_VI_D11, - PINGRP_VI_PCLK, - PINGRP_VI_MCLK, - PINGRP_VI_VSYNC, - PINGRP_VI_HSYNC, - PINGRP_UART2_RXD, - PINGRP_UART2_TXD, - PINGRP_UART2_RTS_N, - PINGRP_UART2_CTS_N, - PINGRP_UART3_TXD, - PINGRP_UART3_RXD, - PINGRP_UART3_CTS_N, - PINGRP_UART3_RTS_N, - PINGRP_GPIO_PU0, - PINGRP_GPIO_PU1, - PINGRP_GPIO_PU2, - PINGRP_GPIO_PU3, - PINGRP_GPIO_PU4, - PINGRP_GPIO_PU5, - PINGRP_GPIO_PU6, - PINGRP_GEN1_I2C_SDA, - PINGRP_GEN1_I2C_SCL, - PINGRP_DAP4_FS, - PINGRP_DAP4_DIN, - PINGRP_DAP4_DOUT, - PINGRP_DAP4_SCLK, - PINGRP_CLK3_OUT, - PINGRP_CLK3_REQ, - PINGRP_GMI_WP_N, - PINGRP_GMI_IORDY, - PINGRP_GMI_WAIT, - PINGRP_GMI_ADV_N, - PINGRP_GMI_CLK, - PINGRP_GMI_CS0_N, - PINGRP_GMI_CS1_N, - PINGRP_GMI_CS2_N, - PINGRP_GMI_CS3_N, - PINGRP_GMI_CS4_N, - PINGRP_GMI_CS6_N, - PINGRP_GMI_CS7_N, - PINGRP_GMI_AD0, - PINGRP_GMI_AD1, - PINGRP_GMI_AD2, - PINGRP_GMI_AD3, - PINGRP_GMI_AD4, - PINGRP_GMI_AD5, - PINGRP_GMI_AD6, - PINGRP_GMI_AD7, - PINGRP_GMI_AD8, - PINGRP_GMI_AD9, - PINGRP_GMI_AD10, - PINGRP_GMI_AD11, - PINGRP_GMI_AD12, - PINGRP_GMI_AD13, - PINGRP_GMI_AD14, - PINGRP_GMI_AD15, - PINGRP_GMI_A16, - PINGRP_GMI_A17, - PINGRP_GMI_A18, - PINGRP_GMI_A19, - PINGRP_GMI_WR_N, - PINGRP_GMI_OE_N, - PINGRP_GMI_DQS, - PINGRP_GMI_RST_N, - PINGRP_GEN2_I2C_SCL, - PINGRP_GEN2_I2C_SDA, - PINGRP_SDMMC4_CLK, - PINGRP_SDMMC4_CMD, - PINGRP_SDMMC4_DAT0, - PINGRP_SDMMC4_DAT1, - PINGRP_SDMMC4_DAT2, - PINGRP_SDMMC4_DAT3, - PINGRP_SDMMC4_DAT4, - PINGRP_SDMMC4_DAT5, - PINGRP_SDMMC4_DAT6, - PINGRP_SDMMC4_DAT7, - PINGRP_SDMMC4_RST_N, - PINGRP_CAM_MCLK, - PINGRP_GPIO_PCC1, - PINGRP_GPIO_PBB0, - PINGRP_CAM_I2C_SCL, - PINGRP_CAM_I2C_SDA, - PINGRP_GPIO_PBB3, - PINGRP_GPIO_PBB4, - PINGRP_GPIO_PBB5, - PINGRP_GPIO_PBB6, - PINGRP_GPIO_PBB7, - PINGRP_GPIO_PCC2, - PINGRP_JTAG_RTCK, - PINGRP_PWR_I2C_SCL, - PINGRP_PWR_I2C_SDA, - PINGRP_KB_ROW0, - PINGRP_KB_ROW1, - PINGRP_KB_ROW2, - PINGRP_KB_ROW3, - PINGRP_KB_ROW4, - PINGRP_KB_ROW5, - PINGRP_KB_ROW6, - PINGRP_KB_ROW7, - PINGRP_KB_ROW8, - PINGRP_KB_ROW9, - PINGRP_KB_ROW10, - PINGRP_KB_ROW11, - PINGRP_KB_ROW12, - PINGRP_KB_ROW13, - PINGRP_KB_ROW14, - PINGRP_KB_ROW15, - PINGRP_KB_COL0, - PINGRP_KB_COL1, - PINGRP_KB_COL2, - PINGRP_KB_COL3, - PINGRP_KB_COL4, - PINGRP_KB_COL5, - PINGRP_KB_COL6, - PINGRP_KB_COL7, - PINGRP_CLK_32K_OUT, - PINGRP_SYS_CLK_REQ, - PINGRP_CORE_PWR_REQ, - PINGRP_CPU_PWR_REQ, - PINGRP_PWR_INT_N, - PINGRP_CLK_32K_IN, - PINGRP_OWR, - PINGRP_DAP1_FS, - PINGRP_DAP1_DIN, - PINGRP_DAP1_DOUT, - PINGRP_DAP1_SCLK, - PINGRP_CLK1_REQ, - PINGRP_CLK1_OUT, - PINGRP_SPDIF_IN, - PINGRP_SPDIF_OUT, - PINGRP_DAP2_FS, - PINGRP_DAP2_DIN, - PINGRP_DAP2_DOUT, - PINGRP_DAP2_SCLK, - PINGRP_SPI2_MOSI, - PINGRP_SPI2_MISO, - PINGRP_SPI2_CS0_N, - PINGRP_SPI2_SCK, - PINGRP_SPI1_MOSI, - PINGRP_SPI1_SCK, - PINGRP_SPI1_CS0_N, - PINGRP_SPI1_MISO, - PINGRP_SPI2_CS1_N, - PINGRP_SPI2_CS2_N, - PINGRP_SDMMC3_CLK, - PINGRP_SDMMC3_CMD, - PINGRP_SDMMC3_DAT0, - PINGRP_SDMMC3_DAT1, - PINGRP_SDMMC3_DAT2, - PINGRP_SDMMC3_DAT3, - PINGRP_SDMMC3_DAT4, - PINGRP_SDMMC3_DAT5, - PINGRP_SDMMC3_DAT6, - PINGRP_SDMMC3_DAT7, - PINGRP_PEX_L0_PRSNT_N, - PINGRP_PEX_L0_RST_N, - PINGRP_PEX_L0_CLKREQ_N, - PINGRP_PEX_WAKE_N, - PINGRP_PEX_L1_PRSNT_N, - PINGRP_PEX_L1_RST_N, - PINGRP_PEX_L1_CLKREQ_N, - PINGRP_PEX_L2_PRSNT_N, - PINGRP_PEX_L2_RST_N, - PINGRP_PEX_L2_CLKREQ_N, - PINGRP_HDMI_CEC, /* offset 0x33e0 */ - PINGRP_COUNT, + PMUX_PINGRP_ULPI_DATA0_PO1, + PMUX_PINGRP_ULPI_DATA1_PO2, + PMUX_PINGRP_ULPI_DATA2_PO3, + PMUX_PINGRP_ULPI_DATA3_PO4, + PMUX_PINGRP_ULPI_DATA4_PO5, + PMUX_PINGRP_ULPI_DATA5_PO6, + PMUX_PINGRP_ULPI_DATA6_PO7, + PMUX_PINGRP_ULPI_DATA7_PO0, + PMUX_PINGRP_ULPI_CLK_PY0, + PMUX_PINGRP_ULPI_DIR_PY1, + PMUX_PINGRP_ULPI_NXT_PY2, + PMUX_PINGRP_ULPI_STP_PY3, + PMUX_PINGRP_DAP3_FS_PP0, + PMUX_PINGRP_DAP3_DIN_PP1, + PMUX_PINGRP_DAP3_DOUT_PP2, + PMUX_PINGRP_DAP3_SCLK_PP3, + PMUX_PINGRP_PV0, + PMUX_PINGRP_PV1, + PMUX_PINGRP_SDMMC1_CLK_PZ0, + PMUX_PINGRP_SDMMC1_CMD_PZ1, + PMUX_PINGRP_SDMMC1_DAT3_PY4, + PMUX_PINGRP_SDMMC1_DAT2_PY5, + PMUX_PINGRP_SDMMC1_DAT1_PY6, + PMUX_PINGRP_SDMMC1_DAT0_PY7, + PMUX_PINGRP_PV2, + PMUX_PINGRP_PV3, + PMUX_PINGRP_CLK2_OUT_PW5, + PMUX_PINGRP_CLK2_REQ_PCC5, + PMUX_PINGRP_LCD_PWR1_PC1, + PMUX_PINGRP_LCD_PWR2_PC6, + PMUX_PINGRP_LCD_SDIN_PZ2, + PMUX_PINGRP_LCD_SDOUT_PN5, + PMUX_PINGRP_LCD_WR_N_PZ3, + PMUX_PINGRP_LCD_CS0_N_PN4, + PMUX_PINGRP_LCD_DC0_PN6, + PMUX_PINGRP_LCD_SCK_PZ4, + PMUX_PINGRP_LCD_PWR0_PB2, + PMUX_PINGRP_LCD_PCLK_PB3, + PMUX_PINGRP_LCD_DE_PJ1, + PMUX_PINGRP_LCD_HSYNC_PJ3, + PMUX_PINGRP_LCD_VSYNC_PJ4, + PMUX_PINGRP_LCD_D0_PE0, + PMUX_PINGRP_LCD_D1_PE1, + PMUX_PINGRP_LCD_D2_PE2, + PMUX_PINGRP_LCD_D3_PE3, + PMUX_PINGRP_LCD_D4_PE4, + PMUX_PINGRP_LCD_D5_PE5, + PMUX_PINGRP_LCD_D6_PE6, + PMUX_PINGRP_LCD_D7_PE7, + PMUX_PINGRP_LCD_D8_PF0, + PMUX_PINGRP_LCD_D9_PF1, + PMUX_PINGRP_LCD_D10_PF2, + PMUX_PINGRP_LCD_D11_PF3, + PMUX_PINGRP_LCD_D12_PF4, + PMUX_PINGRP_LCD_D13_PF5, + PMUX_PINGRP_LCD_D14_PF6, + PMUX_PINGRP_LCD_D15_PF7, + PMUX_PINGRP_LCD_D16_PM0, + PMUX_PINGRP_LCD_D17_PM1, + PMUX_PINGRP_LCD_D18_PM2, + PMUX_PINGRP_LCD_D19_PM3, + PMUX_PINGRP_LCD_D20_PM4, + PMUX_PINGRP_LCD_D21_PM5, + PMUX_PINGRP_LCD_D22_PM6, + PMUX_PINGRP_LCD_D23_PM7, + PMUX_PINGRP_LCD_CS1_N_PW0, + PMUX_PINGRP_LCD_M1_PW1, + PMUX_PINGRP_LCD_DC1_PD2, + PMUX_PINGRP_HDMI_INT_PN7, + PMUX_PINGRP_DDC_SCL_PV4, + PMUX_PINGRP_DDC_SDA_PV5, + PMUX_PINGRP_CRT_HSYNC_PV6, + PMUX_PINGRP_CRT_VSYNC_PV7, + PMUX_PINGRP_VI_D0_PT4, + PMUX_PINGRP_VI_D1_PD5, + PMUX_PINGRP_VI_D2_PL0, + PMUX_PINGRP_VI_D3_PL1, + PMUX_PINGRP_VI_D4_PL2, + PMUX_PINGRP_VI_D5_PL3, + PMUX_PINGRP_VI_D6_PL4, + PMUX_PINGRP_VI_D7_PL5, + PMUX_PINGRP_VI_D8_PL6, + PMUX_PINGRP_VI_D9_PL7, + PMUX_PINGRP_VI_D10_PT2, + PMUX_PINGRP_VI_D11_PT3, + PMUX_PINGRP_VI_PCLK_PT0, + PMUX_PINGRP_VI_MCLK_PT1, + PMUX_PINGRP_VI_VSYNC_PD6, + PMUX_PINGRP_VI_HSYNC_PD7, + PMUX_PINGRP_UART2_RXD_PC3, + PMUX_PINGRP_UART2_TXD_PC2, + PMUX_PINGRP_UART2_RTS_N_PJ6, + PMUX_PINGRP_UART2_CTS_N_PJ5, + PMUX_PINGRP_UART3_TXD_PW6, + PMUX_PINGRP_UART3_RXD_PW7, + PMUX_PINGRP_UART3_CTS_N_PA1, + PMUX_PINGRP_UART3_RTS_N_PC0, + PMUX_PINGRP_PU0, + PMUX_PINGRP_PU1, + PMUX_PINGRP_PU2, + PMUX_PINGRP_PU3, + PMUX_PINGRP_PU4, + PMUX_PINGRP_PU5, + PMUX_PINGRP_PU6, + PMUX_PINGRP_GEN1_I2C_SDA_PC5, + PMUX_PINGRP_GEN1_I2C_SCL_PC4, + PMUX_PINGRP_DAP4_FS_PP4, + PMUX_PINGRP_DAP4_DIN_PP5, + PMUX_PINGRP_DAP4_DOUT_PP6, + PMUX_PINGRP_DAP4_SCLK_PP7, + PMUX_PINGRP_CLK3_OUT_PEE0, + PMUX_PINGRP_CLK3_REQ_PEE1, + PMUX_PINGRP_GMI_WP_N_PC7, + PMUX_PINGRP_GMI_IORDY_PI5, + PMUX_PINGRP_GMI_WAIT_PI7, + PMUX_PINGRP_GMI_ADV_N_PK0, + PMUX_PINGRP_GMI_CLK_PK1, + PMUX_PINGRP_GMI_CS0_N_PJ0, + PMUX_PINGRP_GMI_CS1_N_PJ2, + PMUX_PINGRP_GMI_CS2_N_PK3, + PMUX_PINGRP_GMI_CS3_N_PK4, + PMUX_PINGRP_GMI_CS4_N_PK2, + PMUX_PINGRP_GMI_CS6_N_PI3, + PMUX_PINGRP_GMI_CS7_N_PI6, + PMUX_PINGRP_GMI_AD0_PG0, + PMUX_PINGRP_GMI_AD1_PG1, + PMUX_PINGRP_GMI_AD2_PG2, + PMUX_PINGRP_GMI_AD3_PG3, + PMUX_PINGRP_GMI_AD4_PG4, + PMUX_PINGRP_GMI_AD5_PG5, + PMUX_PINGRP_GMI_AD6_PG6, + PMUX_PINGRP_GMI_AD7_PG7, + PMUX_PINGRP_GMI_AD8_PH0, + PMUX_PINGRP_GMI_AD9_PH1, + PMUX_PINGRP_GMI_AD10_PH2, + PMUX_PINGRP_GMI_AD11_PH3, + PMUX_PINGRP_GMI_AD12_PH4, + PMUX_PINGRP_GMI_AD13_PH5, + PMUX_PINGRP_GMI_AD14_PH6, + PMUX_PINGRP_GMI_AD15_PH7, + PMUX_PINGRP_GMI_A16_PJ7, + PMUX_PINGRP_GMI_A17_PB0, + PMUX_PINGRP_GMI_A18_PB1, + PMUX_PINGRP_GMI_A19_PK7, + PMUX_PINGRP_GMI_WR_N_PI0, + PMUX_PINGRP_GMI_OE_N_PI1, + PMUX_PINGRP_GMI_DQS_PI2, + PMUX_PINGRP_GMI_RST_N_PI4, + PMUX_PINGRP_GEN2_I2C_SCL_PT5, + PMUX_PINGRP_GEN2_I2C_SDA_PT6, + PMUX_PINGRP_SDMMC4_CLK_PCC4, + PMUX_PINGRP_SDMMC4_CMD_PT7, + PMUX_PINGRP_SDMMC4_DAT0_PAA0, + PMUX_PINGRP_SDMMC4_DAT1_PAA1, + PMUX_PINGRP_SDMMC4_DAT2_PAA2, + PMUX_PINGRP_SDMMC4_DAT3_PAA3, + PMUX_PINGRP_SDMMC4_DAT4_PAA4, + PMUX_PINGRP_SDMMC4_DAT5_PAA5, + PMUX_PINGRP_SDMMC4_DAT6_PAA6, + PMUX_PINGRP_SDMMC4_DAT7_PAA7, + PMUX_PINGRP_SDMMC4_RST_N_PCC3, + PMUX_PINGRP_CAM_MCLK_PCC0, + PMUX_PINGRP_PCC1, + PMUX_PINGRP_PBB0, + PMUX_PINGRP_CAM_I2C_SCL_PBB1, + PMUX_PINGRP_CAM_I2C_SDA_PBB2, + PMUX_PINGRP_PBB3, + PMUX_PINGRP_PBB4, + PMUX_PINGRP_PBB5, + PMUX_PINGRP_PBB6, + PMUX_PINGRP_PBB7, + PMUX_PINGRP_PCC2, + PMUX_PINGRP_JTAG_RTCK_PU7, + PMUX_PINGRP_PWR_I2C_SCL_PZ6, + PMUX_PINGRP_PWR_I2C_SDA_PZ7, + PMUX_PINGRP_KB_ROW0_PR0, + PMUX_PINGRP_KB_ROW1_PR1, + PMUX_PINGRP_KB_ROW2_PR2, + PMUX_PINGRP_KB_ROW3_PR3, + PMUX_PINGRP_KB_ROW4_PR4, + PMUX_PINGRP_KB_ROW5_PR5, + PMUX_PINGRP_KB_ROW6_PR6, + PMUX_PINGRP_KB_ROW7_PR7, + PMUX_PINGRP_KB_ROW8_PS0, + PMUX_PINGRP_KB_ROW9_PS1, + PMUX_PINGRP_KB_ROW10_PS2, + PMUX_PINGRP_KB_ROW11_PS3, + PMUX_PINGRP_KB_ROW12_PS4, + PMUX_PINGRP_KB_ROW13_PS5, + PMUX_PINGRP_KB_ROW14_PS6, + PMUX_PINGRP_KB_ROW15_PS7, + PMUX_PINGRP_KB_COL0_PQ0, + PMUX_PINGRP_KB_COL1_PQ1, + PMUX_PINGRP_KB_COL2_PQ2, + PMUX_PINGRP_KB_COL3_PQ3, + PMUX_PINGRP_KB_COL4_PQ4, + PMUX_PINGRP_KB_COL5_PQ5, + PMUX_PINGRP_KB_COL6_PQ6, + PMUX_PINGRP_KB_COL7_PQ7, + PMUX_PINGRP_CLK_32K_OUT_PA0, + PMUX_PINGRP_SYS_CLK_REQ_PZ5, + PMUX_PINGRP_CORE_PWR_REQ, + PMUX_PINGRP_CPU_PWR_REQ, + PMUX_PINGRP_PWR_INT_N, + PMUX_PINGRP_CLK_32K_IN, + PMUX_PINGRP_OWR, + PMUX_PINGRP_DAP1_FS_PN0, + PMUX_PINGRP_DAP1_DIN_PN1, + PMUX_PINGRP_DAP1_DOUT_PN2, + PMUX_PINGRP_DAP1_SCLK_PN3, + PMUX_PINGRP_CLK1_REQ_PEE2, + PMUX_PINGRP_CLK1_OUT_PW4, + PMUX_PINGRP_SPDIF_IN_PK6, + PMUX_PINGRP_SPDIF_OUT_PK5, + PMUX_PINGRP_DAP2_FS_PA2, + PMUX_PINGRP_DAP2_DIN_PA4, + PMUX_PINGRP_DAP2_DOUT_PA5, + PMUX_PINGRP_DAP2_SCLK_PA3, + PMUX_PINGRP_SPI2_MOSI_PX0, + PMUX_PINGRP_SPI2_MISO_PX1, + PMUX_PINGRP_SPI2_CS0_N_PX3, + PMUX_PINGRP_SPI2_SCK_PX2, + PMUX_PINGRP_SPI1_MOSI_PX4, + PMUX_PINGRP_SPI1_SCK_PX5, + PMUX_PINGRP_SPI1_CS0_N_PX6, + PMUX_PINGRP_SPI1_MISO_PX7, + PMUX_PINGRP_SPI2_CS1_N_PW2, + PMUX_PINGRP_SPI2_CS2_N_PW3, + PMUX_PINGRP_SDMMC3_CLK_PA6, + PMUX_PINGRP_SDMMC3_CMD_PA7, + PMUX_PINGRP_SDMMC3_DAT0_PB7, + PMUX_PINGRP_SDMMC3_DAT1_PB6, + PMUX_PINGRP_SDMMC3_DAT2_PB5, + PMUX_PINGRP_SDMMC3_DAT3_PB4, + PMUX_PINGRP_SDMMC3_DAT4_PD1, + PMUX_PINGRP_SDMMC3_DAT5_PD0, + PMUX_PINGRP_SDMMC3_DAT6_PD3, + PMUX_PINGRP_SDMMC3_DAT7_PD4, + PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0, + PMUX_PINGRP_PEX_L0_RST_N_PDD1, + PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2, + PMUX_PINGRP_PEX_WAKE_N_PDD3, + PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4, + PMUX_PINGRP_PEX_L1_RST_N_PDD5, + PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6, + PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7, + PMUX_PINGRP_PEX_L2_RST_N_PCC6, + PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7, + PMUX_PINGRP_HDMI_CEC_PEE3, + PMUX_PINGRP_COUNT, }; -enum pdrive_pingrp { - PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */ - PDRIVE_PINGROUP_AO2, - PDRIVE_PINGROUP_AT1, - PDRIVE_PINGROUP_AT2, - PDRIVE_PINGROUP_AT3, - PDRIVE_PINGROUP_AT4, - PDRIVE_PINGROUP_AT5, - PDRIVE_PINGROUP_CDEV1, - PDRIVE_PINGROUP_CDEV2, - PDRIVE_PINGROUP_CSUS, - PDRIVE_PINGROUP_DAP1, - PDRIVE_PINGROUP_DAP2, - PDRIVE_PINGROUP_DAP3, - PDRIVE_PINGROUP_DAP4, - PDRIVE_PINGROUP_DBG, - PDRIVE_PINGROUP_LCD1, - PDRIVE_PINGROUP_LCD2, - PDRIVE_PINGROUP_SDIO2, - PDRIVE_PINGROUP_SDIO3, - PDRIVE_PINGROUP_SPI, - PDRIVE_PINGROUP_UAA, - PDRIVE_PINGROUP_UAB, - PDRIVE_PINGROUP_UART2, - PDRIVE_PINGROUP_UART3, - PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */ - PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */ - PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */ - PDRIVE_PINGROUP_DDC, - PDRIVE_PINGROUP_GMA, - PDRIVE_PINGROUP_GMB, - PDRIVE_PINGROUP_GMC, - PDRIVE_PINGROUP_GMD, - PDRIVE_PINGROUP_GME, - PDRIVE_PINGROUP_GMF, - PDRIVE_PINGROUP_GMG, - PDRIVE_PINGROUP_GMH, - PDRIVE_PINGROUP_OWR, - PDRIVE_PINGROUP_UAD, - PDRIVE_PINGROUP_GPV, - PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */ - PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */ - PDRIVE_PINGROUP_COUNT, +enum pmux_drvgrp { + PMUX_DRVGRP_AO1, + PMUX_DRVGRP_AO2, + PMUX_DRVGRP_AT1, + PMUX_DRVGRP_AT2, + PMUX_DRVGRP_AT3, + PMUX_DRVGRP_AT4, + PMUX_DRVGRP_AT5, + PMUX_DRVGRP_CDEV1, + PMUX_DRVGRP_CDEV2, + PMUX_DRVGRP_CSUS, + PMUX_DRVGRP_DAP1, + PMUX_DRVGRP_DAP2, + PMUX_DRVGRP_DAP3, + PMUX_DRVGRP_DAP4, + PMUX_DRVGRP_DBG, + PMUX_DRVGRP_LCD1, + PMUX_DRVGRP_LCD2, + PMUX_DRVGRP_SDIO2, + PMUX_DRVGRP_SDIO3, + PMUX_DRVGRP_SPI, + PMUX_DRVGRP_UAA, + PMUX_DRVGRP_UAB, + PMUX_DRVGRP_UART2, + PMUX_DRVGRP_UART3, + PMUX_DRVGRP_VI1, + PMUX_DRVGRP_SDIO1 = (0x84 / 4), + PMUX_DRVGRP_CRT = (0x90 / 4), + PMUX_DRVGRP_DDC, + PMUX_DRVGRP_GMA, + PMUX_DRVGRP_GMB, + PMUX_DRVGRP_GMC, + PMUX_DRVGRP_GMD, + PMUX_DRVGRP_GME, + PMUX_DRVGRP_GMF, + PMUX_DRVGRP_GMG, + PMUX_DRVGRP_GMH, + PMUX_DRVGRP_OWR, + PMUX_DRVGRP_UDA, + PMUX_DRVGRP_GPV, + PMUX_DRVGRP_DEV3, + PMUX_DRVGRP_CEC = (0xd0 / 4), + PMUX_DRVGRP_COUNT, }; -/* - * Functions which can be assigned to each of the pin groups. The values here - * bear no relation to the values programmed into pinmux registers and are - * purely a convenience. The translation is done through a table search. - */ enum pmux_func { - PMUX_FUNC_AHB_CLK, - PMUX_FUNC_APB_CLK, - PMUX_FUNC_AUDIO_SYNC, + PMUX_FUNC_BLINK, + PMUX_FUNC_CEC, + PMUX_FUNC_CLK_12M_OUT, + PMUX_FUNC_CLK_32K_IN, + PMUX_FUNC_CORE_PWR_REQ, + PMUX_FUNC_CPU_PWR_REQ, PMUX_FUNC_CRT, - PMUX_FUNC_DAP1, - PMUX_FUNC_DAP2, - PMUX_FUNC_DAP3, - PMUX_FUNC_DAP4, - PMUX_FUNC_DAP5, - PMUX_FUNC_DISPA, - PMUX_FUNC_DISPB, - PMUX_FUNC_EMC_TEST0_DLL, - PMUX_FUNC_EMC_TEST1_DLL, + PMUX_FUNC_DAP, + PMUX_FUNC_DDR, + PMUX_FUNC_DEV3, + PMUX_FUNC_DISPLAYA, + PMUX_FUNC_DISPLAYB, + PMUX_FUNC_DTV, + PMUX_FUNC_EXTPERIPH1, + PMUX_FUNC_EXTPERIPH2, + PMUX_FUNC_EXTPERIPH3, PMUX_FUNC_GMI, - PMUX_FUNC_GMI_INT, + PMUX_FUNC_GMI_ALT, + PMUX_FUNC_HDA, + PMUX_FUNC_HDCP, PMUX_FUNC_HDMI, + PMUX_FUNC_HSI, PMUX_FUNC_I2C1, PMUX_FUNC_I2C2, PMUX_FUNC_I2C3, - PMUX_FUNC_IDE, + PMUX_FUNC_I2C4, + PMUX_FUNC_I2CPWR, + PMUX_FUNC_I2S0, + PMUX_FUNC_I2S1, + PMUX_FUNC_I2S2, + PMUX_FUNC_I2S3, + PMUX_FUNC_I2S4, + PMUX_FUNC_INVALID, PMUX_FUNC_KBC, PMUX_FUNC_MIO, - PMUX_FUNC_MIPI_HS, PMUX_FUNC_NAND, - PMUX_FUNC_OSC, + PMUX_FUNC_NAND_ALT, PMUX_FUNC_OWR, PMUX_FUNC_PCIE, - PMUX_FUNC_PLLA_OUT, - PMUX_FUNC_PLLC_OUT1, - PMUX_FUNC_PLLM_OUT1, - PMUX_FUNC_PLLP_OUT2, - PMUX_FUNC_PLLP_OUT3, - PMUX_FUNC_PLLP_OUT4, - PMUX_FUNC_PWM, - PMUX_FUNC_PWR_INTR, - PMUX_FUNC_PWR_ON, + PMUX_FUNC_PWM0, + PMUX_FUNC_PWM1, + PMUX_FUNC_PWM2, + PMUX_FUNC_PWM3, + PMUX_FUNC_PWR_INT_N, PMUX_FUNC_RTCK, + PMUX_FUNC_SATA, PMUX_FUNC_SDMMC1, PMUX_FUNC_SDMMC2, PMUX_FUNC_SDMMC3, PMUX_FUNC_SDMMC4, - PMUX_FUNC_SFLASH, PMUX_FUNC_SPDIF, PMUX_FUNC_SPI1, PMUX_FUNC_SPI2, PMUX_FUNC_SPI2_ALT, PMUX_FUNC_SPI3, PMUX_FUNC_SPI4, + PMUX_FUNC_SPI5, + PMUX_FUNC_SPI6, + PMUX_FUNC_SYSCLK, + PMUX_FUNC_TEST, PMUX_FUNC_TRACE, - PMUX_FUNC_TWC, PMUX_FUNC_UARTA, PMUX_FUNC_UARTB, PMUX_FUNC_UARTC, PMUX_FUNC_UARTD, PMUX_FUNC_UARTE, PMUX_FUNC_ULPI, - PMUX_FUNC_VI, - PMUX_FUNC_VI_SENSOR_CLK, - PMUX_FUNC_XIO, - PMUX_FUNC_BLINK, - PMUX_FUNC_CEC, - PMUX_FUNC_CLK12, - PMUX_FUNC_DAP, - PMUX_FUNC_DAPSDMMC2, - PMUX_FUNC_DDR, - PMUX_FUNC_DEV3, - PMUX_FUNC_DTV, - PMUX_FUNC_VI_ALT1, - PMUX_FUNC_VI_ALT2, - PMUX_FUNC_VI_ALT3, - PMUX_FUNC_EMC_DLL, - PMUX_FUNC_EXTPERIPH1, - PMUX_FUNC_EXTPERIPH2, - PMUX_FUNC_EXTPERIPH3, - PMUX_FUNC_GMI_ALT, - PMUX_FUNC_HDA, - PMUX_FUNC_HSI, - PMUX_FUNC_I2C4, - PMUX_FUNC_I2C5, - PMUX_FUNC_I2CPWR, - PMUX_FUNC_I2S0, - PMUX_FUNC_I2S1, - PMUX_FUNC_I2S2, - PMUX_FUNC_I2S3, - PMUX_FUNC_I2S4, - PMUX_FUNC_NAND_ALT, - PMUX_FUNC_POPSDIO4, - PMUX_FUNC_POPSDMMC4, - PMUX_FUNC_PWM0, - PMUX_FUNC_PWM1, - PMUX_FUNC_PWM2, - PMUX_FUNC_PWM3, - PMUX_FUNC_SATA, - PMUX_FUNC_SPI5, - PMUX_FUNC_SPI6, - PMUX_FUNC_SYSCLK, PMUX_FUNC_VGP1, PMUX_FUNC_VGP2, PMUX_FUNC_VGP3, PMUX_FUNC_VGP4, PMUX_FUNC_VGP5, PMUX_FUNC_VGP6, - PMUX_FUNC_CLK_12M_OUT, - PMUX_FUNC_HDCP, - PMUX_FUNC_TEST, - PMUX_FUNC_CORE_PWR_REQ, - PMUX_FUNC_CPU_PWR_REQ, - PMUX_FUNC_PWR_INT_N, - PMUX_FUNC_CLK_32K_IN, - PMUX_FUNC_SAFE, - - PMUX_FUNC_MAX, - - PMUX_FUNC_RSVD1 = 0x8000, - PMUX_FUNC_RSVD2 = 0x8001, - PMUX_FUNC_RSVD3 = 0x8002, - PMUX_FUNC_RSVD4 = 0x8003, -}; - -/* return 1 if a pmux_func is in range */ -#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \ - || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4))) - -/* return 1 if a pingrp is in range */ -#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT)) - -/* The pullup/pulldown state of a pin group */ -enum pmux_pull { - PMUX_PULL_NORMAL = 0, - PMUX_PULL_DOWN, - PMUX_PULL_UP, -}; -/* return 1 if a pin_pupd_is in range */ -#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \ - ((pupd) <= PMUX_PULL_UP)) - -/* Defines whether a pin group is tristated or in normal operation */ -enum pmux_tristate { - PMUX_TRI_NORMAL = 0, - PMUX_TRI_TRISTATE = 1, -}; -/* return 1 if a pin_tristate_is in range */ -#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \ - && ((tristate) <= PMUX_TRI_TRISTATE)) - -enum pmux_pin_io { - PMUX_PIN_OUTPUT = 0, - PMUX_PIN_INPUT = 1, -}; -/* return 1 if a pin_io_is in range */ -#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \ - ((io) <= PMUX_PIN_INPUT)) - -enum pmux_pin_lock { - PMUX_PIN_LOCK_DEFAULT = 0, - PMUX_PIN_LOCK_DISABLE, - PMUX_PIN_LOCK_ENABLE, -}; -/* return 1 if a pin_lock is in range */ -#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \ - ((lock) <= PMUX_PIN_LOCK_ENABLE)) - -enum pmux_pin_od { - PMUX_PIN_OD_DEFAULT = 0, - PMUX_PIN_OD_DISABLE, - PMUX_PIN_OD_ENABLE, -}; -/* return 1 if a pin_od is in range */ -#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \ - ((od) <= PMUX_PIN_OD_ENABLE)) - -enum pmux_pin_ioreset { - PMUX_PIN_IO_RESET_DEFAULT = 0, - PMUX_PIN_IO_RESET_DISABLE, - PMUX_PIN_IO_RESET_ENABLE, -}; -/* return 1 if a pin_ioreset_is in range */ -#define pmux_pin_ioreset_isvalid(ioreset) \ - (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \ - ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE)) - -/* Available power domains used by pin groups */ -enum pmux_vddio { - PMUX_VDDIO_BB = 0, - PMUX_VDDIO_LCD, - PMUX_VDDIO_VI, - PMUX_VDDIO_UART, - PMUX_VDDIO_DDR, - PMUX_VDDIO_NAND, - PMUX_VDDIO_SYS, - PMUX_VDDIO_AUDIO, - PMUX_VDDIO_SD, - PMUX_VDDIO_CAM, - PMUX_VDDIO_GMI, - PMUX_VDDIO_PEXCTL, - PMUX_VDDIO_SDMMC1, - PMUX_VDDIO_SDMMC3, - PMUX_VDDIO_SDMMC4, - - PMUX_VDDIO_NONE -}; - -#define PGRP_SLWF_NONE -1 -#define PGRP_SLWF_MAX 3 -#define PGRP_SLWR_NONE PGRP_SLWF_NONE -#define PGRP_SLWR_MAX PGRP_SLWF_MAX - -#define PGRP_DRVUP_NONE -1 -#define PGRP_DRVUP_MAX 127 -#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE -#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX - -/* return 1 if a padgrp is in range */ -#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT)) - -/* return 1 if a slew-rate rising/falling edge value is in range */ -#define pmux_pad_slw_isvalid(slw) (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)) - -/* return 1 if a driver output pull-up/down strength code value is in range */ -#define pmux_pad_drv_isvalid(drv) (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)) - -/* return 1 if a low-power mode value is in range */ -#define pmux_pad_lpmd_isvalid(lpm) (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)) - -/* Defines a pin group cfg's low-power mode select */ -enum pgrp_lpmd { - PGRP_LPMD_X8 = 0, - PGRP_LPMD_X4, - PGRP_LPMD_X2, - PGRP_LPMD_X, - PGRP_LPMD_NONE = -1, -}; - -/* Defines whether a pin group cfg's schmidt is enabled or not */ -enum pgrp_schmt { - PGRP_SCHMT_DISABLE = 0, - PGRP_SCHMT_ENABLE = 1, -}; - -/* Defines whether a pin group cfg's high-speed mode is enabled or not */ -enum pgrp_hsm { - PGRP_HSM_DISABLE = 0, - PGRP_HSM_ENABLE = 1, -}; - -/* - * This defines the configuration for a pin group's pad control config - */ -struct padctrl_config { - enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */ - int slwf; /* falling edge slew */ - int slwr; /* rising edge slew */ - int drvup; /* pull-up drive strength */ - int drvdn; /* pull-down drive strength */ - enum pgrp_lpmd lpmd; /* low-power mode selection */ - enum pgrp_schmt schmt; /* schmidt enable */ - enum pgrp_hsm hsm; /* high-speed mode enable */ -}; - -/* t30 pin drive group and pin mux registers */ -#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2) -#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \ - PDRIVE_PINGROUP_COUNT) -struct pmux_tri_ctlr { - uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ - uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */ - uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ - uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */ - uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */ - uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */ - uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ - - uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */ - - uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */ - uint pmt_reserved5[PMUX_OFFSET]; - uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */ -}; - -/* - * This defines the configuration for a pin, including the function assigned, - * pull up/down settings and tristate settings. Having set up one of these - * you can call pinmux_config_pingroup() to configure a pin in one step. Also - * available is pinmux_config_table() to configure a list of pins. - */ -struct pingroup_config { - enum pmux_pingrp pingroup; /* pin group PINGRP_... */ - enum pmux_func func; /* function to assign FUNC_... */ - enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ - enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ - enum pmux_pin_io io; /* input or output PMUX_PIN_... */ - enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ - enum pmux_pin_od od; /* open-drain or push-pull driver */ - enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ + PMUX_FUNC_VI, + PMUX_FUNC_VI_ALT1, + PMUX_FUNC_VI_ALT2, + PMUX_FUNC_VI_ALT3, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_RSVD4, + PMUX_FUNC_COUNT, }; -/* Set a pin group to tristate */ -void pinmux_tristate_enable(enum pmux_pingrp pin); - -/* Set a pin group to normal (non tristate) */ -void pinmux_tristate_disable(enum pmux_pingrp pin); - -/* Set the pull up/down feature for a pin group */ -void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); - -/* Set the mux function for a pin group */ -void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); - -/* Set the complete configuration for a pin group */ -void pinmux_config_pingroup(struct pingroup_config *config); - -/* Set a pin group to tristate or normal */ -void pinmux_set_tristate(enum pmux_pingrp pin, int enable); - -/* Set a pin group as input or output */ -void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); - -/** - * Configure a list of pin groups - * - * @param config List of config items - * @param len Number of config items in list - */ -void pinmux_config_table(struct pingroup_config *config, int len); - -/* Set a group of pins from a table */ -void pinmux_init(void); - -/** - * Set the GP pad configs - * - * @param config List of config items - * @param len Number of config items in list - */ -void padgrp_config_table(struct padctrl_config *config, int len); +#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC +#define TEGRA_PMX_HAS_DRVGRPS +#include <asm/arch-tegra/pinmux.h> -#endif /* _TEGRA30_PINMUX_H_ */ +#endif /* _TEGRA30_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/usb.h b/arch/arm/include/asm/arch-tegra30/usb.h deleted file mode 100644 index ab9b760b02c..00000000000 --- a/arch/arm/include/asm/arch-tegra30/usb.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2013 NVIDIA Corporation - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA30_USB_H_ -#define _TEGRA30_USB_H_ - -/* USB Controller (USBx_CONTROLLER_) regs */ -struct usb_ctlr { - /* 0x000 */ - uint id; - uint reserved0; - uint host; - uint device; - - /* 0x010 */ - uint txbuf; - uint rxbuf; - uint reserved1[2]; - - /* 0x020 */ - uint reserved2[56]; - - /* 0x100 */ - u16 cap_length; - u16 hci_version; - uint hcs_params; - uint hcc_params; - uint reserved3[5]; - - /* 0x120 */ - uint dci_version; - uint dcc_params; - uint reserved4[2]; - - /* 0x130 */ - uint usb_cmd; - uint usb_sts; - uint usb_intr; - uint frindex; - - /* 0x140 */ - uint reserved5; - uint periodic_list_base; - uint async_list_addr; - uint reserved5_1; - - /* 0x150 */ - uint burst_size; - uint tx_fill_tuning; - uint reserved6; - uint icusb_ctrl; - - /* 0x160 */ - uint ulpi_viewport; - uint reserved7[3]; - - /* 0x170 */ - uint reserved; - uint port_sc1; - uint reserved8[6]; - - /* 0x190 */ - uint reserved9[8]; - - /* 0x1b0 */ - uint reserved10; - uint hostpc1_devlc; - uint reserved10_1[2]; - - /* 0x1c0 */ - uint reserved10_2[4]; - - /* 0x1d0 */ - uint reserved10_3[4]; - - /* 0x1e0 */ - uint reserved10_4[4]; - - /* 0x1f0 */ - uint reserved10_5; - uint otgsc; - uint usb_mode; - uint reserved10_6; - - /* 0x200 */ - uint endpt_nak; - uint endpt_nak_enable; - uint endpt_setup_stat; - uint reserved11_1[0x7D]; - - /* 0x400 */ - uint susp_ctrl; - uint phy_vbus_sensors; - uint phy_vbus_wakeup_id; - uint phy_alt_vbus_sys; - - /* 0x410 */ - uint usb1_legacy_ctrl; - uint reserved12[3]; - - /* 0x420 */ - uint reserved13[56]; - - /* 0x500 */ - uint reserved14[64 * 3]; - - /* 0x800 */ - uint utmip_pll_cfg0; - uint utmip_pll_cfg1; - uint utmip_xcvr_cfg0; - uint utmip_bias_cfg0; - - /* 0x810 */ - uint utmip_hsrx_cfg0; - uint utmip_hsrx_cfg1; - uint utmip_fslsrx_cfg0; - uint utmip_fslsrx_cfg1; - - /* 0x820 */ - uint utmip_tx_cfg0; - uint utmip_misc_cfg0; - uint utmip_misc_cfg1; - uint utmip_debounce_cfg0; - - /* 0x830 */ - uint utmip_bat_chrg_cfg0; - uint utmip_spare_cfg0; - uint utmip_xcvr_cfg1; - uint utmip_bias_cfg1; -}; - -/* USB2_IF_ULPI_TIMING_CTRL_0 */ -#define ULPI_OUTPUT_PINMUX_BYP (1 << 10) -#define ULPI_CLKOUT_PINMUX_BYP (1 << 11) - -/* USB2_IF_ULPI_TIMING_CTRL_1 */ -#define ULPI_DATA_TRIMMER_LOAD (1 << 0) -#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) -#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) -#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) -#define ULPI_DIR_TRIMMER_LOAD (1 << 24) -#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) - -/* USB2D_HOSTPC1_DEVLC_0 */ -#define PTS_SHIFT 29 -#define PTS_MASK (0x7U << PTS_SHIFT) - -#define STS (1 << 28) -#endif /* _TEGRA30_USB_H_ */ |