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-rw-r--r--arch/arm/include/asm/arch-at91/at91_common.h1
-rw-r--r--arch/arm/include/asm/arch-at91/at91_dbu.h41
-rw-r--r--arch/arm/include/asm/arch-at91/at91_eefc.h51
-rw-r--r--arch/arm/include/asm/arch-at91/at91_gpbr.h45
-rw-r--r--arch/arm/include/asm/arch-at91/at91_pit.h2
-rw-r--r--arch/arm/include/asm/arch-at91/at91_rtt.h36
-rw-r--r--arch/arm/include/asm/arch-at91/at91sam9260.h18
-rw-r--r--arch/arm/include/asm/arch-at91/clk.h5
-rw-r--r--arch/arm/include/asm/arch-at91/hardware.h1
-rw-r--r--arch/arm/include/asm/arch-mb86r0x/asm-offsets.h74
-rw-r--r--arch/arm/include/asm/arch-mb86r0x/hardware.h31
-rw-r--r--arch/arm/include/asm/arch-mb86r0x/mb86r0x.h573
-rw-r--r--arch/arm/include/asm/arch-orion5x/cpu.h2
-rw-r--r--arch/arm/include/asm/arch-s5pc1xx/clk.h5
-rw-r--r--arch/arm/include/asm/arch-s5pc1xx/cpu.h39
-rw-r--r--arch/arm/include/asm/arch-s5pc1xx/gpio.h172
-rw-r--r--arch/arm/include/asm/arch-s5pc1xx/mmc.h2
-rw-r--r--arch/arm/include/asm/arch-s5pc1xx/pwm.h12
18 files changed, 1000 insertions, 110 deletions
diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h
index 01840eede4..0067190a20 100644
--- a/arch/arm/include/asm/arch-at91/at91_common.h
+++ b/arch/arm/include/asm/arch-at91/at91_common.h
@@ -27,6 +27,7 @@
void at91_can_hw_init(void);
void at91_macb_hw_init(void);
+void at91_mci_hw_init(void);
void at91_serial_hw_init(void);
void at91_serial0_hw_init(void);
void at91_serial1_hw_init(void);
diff --git a/arch/arm/include/asm/arch-at91/at91_dbu.h b/arch/arm/include/asm/arch-at91/at91_dbu.h
new file mode 100644
index 0000000000..3429293535
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/at91_dbu.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ *
+ * Debug Unit
+ * Based on AT91SAM9XE datasheet
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_DBU_H
+#define AT91_DBU_H
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_dbu {
+ u32 cr; /* Control Register WO */
+ u32 mr; /* Mode Register RW */
+ u32 ier; /* Interrupt Enable Register WO */
+ u32 idr; /* Interrupt Disable Register WO */
+ u32 imr; /* Interrupt Mask Register RO */
+ u32 sr; /* Status Register RO */
+ u32 rhr; /* Receive Holding Register RO */
+ u32 thr; /* Transmit Holding Register WO */
+ u32 brgr; /* Baud Rate Generator Register RW */
+ u32 res1[7];/* 0x0024 - 0x003C Reserved */
+ u32 cidr; /* Chip ID Register RO */
+ u32 exid; /* Chip ID Extension Register RO */
+ u32 fnr; /* Force NTRST Register RW */
+} at91_dbu_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_DBU_CID_ARCH_MASK 0x0ff00000
+#define AT91_DBU_CID_ARCH_9xx 0x01900000
+#define AT91_DBU_CID_ARCH_9XExx 0x02900000
+
+#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_eefc.h b/arch/arm/include/asm/arch-at91/at91_eefc.h
new file mode 100644
index 0000000000..d45b3deca4
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/at91_eefc.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ *
+ * Enhanced Embedded Flash Controller
+ * Based on AT91SAM9XE datasheet
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_EEFC_H
+#define AT91_EEFC_H
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_eefc {
+ u32 fmr; /* Flash Mode Register RW */
+ u32 fcr; /* Flash Command Register WO */
+ u32 fsr; /* Flash Status Register RO */
+ u32 frr; /* Flash Result Register RO */
+} at91_eefc_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_EEFC_FMR_FWS_MASK 0x00000f00
+#define AT91_EEFC_FMR_FRDY_BIT 0x00000001
+
+#define AT91_EEFC_FCR_KEY 0x5a000000
+#define AT91_EEFC_FCR_FARG_MASK 0x00ffff00
+#define AT91_EEFC_FCR_FARG_SHIFT 8
+#define AT91_EEFC_FCR_FCMD_GETD 0x0
+#define AT91_EEFC_FCR_FCMD_WP 0x1
+#define AT91_EEFC_FCR_FCMD_WPL 0x2
+#define AT91_EEFC_FCR_FCMD_EWP 0x3
+#define AT91_EEFC_FCR_FCMD_EWPL 0x4
+#define AT91_EEFC_FCR_FCMD_EA 0x5
+#define AT91_EEFC_FCR_FCMD_SLB 0x8
+#define AT91_EEFC_FCR_FCMD_CLB 0x9
+#define AT91_EEFC_FCR_FCMD_GLB 0xA
+#define AT91_EEFC_FCR_FCMD_SGPB 0xB
+#define AT91_EEFC_FCR_FCMD_CGPB 0xC
+#define AT91_EEFC_FCR_FCMD_GGPB 0xD
+
+#define AT91_EEFC_FSR_FRDY 1
+#define AT91_EEFC_FSR_FCMDE 2
+#define AT91_EEFC_FSR_FLOCKE 4
+
+#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_gpbr.h b/arch/arm/include/asm/arch-at91/at91_gpbr.h
new file mode 100644
index 0000000000..cf1d790dd9
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/at91_gpbr.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ *
+ * General Purpose Backup Registers
+ * Based on AT91SAM9XE datasheet
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_GPBR_H
+#define AT91_GPBR_H
+
+/*
+ * The Atmel AT91SAM9 series has a small resource of 4 nonvolatile
+ * 32 Bit registers (buffered by the Vbu power).
+ *
+ * Please consider carefully before using this resource for tasks
+ * that do not really need nonvolatile registers. Maybe you can
+ * store information in EEPROM or FLASH instead.
+ *
+ * However, if you use a GPBR please document its use here and
+ * reference the define in your code!
+ *
+ * known typical uses of the GPBRs:
+ * GPBR[0]: offset for RTT timekeeping (u-boot, kernel)
+ * GPBR[1]: unused
+ * GPBR[2]: unused
+ * GPBR[3]: bootcount (u-boot)
+ */
+#define AT91_GPBR_INDEX_TIMEOFF 0
+#define AT91_GPBR_INDEX_BOOTCOUNT 3
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_gpbr {
+ u32 reg[4];
+} at91_gpbr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_pit.h b/arch/arm/include/asm/arch-at91/at91_pit.h
index 5615a0206c..61aca79418 100644
--- a/arch/arm/include/asm/arch-at91/at91_pit.h
+++ b/arch/arm/include/asm/arch-at91/at91_pit.h
@@ -25,7 +25,7 @@ typedef struct at91_pit {
#define AT91_PIT_MR_IEN 0x02000000
#define AT91_PIT_MR_EN 0x01000000
-#define AT91_PIT_MR_PIV_MASK (x & 0x000fffff)
+#define AT91_PIT_MR_PIV_MASK(x) (x & 0x000fffff)
#define AT91_PIT_MR_PIV(x) (x & AT91_PIT_MR_PIV_MASK)
#ifdef CONFIG_AT91_LEGACY
diff --git a/arch/arm/include/asm/arch-at91/at91_rtt.h b/arch/arm/include/asm/arch-at91/at91_rtt.h
new file mode 100644
index 0000000000..e0253ef821
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/at91_rtt.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ *
+ * Real-time Timer
+ * Based on AT91SAM9XE datasheet
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RTT_H
+#define AT91_RTT_H
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_rtt {
+ u32 mr; /* Mode Register RW 0x00008000 */
+ u32 ar; /* Alarm Register RW 0xFFFFFFFF */
+ u32 vr; /* Value Register RO 0x00000000 */
+ u32 sr; /* Status Register RO 0x00000000 */
+} at91_rtt_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_RTT_MR_RTPRES 0x0000ffff
+#define AT91_RTT_MR_ALMIEN 0x00010000
+#define AT91_RTT_RTTINCIEN 0x00020000
+#define AT91_RTT_RTTRST 0x00040000
+
+#define AT91_RTT_SR_ALMS 0x00000001
+#define AT91_RTT_SR_RTTINC 0x00000002
+
+#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h
index ec04318036..cb34a94a3b 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9260.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9260.h
@@ -59,7 +59,15 @@
#define AT91_RTT_BASE 0xfffffd20
#define AT91_PIT_BASE 0xfffffd30
#define AT91_WDT_BASE 0xfffffd40
-#define AT91_GPR_BASE 0xfffffd50
+/*
+ * The AT91SAM9XE has the GPBRs at a different address than
+ * the AT91SAM9260/9G20.
+ */
+#ifdef CONFIG_AT91SAM9XE
+# define AT91_GPR_BASE 0xfffffd60
+#else
+# define AT91_GPR_BASE 0xfffffd50
+#endif
#ifdef CONFIG_AT91_LEGACY
@@ -140,10 +148,12 @@
/*
* Cpu Name
*/
-#if defined(CONFIG_AT91SAM9260)
-#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9260"
+#if defined(CONFIG_AT91SAM9XE)
+# define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9XE"
+#elif defined(CONFIG_AT91SAM9260)
+# define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9260"
#elif defined(CONFIG_AT91SAM9G20)
-#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G20"
+# define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G20"
#endif
#endif
diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h
index f642dd9958..457e6c9b2b 100644
--- a/arch/arm/include/asm/arch-at91/clk.h
+++ b/arch/arm/include/asm/arch-at91/clk.h
@@ -59,5 +59,10 @@ static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
return get_mck_clk_rate();
}
+static inline unsigned long get_mci_clk_rate(void)
+{
+ return get_mck_clk_rate();
+}
+
int at91_clock_init(unsigned long main_clock);
#endif /* __ASM_ARM_ARCH_CLK_H__ */
diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h
index 4ddb3155d7..9f732a738e 100644
--- a/arch/arm/include/asm/arch-at91/hardware.h
+++ b/arch/arm/include/asm/arch-at91/hardware.h
@@ -20,6 +20,7 @@
#include <asm/arch-at91/at91rm9200.h>
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
#include <asm/arch/at91sam9260.h>
+#define AT91_BASE_MCI AT91SAM9260_BASE_MCI
#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0
#define AT91_ID_UHP AT91SAM9260_ID_UHP
#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
diff --git a/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h b/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h
new file mode 100644
index 0000000000..0bc5279137
--- /dev/null
+++ b/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2010
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef ASM_OFFSETS_H
+#define ASM_OFFSETS_H
+
+/*
+ * Offset definitions for DDR controller
+ */
+#define DDR2_DRIC 0x00
+#define DDR2_DRIC1 0x02
+#define DDR2_DRIC2 0x04
+#define DDR2_DRCA 0x06
+#define DDR2_DRCM 0x08
+#define DDR2_DRCST1 0x0a
+#define DDR2_DRCST2 0x0c
+#define DDR2_DRCR 0x0e
+#define DDR2_DRCF 0x20
+#define DDR2_DRASR 0x30
+#define DDR2_DRIMS 0x50
+#define DDR2_DROS 0x60
+#define DDR2_DRIBSODT1 0x64
+#define DDR2_DROABA 0x70
+#define DDR2_DROBS 0x84
+
+/*
+ * Offset definitions Chip Control Module
+ */
+#define CCNT_CDCRC 0xec
+
+/*
+ * Offset definitions clock reset generator
+ */
+#define CRG_CRPR 0x00
+#define CRG_CRHA 0x18
+#define CRG_CRPA 0x1c
+#define CRG_CRPB 0x20
+#define CRG_CRHB 0x24
+#define CRG_CRAM 0x28
+
+/*
+ * Offset definitions External bus interface
+ */
+#define MEMC_MCFMODE0 0x00
+#define MEMC_MCFMODE2 0x08
+#define MEMC_MCFMODE4 0x10
+#define MEMC_MCFTIM0 0x20
+#define MEMC_MCFTIM2 0x28
+#define MEMC_MCFTIM4 0x30
+#define MEMC_MCFAREA0 0x40
+#define MEMC_MCFAREA2 0x48
+#define MEMC_MCFAREA4 0x50
+
+#endif /* ASM_OFFSETS_H */
diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h
new file mode 100644
index 0000000000..d1e57c0349
--- /dev/null
+++ b/arch/arm/include/asm/arch-mb86r0x/hardware.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007
+ *
+ * Author : Carsten Schneider, mycable GmbH
+ * <cs@mycable.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <asm/arch/mb86r0x.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
new file mode 100644
index 0000000000..36a28b7af3
--- /dev/null
+++ b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
@@ -0,0 +1,573 @@
+/*
+ * (C) Copyright 2007
+ *
+ * mb86r0x definitions
+ *
+ * Author : Carsten Schneider, mycable GmbH
+ * <cs@mycable.de>
+ *
+ * (C) Copyright 2010
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MB86R0X_H
+#define MB86R0X_H
+
+#ifndef __ASSEMBLY__
+
+/* GPIO registers */
+struct mb86r0x_gpio {
+ uint32_t gpdr0;
+ uint32_t gpdr1;
+ uint32_t gpdr2;
+ uint32_t res;
+ uint32_t gpddr0;
+ uint32_t gpddr1;
+ uint32_t gpddr2;
+};
+
+/* PWM registers */
+struct mb86r0x_pwm {
+ uint32_t bcr;
+ uint32_t tpr;
+ uint32_t pr;
+ uint32_t dr;
+ uint32_t cr;
+ uint32_t sr;
+ uint32_t ccr;
+ uint32_t ir;
+};
+
+/* The mb86r0x chip control (CCNT) register set. */
+struct mb86r0x_ccnt {
+ uint32_t ccid;
+ uint32_t csrst;
+ uint32_t pad0[2];
+ uint32_t cist;
+ uint32_t cistm;
+ uint32_t cgpio_ist;
+ uint32_t cgpio_istm;
+ uint32_t cgpio_ip;
+ uint32_t cgpio_im;
+ uint32_t caxi_bw;
+ uint32_t caxi_ps;
+ uint32_t cmux_md;
+ uint32_t cex_pin_st;
+ uint32_t cmlb;
+ uint32_t pad1[1];
+ uint32_t cusb;
+ uint32_t pad2[41];
+ uint32_t cbsc;
+ uint32_t cdcrc;
+ uint32_t cmsr0;
+ uint32_t cmsr1;
+ uint32_t pad3[2];
+};
+
+/* The mb86r0x clock reset generator */
+struct mb86r0x_crg {
+ uint32_t crpr;
+ uint32_t pad0;
+ uint32_t crwr;
+ uint32_t crsr;
+ uint32_t crda;
+ uint32_t crdb;
+ uint32_t crha;
+ uint32_t crpa;
+ uint32_t crpb;
+ uint32_t crhb;
+ uint32_t cram;
+};
+
+/* The mb86r0x timer */
+struct mb86r0x_timer {
+ uint32_t load;
+ uint32_t value;
+ uint32_t control;
+ uint32_t intclr;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t bgload;
+};
+
+/* mb86r0x gdc display controller */
+struct mb86r0x_gdc_dsp {
+ /* Display settings */
+ uint32_t dcm0;
+ uint16_t pad00;
+ uint16_t htp;
+ uint16_t hdp;
+ uint16_t hdb;
+ uint16_t hsp;
+ uint8_t hsw;
+ uint8_t vsw;
+ uint16_t pad01;
+ uint16_t vtr;
+ uint16_t vsp;
+ uint16_t vdp;
+ uint16_t wx;
+ uint16_t wy;
+ uint16_t ww;
+ uint16_t wh;
+
+ /* Layer 0 */
+ uint32_t l0m;
+ uint32_t l0oa;
+ uint32_t l0da;
+ uint16_t l0dx;
+ uint16_t l0dy;
+
+ /* Layer 1 */
+ uint32_t l1m;
+ uint32_t cbda0;
+ uint32_t cbda1;
+ uint32_t pad02;
+
+ /* Layer 2 */
+ uint32_t l2m;
+ uint32_t l2oa0;
+ uint32_t l2da0;
+ uint32_t l2oa1;
+ uint32_t l2da1;
+ uint16_t l2dx;
+ uint16_t l2dy;
+
+ /* Layer 3 */
+ uint32_t l3m;
+ uint32_t l3oa0;
+ uint32_t l3da0;
+ uint32_t l3oa1;
+ uint32_t l3da1;
+ uint16_t l3dx;
+ uint16_t l3dy;
+
+ /* Layer 4 */
+ uint32_t l4m;
+ uint32_t l4oa0;
+ uint32_t l4da0;
+ uint32_t l4oa1;
+ uint32_t l4da1;
+ uint16_t l4dx;
+ uint16_t l4dy;
+
+ /* Layer 5 */
+ uint32_t l5m;
+ uint32_t l5oa0;
+ uint32_t l5da0;
+ uint32_t l5oa1;
+ uint32_t l5da1;
+ uint16_t l5dx;
+ uint16_t l5dy;
+
+ /* Cursor */
+ uint16_t cutc;
+ uint8_t cpm;
+ uint8_t csize;
+ uint32_t cuoa0;
+ uint16_t cux0;
+ uint16_t cuy0;
+ uint32_t cuoa1;
+ uint16_t cux1;
+ uint16_t cuy1;
+
+ /* Layer blending */
+ uint32_t l0bld;
+ uint32_t pad03;
+ uint32_t l0tc;
+ uint16_t l3tc;
+ uint16_t l2tc;
+ uint32_t pad04[15];
+
+ /* Display settings */
+ uint32_t dcm1;
+ uint32_t dcm2;
+ uint32_t dcm3;
+ uint32_t pad05;
+
+ /* Layer 0 extended */
+ uint32_t l0em;
+ uint16_t l0wx;
+ uint16_t l0wy;
+ uint16_t l0ww;
+ uint16_t l0wh;
+ uint32_t pad06;
+
+ /* Layer 1 extended */
+ uint32_t l1em;
+ uint16_t l1wx;
+ uint16_t l1wy;
+ uint16_t l1ww;
+ uint16_t l1wh;
+ uint32_t pad07;
+
+ /* Layer 2 extended */
+ uint32_t l2em;
+ uint16_t l2wx;
+ uint16_t l2wy;
+ uint16_t l2ww;
+ uint16_t l2wh;
+ uint32_t pad08;
+
+ /* Layer 3 extended */
+ uint32_t l3em;
+ uint16_t l3wx;
+ uint16_t l3wy;
+ uint16_t l3ww;
+ uint16_t l3wh;
+ uint32_t pad09;
+
+ /* Layer 4 extended */
+ uint32_t l4em;
+ uint16_t l4wx;
+ uint16_t l4wy;
+ uint16_t l4ww;
+ uint16_t l4wh;
+ uint32_t pad10;
+
+ /* Layer 5 extended */
+ uint32_t l5em;
+ uint16_t l5wx;
+ uint16_t l5wy;
+ uint16_t l5ww;
+ uint16_t l5wh;
+ uint32_t pad11;
+
+ /* Multi screen control */
+ uint32_t msc;
+ uint32_t pad12[3];
+ uint32_t dls;
+ uint32_t dbgc;
+
+ /* Layer blending */
+ uint32_t l1bld;
+ uint32_t l2bld;
+ uint32_t l3bld;
+ uint32_t l4bld;
+ uint32_t l5bld;
+ uint32_t pad13;
+
+ /* Extended transparency control */
+ uint32_t l0etc;
+ uint32_t l1etc;
+ uint32_t l2etc;
+ uint32_t l3etc;
+ uint32_t l4etc;
+ uint32_t l5etc;
+ uint32_t pad14[10];
+
+ /* YUV coefficients */
+ uint32_t l1ycr0;
+ uint32_t l1ycr1;
+ uint32_t l1ycg0;
+ uint32_t l1ycg1;
+ uint32_t l1ycb0;
+ uint32_t l1ycb1;
+ uint32_t pad15[130];
+
+ /* Layer palletes */
+ uint32_t l0pal[256];
+ uint32_t l1pal[256];
+ uint32_t pad16[256];
+ uint32_t l2pal[256];
+ uint32_t l3pal[256];
+ uint32_t pad17[256];
+
+ /* PWM settings */
+ uint32_t vpwmm;
+ uint16_t vpwms;
+ uint16_t vpwme;
+ uint32_t vpwmc;
+ uint32_t pad18[253];
+};
+
+/* mb86r0x gdc capture controller */
+struct mb86r0x_gdc_cap {
+ uint32_t vcm;
+ uint32_t csc;
+ uint32_t vcs;
+ uint32_t pad01;
+
+ uint32_t cbm;
+ uint32_t cboa;
+ uint32_t cbla;
+ uint16_t cihstr;
+ uint16_t civstr;
+ uint16_t cihend;
+ uint16_t civend;
+ uint32_t pad02;
+
+ uint32_t chp;
+ uint32_t cvp;
+ uint32_t pad03[4];
+
+ uint32_t clpf;
+ uint32_t pad04;
+ uint32_t cmss;
+ uint32_t cmds;
+ uint32_t pad05[12];
+
+ uint32_t rgbhc;
+ uint32_t rgbhen;
+ uint32_t rgbven;
+ uint32_t pad06;
+ uint32_t rgbs;
+ uint32_t pad07[11];
+
+ uint32_t rgbcmy;
+ uint32_t rgbcmcb;
+ uint32_t rgbcmcr;
+ uint32_t rgbcmb;
+ uint32_t pad08[12 + 1984];
+};
+
+/* mb86r0x gdc draw */
+struct mb86r0x_gdc_draw {
+ uint32_t ys;
+ uint32_t xs;
+ uint32_t dxdy;
+ uint32_t xus;
+ uint32_t dxudy;
+ uint32_t xls;
+ uint32_t dxldy;
+ uint32_t usn;
+ uint32_t lsn;
+ uint32_t pad01[7];
+ uint32_t rs;
+ uint32_t drdx;
+ uint32_t drdy;
+ uint32_t gs;
+ uint32_t dgdx;
+ uint32_t dgdy;
+ uint32_t bs;
+ uint32_t dbdx;
+ uint32_t dbdy;
+ uint32_t pad02[7];
+ uint32_t zs;
+ uint32_t dzdx;
+ uint32_t dzdy;
+ uint32_t pad03[13];
+ uint32_t ss;
+ uint32_t dsdx;
+ uint32_t dsdy;
+ uint32_t ts;
+ uint32_t dtdx;
+ uint32_t dtdy;
+ uint32_t qs;
+ uint32_t dqdx;
+ uint32_t dqdy;
+ uint32_t pad04[23];
+ uint32_t lpn;
+ uint32_t lxs;
+ uint32_t lxde;
+ uint32_t lys;
+ uint32_t lyde;
+ uint32_t lzs;
+ uint32_t lzde;
+ uint32_t pad05[13];
+ uint32_t pxdc;
+ uint32_t pydc;
+ uint32_t pzdc;
+ uint32_t pad06[25];
+ uint32_t rxs;
+ uint32_t rys;
+ uint32_t rsizex;
+ uint32_t rsizey;
+ uint32_t pad07[12];
+ uint32_t saddr;
+ uint32_t sstride;
+ uint32_t srx;
+ uint32_t sry;
+ uint32_t daddr;
+ uint32_t dstride;
+ uint32_t drx;
+ uint32_t dry;
+ uint32_t brsizex;
+ uint32_t brsizey;
+ uint32_t tcolor;
+ uint32_t pad08[93];
+ uint32_t blpo;
+ uint32_t pad09[7];
+ uint32_t ctr;
+ uint32_t ifsr;
+ uint32_t ifcnt;
+ uint32_t sst;
+ uint32_t ds;
+ uint32_t pst;
+ uint32_t est;
+ uint32_t pad10;
+ uint32_t mdr0;
+ uint32_t mdr1;
+ uint32_t mdr2;
+ uint32_t mdr3;
+ uint32_t mdr4;
+ uint32_t pad14[2];
+ uint32_t mdr7;
+ uint32_t fbr;
+ uint32_t xres;
+ uint32_t zbr;
+ uint32_t tbr;
+ uint32_t pfbr;
+ uint32_t cxmin;
+ uint32_t cxmax;
+ uint32_t cymin;
+ uint32_t cymax;
+ uint32_t txs;
+ uint32_t tis;
+ uint32_t toa;
+ uint32_t sho;
+ uint32_t abr;
+ uint32_t pad15[2];
+ uint32_t fc;
+ uint32_t bc;
+ uint32_t alf;
+ uint32_t blp;
+ uint32_t pad16;
+ uint32_t tbc;
+ uint32_t pad11[42];
+ uint32_t lx0dc;
+ uint32_t ly0dc;
+ uint32_t lx1dc;
+ uint32_t ly1dc;
+ uint32_t pad12[12];
+ uint32_t x0dc;
+ uint32_t y0dc;
+ uint32_t x1dc;
+ uint32_t y1dc;
+ uint32_t x2dc;
+ uint32_t y2dc;
+ uint32_t pad13[666];
+};
+
+/* mb86r0x gdc geometry engine */
+struct mb86r0x_gdc_geom {
+ uint32_t gctr;
+ uint32_t pad00[15];
+ uint32_t gmdr0;
+ uint32_t gmdr1;
+ uint32_t gmdr2;
+ uint32_t pad01[237];
+ uint32_t dfifog;
+ uint32_t pad02[767];
+};
+
+/* mb86r0x gdc */
+struct mb86r0x_gdc {
+ uint32_t pad00[2];
+ uint32_t lts;
+ uint32_t pad01;
+ uint32_t lsta;
+ uint32_t pad02[3];
+ uint32_t ist;
+ uint32_t imask;
+ uint32_t pad03[6];
+ uint32_t lsa;
+ uint32_t lco;
+ uint32_t lreq;
+
+ uint32_t pad04[16*1024 - 19];
+ struct mb86r0x_gdc_dsp dsp0;
+ struct mb86r0x_gdc_dsp dsp1;
+ uint32_t pad05[4*1024 - 2];
+ uint32_t vccc;
+ uint32_t vcsr;
+ struct mb86r0x_gdc_cap cap0;
+ struct mb86r0x_gdc_cap cap1;
+ uint32_t pad06[4*1024];
+ uint32_t texture_base[16*1024];
+ struct mb86r0x_gdc_draw draw;
+ uint32_t pad07[7*1024];
+ struct mb86r0x_gdc_geom geom;
+ uint32_t pad08[7*1024];
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Physical Address Defines
+ */
+#define MB86R0x_DDR2_BASE 0xf3000000
+#define MB86R0x_GDC_BASE 0xf1fc0000
+#define MB86R0x_CCNT_BASE 0xfff42000
+#define MB86R0x_CAN0_BASE 0xfff54000
+#define MB86R0x_CAN1_BASE 0xfff55000
+#define MB86R0x_I2C0_BASE 0xfff56000
+#define MB86R0x_I2C1_BASE 0xfff57000
+#define MB86R0x_EHCI_BASE 0xfff80000
+#define MB86R0x_OHCI_BASE 0xfff81000
+#define MB86R0x_IRC1_BASE 0xfffb0000
+#define MB86R0x_MEMC_BASE 0xfffc0000
+#define MB86R0x_TIMER_BASE 0xfffe0000
+#define MB86R0x_UART0_BASE 0xfffe1000
+#define MB86R0x_UART1_BASE 0xfffe2000
+#define MB86R0x_IRCE_BASE 0xfffe4000
+#define MB86R0x_CRG_BASE 0xfffe7000
+#define MB86R0x_IRC0_BASE 0xfffe8000
+#define MB86R0x_GPIO_BASE 0xfffe9000
+#define MB86R0x_PWM0_BASE 0xfff41000
+#define MB86R0x_PWM1_BASE 0xfff41100
+
+#define MB86R0x_CRSR_SWRSTREQ (1 << 1)
+
+/*
+ * Timer register bits
+ */
+#define MB86R0x_TIMER_ENABLE (1 << 7)
+#define MB86R0x_TIMER_MODE_MSK (1 << 6)
+#define MB86R0x_TIMER_MODE_FR (0 << 6)
+#define MB86R0x_TIMER_MODE_PD (1 << 6)
+
+#define MB86R0x_TIMER_INT_EN (1 << 5)
+#define MB86R0x_TIMER_PRS_MSK (3 << 2)
+#define MB86R0x_TIMER_PRS_4S (1 << 2)
+#define MB86R0x_TIMER_PRS_8S (1 << 3)
+#define MB86R0x_TIMER_SIZE_32 (1 << 1)
+#define MB86R0x_TIMER_ONE_SHT (1 << 0)
+
+/*
+ * Clock reset generator bits
+ */
+#define MB86R0x_CRG_CRPR_PLLRDY (1 << 8)
+#define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0)
+/*
+ * DDR2 controller bits
+ */
+#define MB86R0x_DDR2_DRCI_DRINI (1 << 15)
+#define MB86R0x_DDR2_DRCI_CKEN (1 << 14)
+#define MB86R0x_DDR2_DRCI_DRCMD (1 << 0)
+#define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \
+ MB86R0x_DDR2_DRCI_CKEN | \
+ MB86R0x_DDR2_DRCI_DRCMD)
+#define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \
+ MB86R0x_DDR2_DRCI_CKEN)
+#define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN
+#endif /* MB86R0X_H */
diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h
index 80717f8a57..6ce02a9212 100644
--- a/arch/arm/include/asm/arch-orion5x/cpu.h
+++ b/arch/arm/include/asm/arch-orion5x/cpu.h
@@ -76,7 +76,7 @@ enum orion5x_cpu_attrib {
/*
* Device Address MAP BAR values
-/*
+ *
* All addresses and sizes not defined by board code
* will be given default values here.
*/
diff --git a/arch/arm/include/asm/arch-s5pc1xx/clk.h b/arch/arm/include/asm/arch-s5pc1xx/clk.h
index 3e59abe78c..3488eb7c15 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/clk.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/clk.h
@@ -29,10 +29,11 @@
#define HPLL 3
#define VPLL 4
-void s5pc1xx_clock_init(void);
+void s5p_clock_init(void);
extern unsigned long (*get_pll_clk)(int pllreg);
extern unsigned long (*get_arm_clk)(void);
-extern unsigned long (*get_pclk)(void);
+extern unsigned long (*get_pwm_clk)(void);
+extern unsigned long (*get_uart_clk)(int dev_index);
#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h
index b3af8cc782..e74959fe22 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h
@@ -25,9 +25,9 @@
#define S5PC1XX_ADDR_BASE 0xE0000000
-#define S5PC1XX_CLOCK_BASE 0xE0100000
-
/* S5PC100 */
+#define S5PC100_PRO_ID 0xE0000000
+#define S5PC100_CLOCK_BASE 0xE0100000
#define S5PC100_GPIO_BASE 0xE0300000
#define S5PC100_VIC0_BASE 0xE4000000
#define S5PC100_VIC1_BASE 0xE4100000
@@ -41,6 +41,8 @@
#define S5PC100_MMC_BASE 0xED800000
/* S5PC110 */
+#define S5PC110_PRO_ID 0xE0000000
+#define S5PC110_CLOCK_BASE 0xE0100000
#define S5PC110_GPIO_BASE 0xE0200000
#define S5PC110_PWMTIMER_BASE 0xE2500000
#define S5PC110_WATCHDOG_BASE 0xE2700000
@@ -54,21 +56,44 @@
#define S5PC110_VIC2_BASE 0xF2200000
#define S5PC110_VIC3_BASE 0xF2300000
-/* Chip ID */
-#define S5PC1XX_PRO_ID 0xE0000000
-
#ifndef __ASSEMBLY__
+#include <asm/io.h>
/* CPU detection macros */
-extern unsigned int s5pc1xx_cpu_id;
+extern unsigned int s5p_cpu_id;
+
+static inline void s5p_set_cpu_id(void)
+{
+ s5p_cpu_id = readl(S5PC100_PRO_ID);
+ s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
+}
#define IS_SAMSUNG_TYPE(type, id) \
static inline int cpu_is_##type(void) \
{ \
- return s5pc1xx_cpu_id == id ? 1 : 0; \
+ return s5p_cpu_id == id ? 1 : 0; \
}
IS_SAMSUNG_TYPE(s5pc100, 0xc100)
IS_SAMSUNG_TYPE(s5pc110, 0xc110)
+
+#define SAMSUNG_BASE(device, base) \
+static inline unsigned int samsung_get_base_##device(void) \
+{ \
+ if (cpu_is_s5pc100()) \
+ return S5PC100_##base; \
+ else if (cpu_is_s5pc110()) \
+ return S5PC110_##base; \
+ else \
+ return 0; \
+}
+
+SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(gpio, GPIO_BASE)
+SAMSUNG_BASE(pro_id, PRO_ID)
+SAMSUNG_BASE(mmc, MMC_BASE)
+SAMSUNG_BASE(sromc, SROMC_BASE)
+SAMSUNG_BASE(timer, PWMTIMER_BASE)
+SAMSUNG_BASE(uart, UART_BASE)
#endif
#endif /* _S5PC1XX_CPU_H */
diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
index 9a7faed319..2df33a607c 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
@@ -33,96 +33,96 @@ struct s5p_gpio_bank {
};
struct s5pc100_gpio {
- struct s5p_gpio_bank gpio_a0;
- struct s5p_gpio_bank gpio_a1;
- struct s5p_gpio_bank gpio_b;
- struct s5p_gpio_bank gpio_c;
- struct s5p_gpio_bank gpio_d;
- struct s5p_gpio_bank gpio_e0;
- struct s5p_gpio_bank gpio_e1;
- struct s5p_gpio_bank gpio_f0;
- struct s5p_gpio_bank gpio_f1;
- struct s5p_gpio_bank gpio_f2;
- struct s5p_gpio_bank gpio_f3;
- struct s5p_gpio_bank gpio_g0;
- struct s5p_gpio_bank gpio_g1;
- struct s5p_gpio_bank gpio_g2;
- struct s5p_gpio_bank gpio_g3;
- struct s5p_gpio_bank gpio_i;
- struct s5p_gpio_bank gpio_j0;
- struct s5p_gpio_bank gpio_j1;
- struct s5p_gpio_bank gpio_j2;
- struct s5p_gpio_bank gpio_j3;
- struct s5p_gpio_bank gpio_j4;
- struct s5p_gpio_bank gpio_k0;
- struct s5p_gpio_bank gpio_k1;
- struct s5p_gpio_bank gpio_k2;
- struct s5p_gpio_bank gpio_k3;
- struct s5p_gpio_bank gpio_l0;
- struct s5p_gpio_bank gpio_l1;
- struct s5p_gpio_bank gpio_l2;
- struct s5p_gpio_bank gpio_l3;
- struct s5p_gpio_bank gpio_l4;
- struct s5p_gpio_bank gpio_h0;
- struct s5p_gpio_bank gpio_h1;
- struct s5p_gpio_bank gpio_h2;
- struct s5p_gpio_bank gpio_h3;
+ struct s5p_gpio_bank a0;
+ struct s5p_gpio_bank a1;
+ struct s5p_gpio_bank b;
+ struct s5p_gpio_bank c;
+ struct s5p_gpio_bank d;
+ struct s5p_gpio_bank e0;
+ struct s5p_gpio_bank e1;
+ struct s5p_gpio_bank f0;
+ struct s5p_gpio_bank f1;
+ struct s5p_gpio_bank f2;
+ struct s5p_gpio_bank f3;
+ struct s5p_gpio_bank g0;
+ struct s5p_gpio_bank g1;
+ struct s5p_gpio_bank g2;
+ struct s5p_gpio_bank g3;
+ struct s5p_gpio_bank i;
+ struct s5p_gpio_bank j0;
+ struct s5p_gpio_bank j1;
+ struct s5p_gpio_bank j2;
+ struct s5p_gpio_bank j3;
+ struct s5p_gpio_bank j4;
+ struct s5p_gpio_bank k0;
+ struct s5p_gpio_bank k1;
+ struct s5p_gpio_bank k2;
+ struct s5p_gpio_bank k3;
+ struct s5p_gpio_bank l0;
+ struct s5p_gpio_bank l1;
+ struct s5p_gpio_bank l2;
+ struct s5p_gpio_bank l3;
+ struct s5p_gpio_bank l4;
+ struct s5p_gpio_bank h0;
+ struct s5p_gpio_bank h1;
+ struct s5p_gpio_bank h2;
+ struct s5p_gpio_bank h3;
};
struct s5pc110_gpio {
- struct s5p_gpio_bank gpio_a0;
- struct s5p_gpio_bank gpio_a1;
- struct s5p_gpio_bank gpio_b;
- struct s5p_gpio_bank gpio_c0;
- struct s5p_gpio_bank gpio_c1;
- struct s5p_gpio_bank gpio_d0;
- struct s5p_gpio_bank gpio_d1;
- struct s5p_gpio_bank gpio_e0;
- struct s5p_gpio_bank gpio_e1;
- struct s5p_gpio_bank gpio_f0;
- struct s5p_gpio_bank gpio_f1;
- struct s5p_gpio_bank gpio_f2;
- struct s5p_gpio_bank gpio_f3;
- struct s5p_gpio_bank gpio_g0;
- struct s5p_gpio_bank gpio_g1;
- struct s5p_gpio_bank gpio_g2;
- struct s5p_gpio_bank gpio_g3;
- struct s5p_gpio_bank gpio_i;
- struct s5p_gpio_bank gpio_j0;
- struct s5p_gpio_bank gpio_j1;
- struct s5p_gpio_bank gpio_j2;
- struct s5p_gpio_bank gpio_j3;
- struct s5p_gpio_bank gpio_j4;
- struct s5p_gpio_bank gpio_mp0_1;
- struct s5p_gpio_bank gpio_mp0_2;
- struct s5p_gpio_bank gpio_mp0_3;
- struct s5p_gpio_bank gpio_mp0_4;
- struct s5p_gpio_bank gpio_mp0_5;
- struct s5p_gpio_bank gpio_mp0_6;
- struct s5p_gpio_bank gpio_mp0_7;
- struct s5p_gpio_bank gpio_mp1_0;
- struct s5p_gpio_bank gpio_mp1_1;
- struct s5p_gpio_bank gpio_mp1_2;
- struct s5p_gpio_bank gpio_mp1_3;
- struct s5p_gpio_bank gpio_mp1_4;
- struct s5p_gpio_bank gpio_mp1_5;
- struct s5p_gpio_bank gpio_mp1_6;
- struct s5p_gpio_bank gpio_mp1_7;
- struct s5p_gpio_bank gpio_mp1_8;
- struct s5p_gpio_bank gpio_mp2_0;
- struct s5p_gpio_bank gpio_mp2_1;
- struct s5p_gpio_bank gpio_mp2_2;
- struct s5p_gpio_bank gpio_mp2_3;
- struct s5p_gpio_bank gpio_mp2_4;
- struct s5p_gpio_bank gpio_mp2_5;
- struct s5p_gpio_bank gpio_mp2_6;
- struct s5p_gpio_bank gpio_mp2_7;
- struct s5p_gpio_bank gpio_mp2_8;
+ struct s5p_gpio_bank a0;
+ struct s5p_gpio_bank a1;
+ struct s5p_gpio_bank b;
+ struct s5p_gpio_bank c0;
+ struct s5p_gpio_bank c1;
+ struct s5p_gpio_bank d0;
+ struct s5p_gpio_bank d1;
+ struct s5p_gpio_bank e0;
+ struct s5p_gpio_bank e1;
+ struct s5p_gpio_bank f0;
+ struct s5p_gpio_bank f1;
+ struct s5p_gpio_bank f2;
+ struct s5p_gpio_bank f3;
+ struct s5p_gpio_bank g0;
+ struct s5p_gpio_bank g1;
+ struct s5p_gpio_bank g2;
+ struct s5p_gpio_bank g3;
+ struct s5p_gpio_bank i;
+ struct s5p_gpio_bank j0;
+ struct s5p_gpio_bank j1;
+ struct s5p_gpio_bank j2;
+ struct s5p_gpio_bank j3;
+ struct s5p_gpio_bank j4;
+ struct s5p_gpio_bank mp0_1;
+ struct s5p_gpio_bank mp0_2;
+ struct s5p_gpio_bank mp0_3;
+ struct s5p_gpio_bank mp0_4;
+ struct s5p_gpio_bank mp0_5;
+ struct s5p_gpio_bank mp0_6;
+ struct s5p_gpio_bank mp0_7;
+ struct s5p_gpio_bank mp1_0;
+ struct s5p_gpio_bank mp1_1;
+ struct s5p_gpio_bank mp1_2;
+ struct s5p_gpio_bank mp1_3;
+ struct s5p_gpio_bank mp1_4;
+ struct s5p_gpio_bank mp1_5;
+ struct s5p_gpio_bank mp1_6;
+ struct s5p_gpio_bank mp1_7;
+ struct s5p_gpio_bank mp1_8;
+ struct s5p_gpio_bank mp2_0;
+ struct s5p_gpio_bank mp2_1;
+ struct s5p_gpio_bank mp2_2;
+ struct s5p_gpio_bank mp2_3;
+ struct s5p_gpio_bank mp2_4;
+ struct s5p_gpio_bank mp2_5;
+ struct s5p_gpio_bank mp2_6;
+ struct s5p_gpio_bank mp2_7;
+ struct s5p_gpio_bank mp2_8;
struct s5p_gpio_bank res1[48];
- struct s5p_gpio_bank gpio_h0;
- struct s5p_gpio_bank gpio_h1;
- struct s5p_gpio_bank gpio_h2;
- struct s5p_gpio_bank gpio_h3;
+ struct s5p_gpio_bank h0;
+ struct s5p_gpio_bank h1;
+ struct s5p_gpio_bank h2;
+ struct s5p_gpio_bank h3;
};
/* functions */
diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
index ac560c2704..68c59d13e3 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
@@ -56,7 +56,7 @@ struct s5p_mmc {
unsigned int control4;
unsigned char res4[0x6e];
unsigned short hcver;
- unsigned char res5[0xFFF00];
+ unsigned char res5[0xFFF02];
};
struct mmc_host {
diff --git a/arch/arm/include/asm/arch-s5pc1xx/pwm.h b/arch/arm/include/asm/arch-s5pc1xx/pwm.h
index e02a8d8fb3..0369968d4a 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/pwm.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/pwm.h
@@ -22,19 +22,15 @@
#ifndef __ASM_ARM_ARCH_PWM_H_
#define __ASM_ARM_ARCH_PWM_H_
-/* PWM timer addressing */
-#define S5PC100_TIMER_BASE S5PC100_PWMTIMER_BASE
-#define S5PC110_TIMER_BASE S5PC110_PWMTIMER_BASE
-
/* Interval mode(Auto Reload) of PWM Timer 4 */
-#define S5PC1XX_TCON4_AUTO_RELOAD (1 << 22)
+#define TCON4_AUTO_RELOAD (1 << 22)
/* Update TCNTB4 */
-#define S5PC1XX_TCON4_UPDATE (1 << 21)
+#define TCON4_UPDATE (1 << 21)
/* start bit of PWM Timer 4 */
-#define S5PC1XX_TCON4_START (1 << 20)
+#define TCON4_START (1 << 20)
#ifndef __ASSEMBLY__
-struct s5pc1xx_timer {
+struct s5p_timer {
unsigned int tcfg0;
unsigned int tcfg1;
unsigned int tcon;