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-rw-r--r--arch/arm/include/asm/arch-am33xx/clock.h12
-rw-r--r--arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h8
-rw-r--r--arch/arm/include/asm/arch-rockchip/cru_rk3568.h2
-rw-r--r--arch/arm/include/asm/arch-stv0991/stv0991_gpt.h4
-rw-r--r--arch/arm/include/asm/arch-sunxi/ccu.h100
-rw-r--r--arch/arm/include/asm/arch-sunxi/gpio.h20
-rw-r--r--arch/arm/include/asm/arch-tegra/board.h10
7 files changed, 31 insertions, 125 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 5d775902bb..79e3b8c7d9 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -78,6 +78,18 @@
#define CM_CLKSEL_DPLL_N_SHIFT 0
#define CM_CLKSEL_DPLL_N_MASK 0x7F
+/* CM_SSC_DELTAM_DPLL */
+#define CM_SSC_DELTAM_DPLL_FRAC_SHIFT 0
+#define CM_SSC_DELTAM_DPLL_FRAC_MASK GENMASK(17, 0)
+#define CM_SSC_DELTAM_DPLL_INT_SHIFT 18
+#define CM_SSC_DELTAM_DPLL_INT_MASK GENMASK(19, 18)
+
+/* CM_SSC_MODFREQ_DPLL */
+#define CM_SSC_MODFREQ_DPLL_MANT_SHIFT 0
+#define CM_SSC_MODFREQ_DPLL_MANT_MASK GENMASK(6, 0)
+#define CM_SSC_MODFREQ_DPLL_EXP_SHIFT 7
+#define CM_SSC_MODFREQ_DPLL_EXP_MASK GENMASK(10, 8)
+
struct dpll_params {
u32 m;
u32 n;
diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
index ea2f113f98..df392a2714 100644
--- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
+++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
@@ -11,7 +11,7 @@
#include <asm/arch/sys_proto.h>
-/* CONFIG_REG_0 */
+/* CFG REG_0 */
#define CFG_REG_0_OFFSET 0xC
#define CFG_REG_ROM_READ_SHIFT 1
#define CFG_REG_ROM_READ_MASK (1 << 1)
@@ -22,18 +22,18 @@
#define CFG_REG_ROM_READ_START (1 << 1)
#define CFG_REG_ROM_READ_END (0 << 1)
-/* CONFIG_REG_2 */
+/* CFG REG_2 */
#define CFG_REG_2_OFFSET 0x14
#define CFG_REG_REFCLK_PERIOD_SHIFT 0
#define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0)
#define CFG_REG_REFCLK_PERIOD 0x2EF
-/* CONFIG_REG_8 */
+/* CFG REG_8 */
#define CFG_REG_8_OFFSET 0x2C
#define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA
#define CFG_IODELAY_LOCK_KEY 0x0000AAAB
-/* CONFIG_REG_3/4 */
+/* CFG REG_3/4 */
#define CFG_REG_3_OFFSET 0x18
#define CFG_REG_4_OFFSET 0x1C
#define CFG_REG_DLY_CNT_SHIFT 16
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
index 6c59033f03..399f19ad21 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
@@ -14,7 +14,7 @@
#define APLL_HZ (816 * MHz)
#define GPLL_HZ (1188 * MHz)
#define CPLL_HZ (1000 * MHz)
-#define PPLL_HZ (100 * MHz)
+#define PPLL_HZ (200 * MHz)
/* RK3568 pll id */
enum rk3568_pll_id {
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
index cd27472ad7..f1d5667c32 100644
--- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
@@ -36,7 +36,7 @@ struct gpt_regs *const gpt1_regs_ptr =
#define GPT_FREE_RUNNING 0xFFFF
/* Timer, HZ specific defines */
-#define CONFIG_STV0991_HZ 1000
-#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128)
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/arch/arm/include/asm/arch-sunxi/ccu.h
deleted file mode 100644
index cac5c5faf0..0000000000
--- a/arch/arm/include/asm/arch-sunxi/ccu.h
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Amarula Solutions.
- * Author: Jagan Teki <jagan@amarulasolutions.com>
- */
-
-#ifndef _ASM_ARCH_CCU_H
-#define _ASM_ARCH_CCU_H
-
-#ifndef __ASSEMBLY__
-#include <linux/bitops.h>
-#endif
-
-/**
- * enum ccu_flags - ccu clock/reset flags
- *
- * @CCU_CLK_F_IS_VALID: is given clock gate is valid?
- * @CCU_RST_F_IS_VALID: is given reset control is valid?
- */
-enum ccu_flags {
- CCU_CLK_F_IS_VALID = BIT(0),
- CCU_RST_F_IS_VALID = BIT(1),
-};
-
-/**
- * struct ccu_clk_gate - ccu clock gate
- * @off: gate offset
- * @bit: gate bit
- * @flags: ccu clock gate flags
- */
-struct ccu_clk_gate {
- u16 off;
- u32 bit;
- enum ccu_flags flags;
-};
-
-#define GATE(_off, _bit) { \
- .off = _off, \
- .bit = _bit, \
- .flags = CCU_CLK_F_IS_VALID, \
-}
-
-/**
- * struct ccu_reset - ccu reset
- * @off: reset offset
- * @bit: reset bit
- * @flags: ccu reset control flags
- */
-struct ccu_reset {
- u16 off;
- u32 bit;
- enum ccu_flags flags;
-};
-
-#define RESET(_off, _bit) { \
- .off = _off, \
- .bit = _bit, \
- .flags = CCU_RST_F_IS_VALID, \
-}
-
-/**
- * struct ccu_desc - clock control unit descriptor
- *
- * @gates: clock gates
- * @resets: reset unit
- */
-struct ccu_desc {
- const struct ccu_clk_gate *gates;
- const struct ccu_reset *resets;
-};
-
-/**
- * struct ccu_priv - sunxi clock control unit
- *
- * @base: base address
- * @desc: ccu descriptor
- */
-struct ccu_priv {
- void *base;
- const struct ccu_desc *desc;
-};
-
-/**
- * sunxi_clk_probe - common sunxi clock probe
- * @dev: clock device
- */
-int sunxi_clk_probe(struct udevice *dev);
-
-extern struct clk_ops sunxi_clk_ops;
-
-/**
- * sunxi_reset_bind() - reset binding
- *
- * @dev: reset device
- * @count: reset count
- * @return 0 success, or error value
- */
-int sunxi_reset_bind(struct udevice *dev, ulong count);
-
-#endif /* _ASM_ARCH_CCU_H */
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 2969a530ae..f3ab1aea0e 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -93,20 +93,10 @@ struct sunxi_gpio_reg {
#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
/* GPIO bank sizes */
-#define SUNXI_GPIO_A_NR 32
-#define SUNXI_GPIO_B_NR 32
-#define SUNXI_GPIO_C_NR 32
-#define SUNXI_GPIO_D_NR 32
-#define SUNXI_GPIO_E_NR 32
-#define SUNXI_GPIO_F_NR 32
-#define SUNXI_GPIO_G_NR 32
-#define SUNXI_GPIO_H_NR 32
-#define SUNXI_GPIO_I_NR 32
-#define SUNXI_GPIO_L_NR 32
-#define SUNXI_GPIO_M_NR 32
+#define SUNXI_GPIOS_PER_BANK 32
#define SUNXI_GPIO_NEXT(__gpio) \
- ((__gpio##_START) + (__gpio##_NR) + 0)
+ ((__gpio##_START) + SUNXI_GPIOS_PER_BANK)
enum sunxi_gpio_number {
SUNXI_GPIO_A_START = 0,
@@ -148,8 +138,6 @@ enum sunxi_gpio_number {
#define SUNXI_GPA_EMAC 2
#define SUN6I_GPA_GMAC 2
#define SUN7I_GPA_GMAC 5
-#define SUN6I_GPA_SDC2 5
-#define SUN6I_GPA_SDC3 4
#define SUN8I_H3_GPA_UART0 2
#define SUN4I_GPB_PWM 2
@@ -173,12 +161,10 @@ enum sunxi_gpio_number {
#define SUN6I_GPC_SDC3 4
#define SUN50I_GPC_SPI0 4
-#define SUN8I_GPD_SDC1 3
#define SUNXI_GPD_LCD0 2
#define SUNXI_GPD_LVDS0 3
#define SUNXI_GPD_PWM 2
-#define SUN5I_GPE_SDC2 3
#define SUN8I_GPE_TWI2 3
#define SUN50I_GPE_TWI2 3
@@ -242,9 +228,7 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
int sunxi_gpio_get_cfgpin(u32 pin);
int sunxi_gpio_set_drv(u32 pin, u32 val);
int sunxi_gpio_set_pull(u32 pin, u32 val);
-int sunxi_name_to_gpio_bank(const char *name);
int sunxi_name_to_gpio(const char *name);
-#define name_to_gpio(name) sunxi_name_to_gpio(name)
#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
int axp_gpio_init(void);
diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h
index 24d0db8ced..cd4d0ee3c9 100644
--- a/arch/arm/include/asm/arch-tegra/board.h
+++ b/arch/arm/include/asm/arch-tegra/board.h
@@ -30,4 +30,14 @@ void pin_mux_nand(void); /* overridable NAND pinmux setup */
void pin_mux_mmc(void); /* overridable mmc pinmux setup */
void pin_mux_display(void); /* overridable DISPLAY pinmux setup */
+/*
+ * Helpers for various standard DT update mechanisms.
+ */
+
+#if defined(CONFIG_ARM64)
+void ft_mac_address_setup(void *fdt);
+void ft_carveout_setup(void *fdt, const char *const *nodes,
+ unsigned int count);
+#endif
+
#endif
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-07 09:34:06 +0000