diff options
Diffstat (limited to 'arch/arm/include')
19 files changed, 2068 insertions, 504 deletions
diff --git a/arch/arm/include/asm/arch-px30/boot0.h b/arch/arm/include/asm/arch-px30/boot0.h new file mode 100644 index 00000000000..2e78b074ade --- /dev/null +++ b/arch/arm/include/asm/arch-px30/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include <asm/arch-rockchip/boot0.h> + +#endif diff --git a/arch/arm/include/asm/arch-px30/gpio.h b/arch/arm/include/asm/arch-px30/gpio.h new file mode 100644 index 00000000000..eca79d51594 --- /dev/null +++ b/arch/arm/include/asm/arch-px30/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include <asm/arch-rockchip/gpio.h> + +#endif diff --git a/arch/arm/include/asm/arch-rk3308/boot0.h b/arch/arm/include/asm/arch-rk3308/boot0.h new file mode 100644 index 00000000000..2e78b074ade --- /dev/null +++ b/arch/arm/include/asm/arch-rk3308/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include <asm/arch-rockchip/boot0.h> + +#endif diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h new file mode 100644 index 00000000000..a14b64cdb3e --- /dev/null +++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h @@ -0,0 +1,290 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd. + */ +#ifndef _ASM_ARCH_CRU_RK3308_H +#define _ASM_ARCH_CRU_RK3308_H + +#include <common.h> + +#define MHz 1000000 +#define OSC_HZ (24 * MHz) + +#define APLL_HZ (816 * MHz) + +#define CORE_ACLK_HZ 408000000 +#define CORE_DBG_HZ 204000000 + +#define BUS_ACLK_HZ 200000000 +#define BUS_HCLK_HZ 100000000 +#define BUS_PCLK_HZ 100000000 + +#define PERI_ACLK_HZ 200000000 +#define PERI_HCLK_HZ 100000000 +#define PERI_PCLK_HZ 100000000 + +#define AUDIO_HCLK_HZ 100000000 +#define AUDIO_PCLK_HZ 100000000 + +#define RK3308_PLL_CON(x) ((x) * 0x4) +#define RK3308_MODE_CON 0xa0 + +/* RK3308 pll id */ +enum rk3308_pll_id { + APLL, + DPLL, + VPLL0, + VPLL1, + PLL_COUNT, +}; + +struct rk3308_clk_info { + unsigned long id; + char *name; +}; + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3308_clk_priv { + struct rk3308_cru *cru; + ulong armclk_hz; + ulong dpll_hz; + ulong vpll0_hz; + ulong vpll1_hz; +}; + +struct rk3308_cru { + struct rk3308_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int reserved0[3]; + } pll[4]; + unsigned int reserved1[8]; + unsigned int mode; + unsigned int misc; + unsigned int reserved2[2]; + unsigned int glb_cnt_th; + unsigned int glb_rst_st; + unsigned int glb_srst_fst; + unsigned int glb_srst_snd; + unsigned int glb_rst_con; + unsigned int pll_lock; + unsigned int reserved3[6]; + unsigned int hwffc_con0; + unsigned int reserved4; + unsigned int hwffc_th; + unsigned int hwffc_intst; + unsigned int apll_con0_s; + unsigned int apll_con1_s; + unsigned int clksel_con0_s; + unsigned int reserved5; + unsigned int clksel_con[74]; + unsigned int reserved6[54]; + unsigned int clkgate_con[15]; + unsigned int reserved7[(0x380 - 0x338) / 4 - 1]; + unsigned int ssgtbl[32]; + unsigned int softrst_con[10]; + unsigned int reserved8[(0x480 - 0x424) / 4 - 1]; + unsigned int sdmmc_con[2]; + unsigned int sdio_con[2]; + unsigned int emmc_con[2]; +}; + +enum { + /* PLLCON0*/ + PLL_BP_SHIFT = 15, + PLL_POSTDIV1_SHIFT = 12, + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, + PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, + + /* PLLCON1 */ + PLL_PDSEL_SHIFT = 15, + PLL_PD1_SHIFT = 14, + PLL_PD_SHIFT = 13, + PLL_PD_MASK = 1 << PLL_PD_SHIFT, + PLL_DSMPD_SHIFT = 12, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, + PLL_POSTDIV2_SHIFT = 6, + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, + PLL_REFDIV_SHIFT = 0, + PLL_REFDIV_MASK = 0x3f, + + /* PLLCON2 */ + PLL_FOUT4PHASEPD_SHIFT = 27, + PLL_FOUTVCOPD_SHIFT = 26, + PLL_FOUTPOSTDIVPD_SHIFT = 25, + PLL_DACPD_SHIFT = 24, + PLL_FRAC_DIV = 0xffffff, + + /* CRU_MODE */ + PLLMUX_FROM_XIN24M = 0, + PLLMUX_FROM_PLL, + PLLMUX_FROM_RTC32K, + USBPHY480M_MODE_SHIFT = 8, + USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, + VPLL1_MODE_SHIFT = 6, + VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT, + VPLL0_MODE_SHIFT = 4, + VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT, + DPLL_MODE_SHIFT = 2, + DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, + + /* CRU_CLK_SEL0_CON */ + CORE_ACLK_DIV_SHIFT = 12, + CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT, + CORE_DBG_DIV_SHIFT = 8, + CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT, + CORE_CLK_PLL_SEL_SHIFT = 6, + CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_VPLL0, + CORE_CLK_PLL_SEL_VPLL1, + CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, + + /* CRU_CLK_SEL5_CON */ + BUS_PLL_SEL_SHIFT = 6, + BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT, + BUS_PLL_SEL_DPLL = 0, + BUS_PLL_SEL_VPLL0, + BUS_PLL_SEL_VPLL1, + BUS_ACLK_DIV_SHIFT = 0, + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, + + /* CRU_CLK_SEL6_CON */ + BUS_PCLK_DIV_SHIFT = 8, + BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT, + BUS_HCLK_DIV_SHIFT = 0, + BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, + + /* CRU_CLK_SEL7_CON */ + CRYPTO_APK_SEL_SHIFT = 14, + CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT, + CRYPTO_PLL_SEL_DPLL = 0, + CRYPTO_PLL_SEL_VPLL0, + CRYPTO_PLL_SEL_VPLL1 = 0, + CRYPTO_APK_DIV_SHIFT = 8, + CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT, + CRYPTO_PLL_SEL_SHIFT = 6, + CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT, + CRYPTO_DIV_SHIFT = 0, + CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT, + + /* CRU_CLK_SEL8_CON */ + DCLK_VOP_SEL_SHIFT = 14, + DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT, + DCLK_VOP_SEL_DIVOUT = 0, + DCLK_VOP_SEL_FRACOUT, + DCLK_VOP_SEL_24M, + DCLK_VOP_PLL_SEL_SHIFT = 10, + DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT, + DCLK_VOP_PLL_SEL_DPLL = 0, + DCLK_VOP_PLL_SEL_VPLL0, + DCLK_VOP_PLL_SEL_VPLL1, + DCLK_VOP_DIV_SHIFT = 0, + DCLK_VOP_DIV_MASK = 0xff, + + /* CRU_CLK_SEL25_CON */ + /* CRU_CLK_SEL26_CON */ + /* CRU_CLK_SEL27_CON */ + /* CRU_CLK_SEL28_CON */ + CLK_I2C_PLL_SEL_SHIFT = 14, + CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT, + CLK_I2C_PLL_SEL_DPLL = 0, + CLK_I2C_PLL_SEL_VPLL0, + CLK_I2C_PLL_SEL_24M, + CLK_I2C_DIV_CON_SHIFT = 0, + CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT, + + /* CRU_CLK_SEL29_CON */ + CLK_PWM_PLL_SEL_SHIFT = 14, + CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT, + CLK_PWM_PLL_SEL_DPLL = 0, + CLK_PWM_PLL_SEL_VPLL0, + CLK_PWM_PLL_SEL_24M, + CLK_PWM_DIV_CON_SHIFT = 0, + CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT, + + /* CRU_CLK_SEL30_CON */ + /* CRU_CLK_SEL31_CON */ + /* CRU_CLK_SEL32_CON */ + CLK_SPI_PLL_SEL_SHIFT = 14, + CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT, + CLK_SPI_PLL_SEL_DPLL = 0, + CLK_SPI_PLL_SEL_VPLL0, + CLK_SPI_PLL_SEL_24M, + CLK_SPI_DIV_CON_SHIFT = 0, + CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT, + + /* CRU_CLK_SEL34_CON */ + CLK_SARADC_DIV_CON_SHIFT = 0, + CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT, + + /* CRU_CLK_SEL36_CON */ + PERI_PLL_SEL_SHIFT = 6, + PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT, + PERI_PLL_DPLL = 0, + PERI_PLL_VPLL0, + PERI_PLL_VPLL1, + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, + + /* CRU_CLK_SEL37_CON */ + PERI_PCLK_DIV_SHIFT = 8, + PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT, + PERI_HCLK_DIV_SHIFT = 0, + PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, + + /* CRU_CLKSEL41_CON */ + EMMC_CLK_SEL_SHIFT = 15, + EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, + EMMC_CLK_SEL_EMMC = 0, + EMMC_CLK_SEL_EMMC_DIV50, + EMMC_PLL_SHIFT = 8, + EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT, + EMMC_SEL_DPLL = 0, + EMMC_SEL_VPLL0, + EMMC_SEL_VPLL1, + EMMC_SEL_24M, + EMMC_DIV_SHIFT = 0, + EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, + + /* CRU_CLKSEL43_CON */ + MAC_CLK_SPEED_SEL_SHIFT = 15, + MAC_CLK_SPEED_SEL_MASK = 1 << MAC_CLK_SPEED_SEL_SHIFT, + MAC_CLK_SPEED_SEL_10M = 0, + MAC_CLK_SPEED_SEL_100M, + MAC_CLK_SOURCE_SEL_SHIFT = 14, + MAC_CLK_SOURCE_SEL_MASK = 1 << MAC_CLK_SOURCE_SEL_SHIFT, + MAC_CLK_SOURCE_SEL_INTERNAL = 0, + MAC_CLK_SOURCE_SEL_EXTERNAL, + MAC_PLL_SHIFT = 6, + MAC_PLL_MASK = 0x3 << MAC_PLL_SHIFT, + MAC_SEL_DPLL = 0, + MAC_SEL_VPLL0, + MAC_SEL_VPLL1, + MAC_DIV_SHIFT = 0, + MAC_DIV_MASK = 0x1f << MAC_DIV_SHIFT, + + /* CRU_CLK_SEL45_CON */ + AUDIO_PCLK_DIV_SHIFT = 8, + AUDIO_PCLK_DIV_MASK = 0x1f << AUDIO_PCLK_DIV_SHIFT, + AUDIO_PLL_SEL_SHIFT = 6, + AUDIO_PLL_SEL_MASK = 0x3 << AUDIO_PLL_SEL_SHIFT, + AUDIO_PLL_VPLL0 = 0, + AUDIO_PLL_VPLL1, + AUDIO_PLL_24M, + AUDIO_HCLK_DIV_SHIFT = 0, + AUDIO_HCLK_DIV_MASK = 0x1f << AUDIO_HCLK_DIV_SHIFT, +}; + +check_member(rk3308_cru, emmc_con[1], 0x494); + +#endif diff --git a/arch/arm/include/asm/arch-rk3308/gpio.h b/arch/arm/include/asm/arch-rk3308/gpio.h new file mode 100644 index 00000000000..eca79d51594 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3308/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include <asm/arch-rockchip/gpio.h> + +#endif diff --git a/arch/arm/include/asm/arch-rk3308/grf_rk3308.h b/arch/arm/include/asm/arch-rk3308/grf_rk3308.h new file mode 100644 index 00000000000..3e68626d3e9 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3308/grf_rk3308.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + *Copyright 2019 Rockchip Electronics Co., Ltd. + */ +#ifndef _ASM_ARCH_GRF_rk3308_H +#define _ASM_ARCH_GRF_rk3308_H + +#include <common.h> + +struct rk3308_grf { + unsigned int gpio0a_iomux; + unsigned int reserved0; + unsigned int gpio0b_iomux; + unsigned int reserved1; + unsigned int gpio0c_iomux; + unsigned int reserved2[3]; + unsigned int gpio1a_iomux; + unsigned int reserved3; + unsigned int gpio1bl_iomux; + unsigned int gpio1bh_iomux; + unsigned int gpio1cl_iomux; + unsigned int gpio1ch_iomux; + unsigned int gpio1d_iomux; + unsigned int reserved4; + unsigned int gpio2a_iomux; + unsigned int reserved5; + unsigned int gpio2b_iomux; + unsigned int reserved6; + unsigned int gpio2c_iomux; + unsigned int reserved7[3]; + unsigned int gpio3a_iomux; + unsigned int reserved8; + unsigned int gpio3b_iomux; + unsigned int reserved9[5]; + unsigned int gpio4a_iomux; + unsigned int reserved33; + unsigned int gpio4b_iomux; + unsigned int reserved10; + unsigned int gpio4c_iomux; + unsigned int reserved11; + unsigned int gpio4d_iomux; + unsigned int reserved34; + unsigned int gpio0a_p; + unsigned int gpio0b_p; + unsigned int gpio0c_p; + unsigned int reserved12; + unsigned int gpio1a_p; + unsigned int gpio1b_p; + unsigned int gpio1c_p; + unsigned int gpio1d_p; + unsigned int gpio2a_p; + unsigned int gpio2b_p; + unsigned int gpio2c_p; + unsigned int reserved13; + unsigned int gpio3a_p; + unsigned int gpio3b_p; + unsigned int reserved14[2]; + unsigned int gpio4a_p; + unsigned int gpio4b_p; + unsigned int gpio4c_p; + unsigned int gpio4d_p; + unsigned int reserved15[(0x100 - 0xec) / 4 - 1]; + unsigned int gpio0a_e; + unsigned int gpio0b_e; + unsigned int gpio0c_e; + unsigned int reserved16; + unsigned int gpio1a_e; + unsigned int gpio1b_e; + unsigned int gpio1c_e; + unsigned int gpio1d_e; + unsigned int gpio2a_e; + unsigned int gpio2b_e; + unsigned int gpio2c_e; + unsigned int reserved17; + unsigned int gpio3a_e; + unsigned int gpio3b_e; + unsigned int reserved18[2]; + unsigned int gpio4a_e; + unsigned int gpio4b_e; + unsigned int gpio4c_e; + unsigned int gpio4d_e; + unsigned int gpio0a_sr; + unsigned int gpio0b_sr; + unsigned int gpio0c_sr; + unsigned int reserved19; + unsigned int gpio1a_sr; + unsigned int gpio1b_sr; + unsigned int gpio1c_sr; + unsigned int gpio1d_sr; + unsigned int gpio2a_sr; + unsigned int gpio2b_sr; + unsigned int gpio2c_sr; + unsigned int reserved20; + unsigned int gpio3a_sr; + unsigned int gpio3b_sr; + unsigned int reserved21[2]; + unsigned int gpio4a_sr; + unsigned int gpio4b_sr; + unsigned int gpio4c_sr; + unsigned int gpio4d_sr; + unsigned int gpio0a_smt; + unsigned int gpio0b_smt; + unsigned int gpio0c_smt; + unsigned int reserved22; + unsigned int gpio1a_smt; + unsigned int gpio1b_smt; + unsigned int gpio1c_smt; + unsigned int gpio1d_smt; + unsigned int gpio2a_smt; + unsigned int gpio2b_smt; + unsigned int gpio2c_smt; + unsigned int reserved23; + unsigned int gpio3a_smt; + unsigned int gpio3b_smt; + unsigned int reserved35[2]; + unsigned int gpio4a_smt; + unsigned int gpio4b_smt; + unsigned int gpio4c_smt; + unsigned int gpio4d_smt; + unsigned int reserved24[(0x300 - 0x1EC) / 4 - 1]; + unsigned int soc_con0; + unsigned int soc_con1; + unsigned int soc_con2; + unsigned int soc_con3; + unsigned int soc_con4; + unsigned int soc_con5; + unsigned int soc_con6; + unsigned int soc_con7; + unsigned int soc_con8; + unsigned int soc_con9; + unsigned int soc_con10; + unsigned int reserved25[(0x380 - 0x328) / 4 - 1]; + unsigned int soc_status0; + unsigned int reserved26[(0x400 - 0x380) / 4 - 1]; + unsigned int cpu_con0; + unsigned int cpu_con1; + unsigned int cpu_con2; + unsigned int reserved27[(0x420 - 0x408) / 4 - 1]; + unsigned int cpu_status0; + unsigned int cpu_status1; + unsigned int reserved28[(0x440 - 0x424) / 4 - 1]; + unsigned int pvtm_con0; + unsigned int pvtm_con1; + unsigned int pvtm_status0; + unsigned int pvtm_status1; + unsigned int reserved29[(0x460 - 0x44C) / 4 - 1]; + unsigned int tsadc_tbl; + unsigned int tsadc_tbh; + unsigned int reserved30[(0x480 - 0x464) / 4 - 1]; + unsigned int host0_con0; + unsigned int host0_con1; + unsigned int otg_con0; + unsigned int host0_status0; + unsigned int reserved31[(0x4a0 - 0x48C) / 4 - 1]; + unsigned int mac_con0; + unsigned int upctrl_con0; + unsigned int upctrl_status0; + unsigned int reserved32[(0x500 - 0x4A8) / 4 - 1]; + unsigned int os_reg0; + unsigned int os_reg1; + unsigned int os_reg2; + unsigned int os_reg3; + unsigned int os_reg4; + unsigned int os_reg5; + unsigned int os_reg6; + unsigned int os_reg7; + unsigned int os_reg8; + unsigned int os_reg9; + unsigned int os_reg10; + unsigned int os_reg11; + unsigned int reserved38[(0x600 - 0x52c) / 4 - 1]; + unsigned int soc_con12; + unsigned int reserved39; + unsigned int soc_con13; + unsigned int soc_con14; + unsigned int soc_con15; + unsigned int reserved40[(0x800 - 0x610) / 4 - 1]; + unsigned int chip_id; +}; +check_member(rk3308_grf, gpio0a_p, 0xa0); + +struct rk3308_sgrf { + unsigned int soc_con0; + unsigned int soc_con1; + unsigned int con_tzma_r0size; + unsigned int con_secure0; + unsigned int reserved0; + unsigned int clk_timer_en; + unsigned int clkgat_con; + unsigned int fastboot_addr; + unsigned int fastboot_en; + unsigned int reserved1[(0x30 - 0x24) / 4]; + unsigned int srst_con; +}; +check_member(rk3308_sgrf, fastboot_en, 0x20); + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 0eb19ca86f2..8f7fc86a9eb 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -9,6 +9,7 @@ /* define pll mode */ #define RKCLK_PLL_MODE_SLOW 0 #define RKCLK_PLL_MODE_NORMAL 1 +#define RKCLK_PLL_MODE_DEEP 2 enum { ROCKCHIP_SYSCON_NOC, @@ -33,6 +34,81 @@ enum rk_clk_id { CLK_COUNT, }; +#define PLL(_type, _id, _con, _mode, _mshift, \ + _lshift, _pflags, _rtable) \ + { \ + .id = _id, \ + .type = _type, \ + .con_offset = _con, \ + .mode_offset = _mode, \ + .mode_shift = _mshift, \ + .lock_shift = _lshift, \ + .pll_flags = _pflags, \ + .rate_table = _rtable, \ + } + +#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ + _postdiv2, _dsmpd, _frac) \ +{ \ + .rate = _rate##U, \ + .fbdiv = _fbdiv, \ + .postdiv1 = _postdiv1, \ + .refdiv = _refdiv, \ + .postdiv2 = _postdiv2, \ + .dsmpd = _dsmpd, \ + .frac = _frac, \ +} + +struct rockchip_pll_rate_table { + unsigned long rate; + unsigned int nr; + unsigned int nf; + unsigned int no; + unsigned int nb; + /* for RK3036/RK3399 */ + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; +}; + +enum rockchip_pll_type { + pll_rk3036, + pll_rk3066, + pll_rk3328, + pll_rk3366, + pll_rk3399, +}; + +struct rockchip_pll_clock { + unsigned int id; + unsigned int con_offset; + unsigned int mode_offset; + unsigned int mode_shift; + unsigned int lock_shift; + enum rockchip_pll_type type; + unsigned int pll_flags; + struct rockchip_pll_rate_table *rate_table; + unsigned int mode_mask; +}; + +struct rockchip_cpu_rate_table { + unsigned long rate; + unsigned int aclk_div; + unsigned int pclk_div; +}; + +int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, + void __iomem *base, ulong clk_id, + ulong drate); +ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, + void __iomem *base, ulong clk_id); +const struct rockchip_cpu_rate_table * +rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table, + ulong rate); + static inline int rk_pll_id(enum rk_clk_id clk_id) { return clk_id - 1; @@ -43,12 +119,6 @@ struct sysreset_reg { unsigned int glb_srst_snd_value; }; -struct softreset_reg { - void __iomem *base; - unsigned int sf_reset_offset; - unsigned int sf_reset_num; -}; - /** * clk_get_divisor() - Calculate the required clock divisior * diff --git a/arch/arm/include/asm/arch-rockchip/cru_px30.h b/arch/arm/include/asm/arch-rockchip/cru_px30.h new file mode 100644 index 00000000000..7d9fd181aca --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_px30.h @@ -0,0 +1,432 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + */ +#ifndef _ASM_ARCH_CRU_PX30_H +#define _ASM_ARCH_CRU_PX30_H + +#include <common.h> + +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) + +#define APLL_HZ (600 * MHz) +#define GPLL_HZ (1200 * MHz) +#define NPLL_HZ (1188 * MHz) +#define ACLK_BUS_HZ (200 * MHz) +#define HCLK_BUS_HZ (150 * MHz) +#define PCLK_BUS_HZ (100 * MHz) +#define ACLK_PERI_HZ (200 * MHz) +#define HCLK_PERI_HZ (150 * MHz) +#define PCLK_PMU_HZ (100 * MHz) + +/* PX30 pll id */ +enum px30_pll_id { + APLL, + DPLL, + CPLL, + NPLL, + GPLL, + PLL_COUNT, +}; + +struct px30_clk_priv { + struct px30_cru *cru; + ulong gpll_hz; +}; + +struct px30_pmuclk_priv { + struct px30_pmucru *pmucru; + ulong gpll_hz; +}; + +struct px30_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int reserved0[3]; +}; + +struct px30_cru { + struct px30_pll pll[4]; + unsigned int reserved1[8]; + unsigned int mode; + unsigned int misc; + unsigned int reserved2[2]; + unsigned int glb_cnt_th; + unsigned int glb_rst_st; + unsigned int glb_srst_fst; + unsigned int glb_srst_snd; + unsigned int glb_rst_con; + unsigned int reserved3[7]; + unsigned int hwffc_con0; + unsigned int reserved4; + unsigned int hwffc_th; + unsigned int hwffc_intst; + unsigned int apll_con0_s; + unsigned int apll_con1_s; + unsigned int clksel_con0_s; + unsigned int reserved5; + unsigned int clksel_con[60]; + unsigned int reserved6[4]; + unsigned int clkgate_con[18]; + unsigned int reserved7[(0x280 - 0x244) / 4 - 1]; + unsigned int ssgtbl[32]; + unsigned int softrst_con[12]; + unsigned int reserved8[(0x380 - 0x32c) / 4 - 1]; + unsigned int sdmmc_con[2]; + unsigned int sdio_con[2]; + unsigned int emmc_con[2]; + unsigned int reserved9[(0x400 - 0x394) / 4 - 1]; + unsigned int autocs_con[8]; +}; + +check_member(px30_cru, autocs_con[7], 0x41c); + +struct px30_pmucru { + struct px30_pll pll; + unsigned int pmu_mode; + unsigned int reserved1[7]; + unsigned int pmu_clksel_con[6]; + unsigned int reserved2[10]; + unsigned int pmu_clkgate_con[2]; + unsigned int reserved3[14]; + unsigned int pmu_autocs_con[2]; +}; + +check_member(px30_pmucru, pmu_autocs_con[1], 0xc4); + +struct pll_rate_table { + unsigned long rate; + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; +}; + +struct cpu_rate_table { + unsigned long rate; + unsigned int aclk_div; + unsigned int pclk_div; +}; + +enum { + /* PLLCON0*/ + PLL_BP_SHIFT = 15, + PLL_POSTDIV1_SHIFT = 12, + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, + PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, + + /* PLLCON1 */ + PLL_PDSEL_SHIFT = 15, + PLL_PD1_SHIFT = 14, + PLL_PD_SHIFT = 13, + PLL_PD_MASK = 1 << PLL_PD_SHIFT, + PLL_DSMPD_SHIFT = 12, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, + PLL_POSTDIV2_SHIFT = 6, + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, + PLL_REFDIV_SHIFT = 0, + PLL_REFDIV_MASK = 0x3f, + + /* PLLCON2 */ + PLL_FOUT4PHASEPD_SHIFT = 27, + PLL_FOUTVCOPD_SHIFT = 26, + PLL_FOUTPOSTDIVPD_SHIFT = 25, + PLL_DACPD_SHIFT = 24, + PLL_FRAC_DIV = 0xffffff, + + /* CRU_MODE */ + PLLMUX_FROM_XIN24M = 0, + PLLMUX_FROM_PLL, + PLLMUX_FROM_RTC32K, + USBPHY480M_MODE_SHIFT = 8, + USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, + NPLL_MODE_SHIFT = 6, + NPLL_MODE_MASK = 3 << NPLL_MODE_SHIFT, + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, + CPLL_MODE_SHIFT = 2, + CPLL_MODE_MASK = 3 << CPLL_MODE_SHIFT, + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, + + /* CRU_CLK_SEL0_CON */ + CORE_ACLK_DIV_SHIFT = 12, + CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, + CORE_DBG_DIV_SHIFT = 8, + CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT, + CORE_CLK_PLL_SEL_SHIFT = 7, + CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_GPLL, + CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, + + /* CRU_CLK_SEL3_CON */ + ACLK_VO_PLL_SHIFT = 6, + ACLK_VO_PLL_MASK = 0x3 << ACLK_VO_PLL_SHIFT, + ACLK_VO_SEL_GPLL = 0, + ACLK_VO_SEL_CPLL, + ACLK_VO_SEL_NPLL, + ACLK_VO_DIV_SHIFT = 0, + ACLK_VO_DIV_MASK = 0x1f << ACLK_VO_DIV_SHIFT, + + /* CRU_CLK_SEL5_CON */ + DCLK_VOPB_SEL_SHIFT = 14, + DCLK_VOPB_SEL_MASK = 0x3 << DCLK_VOPB_SEL_SHIFT, + DCLK_VOPB_SEL_DIVOUT = 0, + DCLK_VOPB_SEL_FRACOUT, + DCLK_VOPB_SEL_24M, + DCLK_VOPB_PLL_SEL_SHIFT = 11, + DCLK_VOPB_PLL_SEL_MASK = 0x1 << DCLK_VOPB_PLL_SEL_SHIFT, + DCLK_VOPB_PLL_SEL_CPLL = 0, + DCLK_VOPB_PLL_SEL_NPLL, + DCLK_VOPB_DIV_SHIFT = 0, + DCLK_VOPB_DIV_MASK = 0xff, + + /* CRU_CLK_SEL8_CON */ + DCLK_VOPL_SEL_SHIFT = 14, + DCLK_VOPL_SEL_MASK = 0x3 << DCLK_VOPL_SEL_SHIFT, + DCLK_VOPL_SEL_DIVOUT = 0, + DCLK_VOPL_SEL_FRACOUT, + DCLK_VOPL_SEL_24M, + DCLK_VOPL_PLL_SEL_SHIFT = 11, + DCLK_VOPL_PLL_SEL_MASK = 0x1 << DCLK_VOPL_PLL_SEL_SHIFT, + DCLK_VOPL_PLL_SEL_NPLL = 0, + DCLK_VOPL_PLL_SEL_CPLL, + DCLK_VOPL_DIV_SHIFT = 0, + DCLK_VOPL_DIV_MASK = 0xff, + + /* CRU_CLK_SEL14_CON */ + PERI_PLL_SEL_SHIFT = 15, + PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, + PERI_PLL_GPLL = 0, + PERI_PLL_CPLL, + PERI_HCLK_DIV_SHIFT = 8, + PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, + + /* CRU_CLKSEL15_CON */ + NANDC_CLK_SEL_SHIFT = 15, + NANDC_CLK_SEL_MASK = 0x1 << NANDC_CLK_SEL_SHIFT, + NANDC_CLK_SEL_NANDC = 0, + NANDC_CLK_SEL_NANDC_DIV50, + NANDC_DIV50_SHIFT = 8, + NANDC_DIV50_MASK = 0x1f << NANDC_DIV50_SHIFT, + NANDC_PLL_SHIFT = 6, + NANDC_PLL_MASK = 0x3 << NANDC_PLL_SHIFT, + NANDC_SEL_GPLL = 0, + NANDC_SEL_CPLL, + NANDC_SEL_NPLL, + NANDC_DIV_SHIFT = 0, + NANDC_DIV_MASK = 0x1f << NANDC_DIV_SHIFT, + + /* CRU_CLKSEL20_CON */ + EMMC_PLL_SHIFT = 14, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, + EMMC_SEL_GPLL = 0, + EMMC_SEL_CPLL, + EMMC_SEL_NPLL, + EMMC_SEL_24M, + EMMC_DIV_SHIFT = 0, + EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, + + /* CRU_CLKSEL21_CON */ + EMMC_CLK_SEL_SHIFT = 15, + EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, + EMMC_CLK_SEL_EMMC = 0, + EMMC_CLK_SEL_EMMC_DIV50, + EMMC_DIV50_SHIFT = 0, + EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT, + + /* CRU_CLKSEL22_CON */ + GMAC_PLL_SEL_SHIFT = 14, + GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT, + GMAC_PLL_SEL_GPLL = 0, + GMAC_PLL_SEL_CPLL, + GMAC_PLL_SEL_NPLL, + CLK_GMAC_DIV_SHIFT = 8, + CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT, + SFC_PLL_SEL_SHIFT = 7, + SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, + SFC_DIV_CON_SHIFT = 0, + SFC_DIV_CON_MASK = 0x7f, + + /* CRU_CLK_SEL23_CON */ + BUS_PLL_SEL_SHIFT = 15, + BUS_PLL_SEL_MASK = 1 << BUS_PLL_SEL_SHIFT, + BUS_PLL_SEL_GPLL = 0, + BUS_PLL_SEL_CPLL, + BUS_ACLK_DIV_SHIFT = 8, + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, + RMII_CLK_SEL_SHIFT = 7, + RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT, + RMII_CLK_SEL_10M = 0, + RMII_CLK_SEL_100M, + RMII_EXTCLK_SEL_SHIFT = 6, + RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, + RMII_EXTCLK_SEL_INT = 0, + RMII_EXTCLK_SEL_EXT, + PCLK_GMAC_DIV_SHIFT = 0, + PCLK_GMAC_DIV_MASK = 0x0f << PCLK_GMAC_DIV_SHIFT, + + /* CRU_CLK_SEL24_CON */ + BUS_PCLK_DIV_SHIFT = 8, + BUS_PCLK_DIV_MASK = 3 << BUS_PCLK_DIV_SHIFT, + BUS_HCLK_DIV_SHIFT = 0, + BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, + + /* CRU_CLK_SEL25_CON */ + CRYPTO_APK_SEL_SHIFT = 14, + CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT, + CRYPTO_PLL_SEL_GPLL = 0, + CRYPTO_PLL_SEL_CPLL, + CRYPTO_PLL_SEL_NPLL = 0, + CRYPTO_APK_DIV_SHIFT = 8, + CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT, + CRYPTO_PLL_SEL_SHIFT = 6, + CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT, + CRYPTO_DIV_SHIFT = 0, + CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT, + + /* CRU_CLK_SEL30_CON */ + CLK_I2S1_DIV_CON_MASK = 0x7f, + CLK_I2S1_PLL_SEL_MASK = 0X1 << 8, + CLK_I2S1_PLL_SEL_GPLL = 0X0 << 8, + CLK_I2S1_PLL_SEL_NPLL = 0X1 << 8, + CLK_I2S1_SEL_MASK = 0x3 << 10, + CLK_I2S1_SEL_I2S1 = 0x0 << 10, + CLK_I2S1_SEL_FRAC = 0x1 << 10, + CLK_I2S1_SEL_MCLK_IN = 0x2 << 10, + CLK_I2S1_SEL_OSC = 0x3 << 10, + CLK_I2S1_OUT_SEL_MASK = 0x1 << 15, + CLK_I2S1_OUT_SEL_I2S1 = 0x0 << 15, + CLK_I2S1_OUT_SEL_OSC = 0x1 << 15, + + /* CRU_CLK_SEL31_CON */ + CLK_I2S1_FRAC_NUMERATOR_SHIFT = 16, + CLK_I2S1_FRAC_NUMERATOR_MASK = 0xffff << 16, + CLK_I2S1_FRAC_DENOMINATOR_SHIFT = 0, + CLK_I2S1_FRAC_DENOMINATOR_MASK = 0xffff, + + /* CRU_CLK_SEL34_CON */ + UART1_PLL_SEL_SHIFT = 14, + UART1_PLL_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT, + UART1_PLL_SEL_GPLL = 0, + UART1_PLL_SEL_24M, + UART1_PLL_SEL_480M, + UART1_PLL_SEL_NPLL, + UART1_DIV_CON_SHIFT = 0, + UART1_DIV_CON_MASK = 0x1f << UART1_DIV_CON_SHIFT, + + /* CRU_CLK_SEL35_CON */ + UART1_CLK_SEL_SHIFT = 14, + UART1_CLK_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT, + UART1_CLK_SEL_UART1 = 0, + UART1_CLK_SEL_UART1_NP5, + UART1_CLK_SEL_UART1_FRAC, + UART1_DIVNP5_SHIFT = 0, + UART1_DIVNP5_MASK = 0x1f << UART1_DIVNP5_SHIFT, + + /* CRU_CLK_SEL37_CON */ + UART2_PLL_SEL_SHIFT = 14, + UART2_PLL_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT, + UART2_PLL_SEL_GPLL = 0, + UART2_PLL_SEL_24M, + UART2_PLL_SEL_480M, + UART2_PLL_SEL_NPLL, + UART2_DIV_CON_SHIFT = 0, + UART2_DIV_CON_MASK = 0x1f << UART2_DIV_CON_SHIFT, + + /* CRU_CLK_SEL38_CON */ + UART2_CLK_SEL_SHIFT = 14, + UART2_CLK_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT, + UART2_CLK_SEL_UART2 = 0, + UART2_CLK_SEL_UART2_NP5, + UART2_CLK_SEL_UART2_FRAC, + UART2_DIVNP5_SHIFT = 0, + UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT, + + /* CRU_CLK_SEL46_CON */ + UART5_PLL_SEL_SHIFT = 14, + UART5_PLL_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT, + UART5_PLL_SEL_GPLL = 0, + UART5_PLL_SEL_24M, + UART5_PLL_SEL_480M, + UART5_PLL_SEL_NPLL, + UART5_DIV_CON_SHIFT = 0, + UART5_DIV_CON_MASK = 0x1f << UART5_DIV_CON_SHIFT, + + /* CRU_CLK_SEL47_CON */ + UART5_CLK_SEL_SHIFT = 14, + UART5_CLK_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT, + UART5_CLK_SEL_UART5 = 0, + UART5_CLK_SEL_UART5_NP5, + UART5_CLK_SEL_UART5_FRAC, + UART5_DIVNP5_SHIFT = 0, + UART5_DIVNP5_MASK = 0x1f << UART5_DIVNP5_SHIFT, + + /* CRU_CLK_SEL49_CON */ + CLK_I2C_PLL_SEL_GPLL = 0, + CLK_I2C_PLL_SEL_24M, + CLK_I2C_DIV_CON_MASK = 0x7f, + CLK_I2C_PLL_SEL_MASK = 1, + CLK_I2C1_PLL_SEL_SHIFT = 15, + CLK_I2C1_DIV_CON_SHIFT = 8, + CLK_I2C0_PLL_SEL_SHIFT = 7, + CLK_I2C0_DIV_CON_SHIFT = 0, + + /* CRU_CLK_SEL50_CON */ + CLK_I2C3_PLL_SEL_SHIFT = 15, + CLK_I2C3_DIV_CON_SHIFT = 8, + CLK_I2C2_PLL_SEL_SHIFT = 7, + CLK_I2C2_DIV_CON_SHIFT = 0, + + /* CRU_CLK_SEL52_CON */ + CLK_PWM_PLL_SEL_GPLL = 0, + CLK_PWM_PLL_SEL_24M, + CLK_PWM_DIV_CON_MASK = 0x7f, + CLK_PWM_PLL_SEL_MASK = 1, + CLK_PWM1_PLL_SEL_SHIFT = 15, + CLK_PWM1_DIV_CON_SHIFT = 8, + CLK_PWM0_PLL_SEL_SHIFT = 7, + CLK_PWM0_DIV_CON_SHIFT = 0, + + /* CRU_CLK_SEL53_CON */ + CLK_SPI_PLL_SEL_GPLL = 0, + CLK_SPI_PLL_SEL_24M, + CLK_SPI_DIV_CON_MASK = 0x7f, + CLK_SPI_PLL_SEL_MASK = 1, + CLK_SPI1_PLL_SEL_SHIFT = 15, + CLK_SPI1_DIV_CON_SHIFT = 8, + CLK_SPI0_PLL_SEL_SHIFT = 7, + CLK_SPI0_DIV_CON_SHIFT = 0, + + /* CRU_CLK_SEL55_CON */ + CLK_SARADC_DIV_CON_SHIFT = 0, + CLK_SARADC_DIV_CON_MASK = 0x7ff, + + /* CRU_CLK_GATE10_CON */ + CLK_I2S1_OUT_MCLK_PAD_MASK = 0x1 << 9, + CLK_I2S1_OUT_MCLK_PAD_ENABLE = 0x1 << 9, + CLK_I2S1_OUT_MCLK_PAD_DISABLE = 0x0 << 9, + + /* CRU_PMU_MODE */ + GPLL_MODE_SHIFT = 0, + GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, + + /* CRU_PMU_CLK_SEL0_CON */ + CLK_PMU_PCLK_DIV_SHIFT = 0, + CLK_PMU_PCLK_DIV_MASK = 0x1f << CLK_PMU_PCLK_DIV_SHIFT, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_px30.h b/arch/arm/include/asm/arch-rockchip/grf_px30.h new file mode 100644 index 00000000000..c167bb42fac --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_px30.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + */ +#ifndef _ASM_ARCH_GRF_px30_H +#define _ASM_ARCH_GRF_px30_H + +#include <common.h> + +struct px30_grf { + unsigned int gpio1al_iomux; + unsigned int gpio1ah_iomux; + unsigned int gpio1bl_iomux; + unsigned int gpio1bh_iomux; + unsigned int gpio1cl_iomux; + unsigned int gpio1ch_iomux; + unsigned int gpio1dl_iomux; + unsigned int gpio1dh_iomux; + + unsigned int gpio2al_iomux; + unsigned int gpio2ah_iomux; + unsigned int gpio2bl_iomux; + unsigned int gpio2bh_iomux; + unsigned int gpio2cl_iomux; + unsigned int gpio2ch_iomux; + unsigned int gpio2dl_iomux; + unsigned int gpio2dh_iomux; + + unsigned int gpio3al_iomux; + unsigned int gpio3ah_iomux; + unsigned int gpio3bl_iomux; + unsigned int gpio3bh_iomux; + unsigned int gpio3cl_iomux; + unsigned int gpio3ch_iomux; + unsigned int gpio3dl_iomux; + unsigned int gpio3dh_iomux; + + unsigned int gpio1a_p; + unsigned int gpio1b_p; + unsigned int gpio1c_p; + unsigned int gpio1d_p; + unsigned int gpio2a_p; + unsigned int gpio2b_p; + unsigned int gpio2c_p; + unsigned int gpio2d_p; + unsigned int gpio3a_p; + unsigned int gpio3b_p; + unsigned int gpio3c_p; + unsigned int gpio3d_p; + unsigned int gpio1a_sr; + unsigned int gpio1b_sr; + unsigned int gpio1c_sr; + unsigned int gpio1d_sr; + unsigned int gpio2a_sr; + unsigned int gpio2b_sr; + unsigned int gpio2c_sr; + unsigned int gpio2d_sr; + unsigned int gpio3a_sr; + unsigned int gpio3b_sr; + unsigned int gpio3c_sr; + unsigned int gpio3d_sr; + unsigned int gpio1a_smt; + unsigned int gpio1b_smt; + unsigned int gpio1c_smt; + unsigned int gpio1d_smt; + unsigned int gpio2a_smt; + unsigned int gpio2b_smt; + unsigned int gpio2c_smt; + unsigned int gpio2d_smt; + unsigned int gpio3a_smt; + unsigned int gpio3b_smt; + unsigned int gpio3c_smt; + unsigned int gpio3d_smt; + unsigned int gpio1a_e; + unsigned int gpio1b_e; + unsigned int gpio1c_e; + unsigned int gpio1d_e; + unsigned int gpio2a_e; + unsigned int gpio2b_e; + unsigned int gpio2c_e; + unsigned int gpio2d_e; + unsigned int gpio3a_e; + unsigned int gpio3b_e; + unsigned int gpio3c_e; + unsigned int gpio3d_e; + + unsigned int reserved0[(0x180 - 0x11C) / 4 - 1]; + unsigned int io_vsel; + unsigned int iofunc_con0; + unsigned int reserved1[(0x400 - 0x184) / 4 - 1]; + unsigned int soc_con[6]; + unsigned int reserved2[(0x480 - 0x414) / 4 - 1]; + unsigned int soc_status0; + unsigned int reserved3[(0x500 - 0x480) / 4 - 1]; + unsigned int cpu_con[3]; + unsigned int reserved4[5]; + unsigned int cpu_status[2]; + unsigned int reserved5[2]; + unsigned int soc_noc_con[2]; + unsigned int reserved6[6]; + unsigned int ddr_bankhash[4]; + unsigned int reserved7[(0x700 - 0x55c) / 4 - 1]; + unsigned int host0_con[2]; + unsigned int reserved8[(0x880 - 0x704) / 4 - 1]; + unsigned int otg_con3; + unsigned int reserved9[3]; + unsigned int host0_status4; + unsigned int reserved10[(0x904 - 0x890) / 4 - 1]; + unsigned int mac_con1; +}; + +check_member(px30_grf, mac_con1, 0x904); + +struct px30_pmugrf { + unsigned int gpio0a_e; + unsigned int gpio0b_e; + unsigned int gpio0c_e; + unsigned int gpio0d_e; + unsigned int gpio0a_p; + unsigned int gpio0b_p; + unsigned int gpio0c_p; + unsigned int gpio0d_p; + unsigned int gpio0al_iomux; + unsigned int gpio0bl_iomux; + unsigned int gpio0cl_iomux; + unsigned int gpio0dl_iomux; + unsigned int gpio0l_sr; + unsigned int gpio0h_sr; + unsigned int gpio0l_smt; + unsigned int gpio0h_smt; + unsigned int reserved1[(0x100 - 0x3c) / 4 - 1]; + unsigned int soc_con[4]; + unsigned int reserved2[(0x180 - 0x10c) / 4 - 1]; + unsigned int pvtm_con[2]; + unsigned int reserved3[2]; + unsigned int pvtm_status[2]; + unsigned int reserved4[(0x200 - 0x194) / 4 - 1]; + unsigned int os_reg[12]; + unsigned int reset_function_status; +}; + +check_member(px30_pmugrf, reset_function_status, 0x230); + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h index 9220763fa7f..cf2a7b7d105 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram.h +++ b/arch/arm/include/asm/arch-rockchip/sdram.h @@ -1,102 +1,86 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (c) 2015 Google, Inc - * - * Copyright 2014 Rockchip Inc. + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. */ -#ifndef _ASM_ARCH_RK3288_SDRAM_H__ -#define _ASM_ARCH_RK3288_SDRAM_H__ +#ifndef _ASM_ARCH_SDRAM_H +#define _ASM_ARCH_SDRAM_H -struct rk3288_sdram_channel { - /* - * bit width in address, eg: - * 8 banks using 3 bit to address, - * 2 cs using 1 bit to address. - */ - u8 rank; - u8 col; - u8 bk; - u8 bw; - u8 dbw; - u8 row_3_4; - u8 cs0_row; - u8 cs1_row; -#if CONFIG_IS_ENABLED(OF_PLATDATA) - /* - * For of-platdata, which would otherwise convert this into two - * byte-swapped integers. With a size of 9 bytes, this struct will - * appear in of-platdata as a byte array. - * - * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) - */ - u8 dummy; -#endif +enum { + DDR4 = 0, + DDR3 = 0x3, + LPDDR2 = 0x5, + LPDDR3 = 0x6, + LPDDR4 = 0x7, + UNUSED = 0xFF }; -struct rk3288_sdram_pctl_timing { - u32 togcnt1u; - u32 tinit; - u32 trsth; - u32 togcnt100n; - u32 trefi; - u32 tmrd; - u32 trfc; - u32 trp; - u32 trtw; - u32 tal; - u32 tcl; - u32 tcwl; - u32 tras; - u32 trc; - u32 trcd; - u32 trrd; - u32 trtp; - u32 twr; - u32 twtr; - u32 texsr; - u32 txp; - u32 txpdll; - u32 tzqcs; - u32 tzqcsi; - u32 tdqs; - u32 tcksre; - u32 tcksrx; - u32 tcke; - u32 tmod; - u32 trstl; - u32 tzqcl; - u32 tmrr; - u32 tckesr; - u32 tdpd; -}; -check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0); +/* + * sys_reg2 bitfield struct + * [31] row_3_4_ch1 + * [30] row_3_4_ch0 + * [29:28] chinfo + * [27] rank_ch1 + * [26:25] col_ch1 + * [24] bk_ch1 + * [23:22] low bits of cs0_row_ch1 + * [21:20] low bits of cs1_row_ch1 + * [19:18] bw_ch1 + * [17:16] dbw_ch1; + * [15:13] ddrtype + * [12] channelnum + * [11] rank_ch0 + * [10:9] col_ch0, + * [8] bk_ch0 + * [7:6] low bits of cs0_row_ch0 + * [5:4] low bits of cs1_row_ch0 + * [3:2] bw_ch0 + * [1:0] dbw_ch0 + */ +#define SYS_REG_DDRTYPE_SHIFT 13 +#define SYS_REG_DDRTYPE_MASK 7 +#define SYS_REG_NUM_CH_SHIFT 12 +#define SYS_REG_NUM_CH_MASK 1 +#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) +#define SYS_REG_ROW_3_4_MASK 1 +#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) +#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) +#define SYS_REG_RANK_MASK 1 +#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) +#define SYS_REG_COL_MASK 3 +#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) +#define SYS_REG_BK_MASK 1 +#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) +#define SYS_REG_CS0_ROW_MASK 3 +#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) +#define SYS_REG_CS1_ROW_MASK 3 +#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) +#define SYS_REG_BW_MASK 3 +#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) +#define SYS_REG_DBW_MASK 3 -struct rk3288_sdram_phy_timing { - u32 dtpr0; - u32 dtpr1; - u32 dtpr2; - u32 mr[4]; -}; +/* + * sys_reg3 bitfield struct + * [7] high bit of cs0_row_ch1 + * [6] high bit of cs1_row_ch1 + * [5] high bit of cs0_row_ch0 + * [4] high bit of cs1_row_ch0 + * [3:2] cs1_col_ch1 + * [1:0] cs1_col_ch0 + */ +#define SYS_REG_VERSION_SHIFT 28 +#define SYS_REG_VERSION_MASK 0xf +#define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) +#define SYS_REG_EXTEND_CS0_ROW_MASK 1 +#define SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) (4 + (ch) * 2) +#define SYS_REG_EXTEND_CS1_ROW_MASK 1 +#define SYS_REG_CS1_COL_SHIFT(ch) (0 + (ch) * 2) +#define SYS_REG_CS1_COL_MASK 3 -struct rk3288_base_params { - u32 noc_timing; - u32 noc_activate; - u32 ddrconfig; - u32 ddr_freq; - u32 dramtype; - /* - * DDR Stride is address mapping for DRAM space - * Stride Ch 0 range Ch1 range Total - * 0x00 0-256MB 256MB-512MB 512MB - * 0x05 0-1GB 0-1GB 1GB - * 0x09 0-2GB 0-2GB 2GB - * 0x0d 0-4GB 0-4GB 4GB - * 0x17 N/A 0-4GB 4GB - * 0x1a 0-4GB 4GB-8GB 8GB - */ - u32 stride; - u32 odt; -}; +/* Get sdram size decode from reg */ +size_t rockchip_sdram_size(phys_addr_t reg); + +/* Called by U-Boot board_init_r for Rockchip SoCs */ +int dram_init(void); #endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 8027b53636a..36d31156be2 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -1,19 +1,19 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + * Copyright (C) 2018 Rockchip Electronics Co., Ltd */ #ifndef _ASM_ARCH_SDRAM_COMMON_H #define _ASM_ARCH_SDRAM_COMMON_H -enum { - DDR4 = 0, - DDR3 = 0x3, - LPDDR2 = 0x5, - LPDDR3 = 0x6, - LPDDR4 = 0x7, - UNUSED = 0xFF -}; +#ifndef MHZ +#define MHZ (1000 * 1000) +#endif + +#define PATTERN (0x5aa5f00f) + +#define MIN(a, b) (((a) > (b)) ? (b) : (a)) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) struct sdram_cap_info { unsigned int rank; @@ -32,6 +32,8 @@ struct sdram_cap_info { unsigned int row_3_4; unsigned int cs0_row; unsigned int cs1_row; + unsigned int cs0_high16bit_row; + unsigned int cs1_high16bit_row; unsigned int ddrconfig; }; @@ -43,8 +45,9 @@ struct sdram_base_params { unsigned int odt; }; +#define DDR_SYS_REG_VERSION (0x2) /* - * sys_reg bitfield struct + * sys_reg2 bitfield struct * [31] row_3_4_ch1 * [30] row_3_4_ch0 * [29:28] chinfo @@ -64,49 +67,38 @@ struct sdram_base_params { * [5:4] cs1_row_ch0 * [3:2] bw_ch0 * [1:0] dbw_ch0 -*/ -#define SYS_REG_DDRTYPE_SHIFT 13 -#define DDR_SYS_REG_VERSION 2 -#define SYS_REG_DDRTYPE_MASK 7 -#define SYS_REG_NUM_CH_SHIFT 12 -#define SYS_REG_NUM_CH_MASK 1 -#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) -#define SYS_REG_ROW_3_4_MASK 1 + */ #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) -#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) -#define SYS_REG_ENC_CHINFO(ch) (1 << SYS_REG_CHINFO_SHIFT(ch)) -#define SYS_REG_ENC_DDRTYPE(n) ((n) << SYS_REG_DDRTYPE_SHIFT) -#define SYS_REG_ENC_NUM_CH(n) (((n) - SYS_REG_NUM_CH_MASK) << \ - SYS_REG_NUM_CH_SHIFT) -#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) -#define SYS_REG_RANK_MASK 1 -#define SYS_REG_ENC_RANK(n, ch) (((n) - SYS_REG_RANK_MASK) << \ - SYS_REG_RANK_SHIFT(ch)) -#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) -#define SYS_REG_COL_MASK 3 -#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch)) -#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) -#define SYS_REG_BK_MASK 1 +#define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) +#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) +#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) +#define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) +#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) +#define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) +#define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16))) +#define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + 16 * (ch))) & 0x1)) +#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16))) +#define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + 16 * (ch))) & 0x3)) #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \ - SYS_REG_BK_SHIFT(ch)) -#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) -#define SYS_REG_CS0_ROW_MASK 3 -#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) -#define SYS_REG_CS1_ROW_MASK 3 -#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) -#define SYS_REG_BW_MASK 3 -#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch)) -#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) -#define SYS_REG_DBW_MASK 3 -#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch)) - + (8 + ((ch) * 16))) +#define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + 16 * (ch))) & 0x1)) +#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16))) +#define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + 16 * (ch))) & 0x3)) +#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16))) +#define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + 16 * (ch))) & 0x3)) +/* sys reg 3 */ #define SYS_REG_ENC_VERSION(n) ((n) << 28) +#define SYS_REG_DEC_VERSION(n) (((n) >> 28) & 0xf) #define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ (5 + 2 * (ch)); \ } while (0) +#define SYS_REG_DEC_CS0_ROW(os_reg2, os_reg3, ch) \ + ((((((os_reg2) >> (6 + 16 * (ch)) & 0x3) | \ + ((((os_reg3) >> (5 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12) + #define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \ (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \ (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \ @@ -115,14 +107,12 @@ struct sdram_base_params { (4 + 2 * (ch)); \ } while (0) -#define SYS_REG_CS1_COL_SHIFT(ch) (0 + 2 * (ch)) -#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch)) - -/* Get sdram size decode from reg */ -size_t rockchip_sdram_size(phys_addr_t reg); +#define SYS_REG_DEC_CS1_ROW(os_reg2, os_reg3, ch) \ + ((((((os_reg2) >> (4 + 16 * (ch)) & 0x3) | \ + ((((os_reg3) >> (4 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12) -/* Called by U-Boot board_init_r for Rockchip SoCs */ -int dram_init(void); +#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << (0 + 2 * (ch))) +#define SYS_REG_DEC_CS1_COL(n, ch) (9 + (((n) >> (0 + 2 * (ch))) & 0x3)) #if !defined(CONFIG_RAM_ROCKCHIP_DEBUG) inline void sdram_print_dram_type(unsigned char dramtype) @@ -144,4 +134,26 @@ void sdram_print_ddr_info(struct sdram_cap_info *cap_info, void sdram_print_stride(unsigned int stride); #endif /* CONFIG_RAM_ROCKCHIP_DEBUG */ +void sdram_org_config(struct sdram_cap_info *cap_info, + struct sdram_base_params *base, + u32 *p_os_reg2, u32 *p_os_reg3, u32 channel); + +int sdram_detect_bw(struct sdram_cap_info *cap_info); +int sdram_detect_cs(struct sdram_cap_info *cap_info); +int sdram_detect_col(struct sdram_cap_info *cap_info, + u32 coltmp); +int sdram_detect_bank(struct sdram_cap_info *cap_info, + u32 coltmp, u32 bktmp); +int sdram_detect_bg(struct sdram_cap_info *cap_info, + u32 coltmp); +int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type); +int sdram_detect_row(struct sdram_cap_info *cap_info, + u32 coltmp, u32 bktmp, u32 rowtmp); +int sdram_detect_row_3_4(struct sdram_cap_info *cap_info, + u32 coltmp, u32 bktmp); +int sdram_detect_high_row(struct sdram_cap_info *cap_info); +int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type); +u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type); +void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n); + #endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_msch.h b/arch/arm/include/asm/arch-rockchip/sdram_msch.h new file mode 100644 index 00000000000..cfb3d9cc869 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_msch.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef _ASM_ARCH_SDRAM_MSCH_H +#define _ASM_ARCH_SDRAM_MSCH_H + +union noc_ddrtiminga0 { + u32 d32; + struct { + unsigned acttoact : 6; + unsigned reserved0 : 2; + unsigned rdtomiss : 6; + unsigned reserved1 : 2; + unsigned wrtomiss : 6; + unsigned reserved2 : 2; + unsigned readlatency : 8; + } b; +}; + +union noc_ddrtimingb0 { + u32 d32; + struct { + unsigned rdtowr : 5; + unsigned reserved0 : 3; + unsigned wrtord : 5; + unsigned reserved1 : 3; + unsigned rrd : 4; + unsigned reserved2 : 4; + unsigned faw : 6; + unsigned reserved3 : 2; + } b; +}; + +union noc_ddrtimingc0 { + u32 d32; + struct { + unsigned burstpenalty : 4; + unsigned reserved0 : 4; + unsigned wrtomwr : 6; + unsigned reserved1 : 18; + } b; +}; + +union noc_devtodev0 { + u32 d32; + struct { + unsigned busrdtord : 3; + unsigned reserved0 : 1; + unsigned busrdtowr : 3; + unsigned reserved1 : 1; + unsigned buswrtord : 3; + unsigned reserved2 : 1; + unsigned buswrtowr : 3; + unsigned reserved3 : 17; + } b; +}; + +union noc_ddrmode { + u32 d32; + struct { + unsigned autoprecharge : 1; + unsigned bypassfiltering : 1; + unsigned fawbank : 1; + unsigned burstsize : 2; + unsigned mwrsize : 2; + unsigned reserved2 : 1; + unsigned forceorder : 8; + unsigned forceorderstate : 8; + unsigned reserved3 : 8; + } b; +}; + +union noc_ddr4timing { + u32 d32; + struct { + unsigned ccdl : 3; + unsigned wrtordl : 5; + unsigned rrdl : 4; + unsigned reserved1 : 20; + } b; +}; + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h b/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h new file mode 100644 index 00000000000..97818817389 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Rockchip Electronics Co., Ltd + */ + +#ifndef _ASM_ARCH_SDRAM_PCTL_PX30_H +#define _ASM_ARCH_SDRAM_PCTL_PX30_H +#include <asm/arch-rockchip/sdram_common.h> + +struct ddr_pctl_regs { + u32 pctl[30][2]; +}; + +/* ddr pctl registers define */ +#define DDR_PCTL2_MSTR 0x0 +#define DDR_PCTL2_STAT 0x4 +#define DDR_PCTL2_MSTR1 0x8 +#define DDR_PCTL2_MRCTRL0 0x10 +#define DDR_PCTL2_MRCTRL1 0x14 +#define DDR_PCTL2_MRSTAT 0x18 +#define DDR_PCTL2_MRCTRL2 0x1c +#define DDR_PCTL2_DERATEEN 0x20 +#define DDR_PCTL2_DERATEINT 0x24 +#define DDR_PCTL2_PWRCTL 0x30 +#define DDR_PCTL2_PWRTMG 0x34 +#define DDR_PCTL2_HWLPCTL 0x38 +#define DDR_PCTL2_RFSHCTL0 0x50 +#define DDR_PCTL2_RFSHCTL1 0x54 +#define DDR_PCTL2_RFSHCTL2 0x58 +#define DDR_PCTL2_RFSHCTL4 0x5c +#define DDR_PCTL2_RFSHCTL3 0x60 +#define DDR_PCTL2_RFSHTMG 0x64 +#define DDR_PCTL2_RFSHTMG1 0x68 +#define DDR_PCTL2_RFSHCTL5 0x6c +#define DDR_PCTL2_INIT0 0xd0 +#define DDR_PCTL2_INIT1 0xd4 +#define DDR_PCTL2_INIT2 0xd8 +#define DDR_PCTL2_INIT3 0xdc +#define DDR_PCTL2_INIT4 0xe0 +#define DDR_PCTL2_INIT5 0xe4 +#define DDR_PCTL2_INIT6 0xe8 +#define DDR_PCTL2_INIT7 0xec +#define DDR_PCTL2_DIMMCTL 0xf0 +#define DDR_PCTL2_RANKCTL 0xf4 +#define DDR_PCTL2_CHCTL 0xfc +#define DDR_PCTL2_DRAMTMG0 0x100 +#define DDR_PCTL2_DRAMTMG1 0x104 +#define DDR_PCTL2_DRAMTMG2 0x108 +#define DDR_PCTL2_DRAMTMG3 0x10c +#define DDR_PCTL2_DRAMTMG4 0x110 +#define DDR_PCTL2_DRAMTMG5 0x114 +#define DDR_PCTL2_DRAMTMG6 0x118 +#define DDR_PCTL2_DRAMTMG7 0x11c +#define DDR_PCTL2_DRAMTMG8 0x120 +#define DDR_PCTL2_DRAMTMG9 0x124 +#define DDR_PCTL2_DRAMTMG10 0x128 +#define DDR_PCTL2_DRAMTMG11 0x12c +#define DDR_PCTL2_DRAMTMG12 0x130 +#define DDR_PCTL2_DRAMTMG13 0x134 +#define DDR_PCTL2_DRAMTMG14 0x138 +#define DDR_PCTL2_DRAMTMG15 0x13c +#define DDR_PCTL2_DRAMTMG16 0x140 +#define DDR_PCTL2_ZQCTL0 0x180 +#define DDR_PCTL2_ZQCTL1 0x184 +#define DDR_PCTL2_ZQCTL2 0x188 +#define DDR_PCTL2_ZQSTAT 0x18c +#define DDR_PCTL2_DFITMG0 0x190 +#define DDR_PCTL2_DFITMG1 0x194 +#define DDR_PCTL2_DFILPCFG0 0x198 +#define DDR_PCTL2_DFILPCFG1 0x19c +#define DDR_PCTL2_DFIUPD0 0x1a0 +#define DDR_PCTL2_DFIUPD1 0x1a4 +#define DDR_PCTL2_DFIUPD2 0x1a8 +#define DDR_PCTL2_DFIMISC 0x1b0 +#define DDR_PCTL2_DFITMG2 0x1b4 +#define DDR_PCTL2_DFITMG3 0x1b8 +#define DDR_PCTL2_DFISTAT 0x1bc +#define DDR_PCTL2_DBICTL 0x1c0 +#define DDR_PCTL2_ADDRMAP0 0x200 +#define DDR_PCTL2_ADDRMAP1 0x204 +#define DDR_PCTL2_ADDRMAP2 0x208 +#define DDR_PCTL2_ADDRMAP3 0x20c +#define DDR_PCTL2_ADDRMAP4 0x210 +#define DDR_PCTL2_ADDRMAP5 0x214 +#define DDR_PCTL2_ADDRMAP6 0x218 +#define DDR_PCTL2_ADDRMAP7 0x21c +#define DDR_PCTL2_ADDRMAP8 0x220 +#define DDR_PCTL2_ADDRMAP9 0x224 +#define DDR_PCTL2_ADDRMAP10 0x228 +#define DDR_PCTL2_ADDRMAP11 0x22c +#define DDR_PCTL2_ODTCFG 0x240 +#define DDR_PCTL2_ODTMAP 0x244 +#define DDR_PCTL2_SCHED 0x250 +#define DDR_PCTL2_SCHED1 0x254 +#define DDR_PCTL2_PERFHPR1 0x25c +#define DDR_PCTL2_PERFLPR1 0x264 +#define DDR_PCTL2_PERFWR1 0x26c +#define DDR_PCTL2_DQMAP0 0x280 +#define DDR_PCTL2_DQMAP1 0x284 +#define DDR_PCTL2_DQMAP2 0x288 +#define DDR_PCTL2_DQMAP3 0x28c +#define DDR_PCTL2_DQMAP4 0x290 +#define DDR_PCTL2_DQMAP5 0x294 +#define DDR_PCTL2_DBG0 0x300 +#define DDR_PCTL2_DBG1 0x304 +#define DDR_PCTL2_DBGCAM 0x308 +#define DDR_PCTL2_DBGCMD 0x30c +#define DDR_PCTL2_DBGSTAT 0x310 +#define DDR_PCTL2_SWCTL 0x320 +#define DDR_PCTL2_SWSTAT 0x324 +#define DDR_PCTL2_POISONCFG 0x36c +#define DDR_PCTL2_POISONSTAT 0x370 +#define DDR_PCTL2_ADVECCINDEX 0x374 +#define DDR_PCTL2_ADVECCSTAT 0x378 +#define DDR_PCTL2_PSTAT 0x3fc +#define DDR_PCTL2_PCCFG 0x400 +#define DDR_PCTL2_PCFGR_n 0x404 +#define DDR_PCTL2_PCFGW_n 0x408 +#define DDR_PCTL2_PCTRL_n 0x490 + +/* PCTL2_MRSTAT */ +#define MR_WR_BUSY BIT(0) + +void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num); +int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg, + u32 dramtype); +int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate, + u32 dramtype); + +u32 pctl_dis_zqcs_aref(void __iomem *pctl_base); +void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq); + +u32 pctl_remodify_sdram_params(struct ddr_pctl_regs *pctl_regs, + struct sdram_cap_info *cap_info, + u32 dram_type); +int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs, + u32 sr_idle, u32 pd_idle); + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_phy_px30.h b/arch/arm/include/asm/arch-rockchip/sdram_phy_px30.h new file mode 100644 index 00000000000..c75a633c919 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_phy_px30.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Rockchip Electronics Co., Ltd + */ + +#ifndef _ASM_ARCH_SDRAM_PHY_PX30_H +#define _ASM_ARCH_SDRAM_PHY_PX30_H +#include <asm/arch-rockchip/sdram_common.h> +#include <asm/arch-rockchip/sdram_phy_ron_rtt_px30.h> + +struct ddr_phy_regs { + u32 phy[5][2]; +}; + +#define PHY_REG(base, n) ((base) + 4 * (n)) + +/* PHY_REG0 */ +#define DIGITAL_DERESET BIT(3) +#define ANALOG_DERESET BIT(2) +#define DIGITAL_RESET (0 << 3) +#define ANALOG_RESET (0 << 2) + +/* PHY_REG1 */ +#define PHY_DDR2 (0) +#define PHY_LPDDR2 (1) +#define PHY_DDR3 (2) +#define PHY_LPDDR3 (3) +#define PHY_DDR4 (4) +#define PHY_BL_4 (0 << 2) +#define PHY_BL_8 BIT(2) + +/* PHY_REG2 */ +#define PHY_DTT_EN BIT(0) +#define PHY_DTT_DISB (0 << 0) +#define PHY_WRITE_LEVELING_EN BIT(2) +#define PHY_WRITE_LEVELING_DISB (0 << 2) +#define PHY_SELECT_CS0 (2) +#define PHY_SELECT_CS1 (1) +#define PHY_SELECT_CS0_1 (0) +#define PHY_WRITE_LEVELING_SELECTCS(n) ((n) << 6) +#define PHY_DATA_TRAINING_SELECTCS(n) ((n) << 4) + +struct ddr_phy_skew { + u32 a0_a1_skew[15]; + u32 cs0_dm0_skew[11]; + u32 cs0_dm1_skew[11]; + u32 cs0_dm2_skew[11]; + u32 cs0_dm3_skew[11]; + u32 cs1_dm0_skew[11]; + u32 cs1_dm1_skew[11]; + u32 cs1_dm2_skew[11]; + u32 cs1_dm3_skew[11]; +}; + +void phy_soft_reset(void __iomem *phy_base); +void phy_dram_set_bw(void __iomem *phy_base, u32 bw); +void phy_cfg(void __iomem *phy_base, + struct ddr_phy_regs *phy_regs, struct ddr_phy_skew *skew, + struct sdram_base_params *base, u32 bw); +int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype); + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_phy_ron_rtt_px30.h b/arch/arm/include/asm/arch-rockchip/sdram_phy_ron_rtt_px30.h new file mode 100644 index 00000000000..9c15232047c --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_phy_ron_rtt_px30.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Rockchip Electronics Co., Ltd + */ + +#ifndef _ASM_ARCH_SDRAM_PHY_RON_RTT_PX30_H +#define _ASM_ARCH_SDRAM_PHY_RON_RTT_PX30_H + +#define PHY_DDR3_RON_RTT_DISABLE (0) +#define PHY_DDR3_RON_RTT_451ohm (1) +#define PHY_DDR3_RON_RTT_225ohm (2) +#define PHY_DDR3_RON_RTT_150ohm (3) +#define PHY_DDR3_RON_RTT_112ohm (4) +#define PHY_DDR3_RON_RTT_90ohm (5) +#define PHY_DDR3_RON_RTT_75ohm (6) +#define PHY_DDR3_RON_RTT_64ohm (7) +#define PHY_DDR3_RON_RTT_56ohm (16) +#define PHY_DDR3_RON_RTT_50ohm (17) +#define PHY_DDR3_RON_RTT_45ohm (18) +#define PHY_DDR3_RON_RTT_41ohm (19) +#define PHY_DDR3_RON_RTT_37ohm (20) +#define PHY_DDR3_RON_RTT_34ohm (21) +#define PHY_DDR3_RON_RTT_33ohm (22) +#define PHY_DDR3_RON_RTT_30ohm (23) +#define PHY_DDR3_RON_RTT_28ohm (24) +#define PHY_DDR3_RON_RTT_26ohm (25) +#define PHY_DDR3_RON_RTT_25ohm (26) +#define PHY_DDR3_RON_RTT_23ohm (27) +#define PHY_DDR3_RON_RTT_22ohm (28) +#define PHY_DDR3_RON_RTT_21ohm (29) +#define PHY_DDR3_RON_RTT_20ohm (30) +#define PHY_DDR3_RON_RTT_19ohm (31) + +#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0) +#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1) +#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2) +#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3) +#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4) +#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5) +#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6) +#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7) +#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16) +#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17) +#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18) +#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19) +#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20) +#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21) +#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22) +#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23) +#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24) +#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25) +#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26) +#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27) +#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28) +#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29) +#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30) +#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31) + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_px30.h b/arch/arm/include/asm/arch-rockchip/sdram_px30.h new file mode 100644 index 00000000000..2ab8e97ae1d --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_px30.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Rockchip Electronics Co., Ltd + */ + +#ifndef _ASM_ARCH_SDRAM_PX30_H +#define _ASM_ARCH_SDRAM_PX30_H +#include <asm/arch-rockchip/sdram_common.h> +#include <asm/arch-rockchip/sdram_msch.h> +#include <asm/arch-rockchip/sdram_pctl_px30.h> +#include <asm/arch-rockchip/sdram_phy_px30.h> +#include <asm/arch-rockchip/sdram_phy_ron_rtt_px30.h> + +#define SR_IDLE 93 +#define PD_IDLE 13 + +/* PMUGRF */ +#define PMUGRF_OS_REG0 (0x200) +#define PMUGRF_OS_REG(n) (PMUGRF_OS_REG0 + (n) * 4) + +/* DDR GRF */ +#define DDR_GRF_CON(n) (0 + (n) * 4) +#define DDR_GRF_STATUS_BASE (0X100) +#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) +#define DDR_GRF_LP_CON (0x20) + +#define SPLIT_MODE_32_L16_VALID (0) +#define SPLIT_MODE_32_H16_VALID (1) +#define SPLIT_MODE_16_L8_VALID (2) +#define SPLIT_MODE_16_H8_VALID (3) + +#define DDR_GRF_SPLIT_CON (0x8) +#define SPLIT_MODE_MASK (0x3) +#define SPLIT_MODE_OFFSET (9) +#define SPLIT_BYPASS_MASK (1) +#define SPLIT_BYPASS_OFFSET (8) +#define SPLIT_SIZE_MASK (0xff) +#define SPLIT_SIZE_OFFSET (0) + +/* CRU define */ +/* CRU_PLL_CON0 */ +#define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) +#define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) +#define FBDIV(n) ((0xFFF << 16) | (n)) + +/* CRU_PLL_CON1 */ +#define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15)) +#define RST(n) ((0x1 << (14 + 16)) | ((n) << 14)) +#define PD(n) ((0x1 << (13 + 16)) | ((n) << 13)) +#define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12)) +#define LOCK(n) (((n) >> 10) & 0x1) +#define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6)) +#define REFDIV(n) ((0x3F << 16) | (n)) + +/* CRU_MODE */ +#define CLOCK_FROM_XIN_OSC (0) +#define CLOCK_FROM_PLL (1) +#define CLOCK_FROM_RTC_32K (2) +#define DPLL_MODE(n) ((0x3 << (4 + 16)) | ((n) << 4)) + +/* CRU_SOFTRESET_CON1 */ +#define upctl2_psrstn_req(n) (((0x1 << 6) << 16) | ((n) << 6)) +#define upctl2_asrstn_req(n) (((0x1 << 5) << 16) | ((n) << 5)) +#define upctl2_srstn_req(n) (((0x1 << 4) << 16) | ((n) << 4)) + +/* CRU_SOFTRESET_CON2 */ +#define ddrphy_psrstn_req(n) (((0x1 << 2) << 16) | ((n) << 2)) +#define ddrphy_srstn_req(n) (((0x1 << 0) << 16) | ((n) << 0)) + +/* CRU register */ +#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) +#define CRU_MODE (0xa0) +#define CRU_GLB_CNT_TH (0xb0) +#define CRU_CLKSEL_CON_BASE 0x100 +#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4)) +#define CRU_CLKGATE_CON_BASE 0x200 +#define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4)) +#define CRU_CLKSFTRST_CON_BASE 0x300 +#define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4)) + +struct px30_ddr_grf_regs { + u32 ddr_grf_con[4]; + u32 reserved1[(0x20 - 0x10) / 4]; + u32 ddr_grf_lp_con; + u32 reserved2[(0x100 - 0x24) / 4]; + u32 ddr_grf_status[11]; +}; + +struct msch_regs { + u32 coreid; + u32 revisionid; + u32 deviceconf; + u32 devicesize; + u32 ddrtiminga0; + u32 ddrtimingb0; + u32 ddrtimingc0; + u32 devtodev0; + u32 reserved1[(0x110 - 0x20) / 4]; + u32 ddrmode; + u32 ddr4timing; + u32 reserved2[(0x1000 - 0x118) / 4]; + u32 agingx0; + u32 reserved3[(0x1040 - 0x1004) / 4]; + u32 aging0; + u32 aging1; + u32 aging2; + u32 aging3; +}; + +struct sdram_msch_timings { + union noc_ddrtiminga0 ddrtiminga0; + union noc_ddrtimingb0 ddrtimingb0; + union noc_ddrtimingc0 ddrtimingc0; + union noc_devtodev0 devtodev0; + union noc_ddrmode ddrmode; + union noc_ddr4timing ddr4timing; + u32 agingx0; +}; + +struct px30_sdram_channel { + struct sdram_cap_info cap_info; + struct sdram_msch_timings noc_timings; +}; + +struct px30_sdram_params { + struct px30_sdram_channel ch; + struct sdram_base_params base; + struct ddr_pctl_regs pctl_regs; + struct ddr_phy_regs phy_regs; + struct ddr_phy_skew *skew; +}; + +int sdram_init(void); +#endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3288.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3288.h new file mode 100644 index 00000000000..9220763fa7f --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3288.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2015 Google, Inc + * + * Copyright 2014 Rockchip Inc. + */ + +#ifndef _ASM_ARCH_RK3288_SDRAM_H__ +#define _ASM_ARCH_RK3288_SDRAM_H__ + +struct rk3288_sdram_channel { + /* + * bit width in address, eg: + * 8 banks using 3 bit to address, + * 2 cs using 1 bit to address. + */ + u8 rank; + u8 col; + u8 bk; + u8 bw; + u8 dbw; + u8 row_3_4; + u8 cs0_row; + u8 cs1_row; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + /* + * For of-platdata, which would otherwise convert this into two + * byte-swapped integers. With a size of 9 bytes, this struct will + * appear in of-platdata as a byte array. + * + * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) + */ + u8 dummy; +#endif +}; + +struct rk3288_sdram_pctl_timing { + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; +}; +check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0); + +struct rk3288_sdram_phy_timing { + u32 dtpr0; + u32 dtpr1; + u32 dtpr2; + u32 mr[4]; +}; + +struct rk3288_base_params { + u32 noc_timing; + u32 noc_activate; + u32 ddrconfig; + u32 ddr_freq; + u32 dramtype; + /* + * DDR Stride is address mapping for DRAM space + * Stride Ch 0 range Ch1 range Total + * 0x00 0-256MB 256MB-512MB 512MB + * 0x05 0-1GB 0-1GB 1GB + * 0x09 0-2GB 0-2GB 2GB + * 0x0d 0-4GB 0-4GB 4GB + * 0x17 N/A 0-4GB 4GB + * 0x1a 0-4GB 4GB-8GB 8GB + */ + u32 stride; + u32 odt; +}; + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h index 11411ead10b..10923505d6e 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h @@ -6,197 +6,14 @@ #ifndef _ASM_ARCH_SDRAM_RK3328_H #define _ASM_ARCH_SDRAM_RK3328_H +#include <asm/arch-rockchip/sdram_common.h> +#include <asm/arch-rockchip/sdram_pctl_px30.h> +#include <asm/arch-rockchip/sdram_phy_px30.h> +#include <asm/arch-rockchip/sdram_phy_ron_rtt_px30.h> #define SR_IDLE 93 #define PD_IDLE 13 #define SDRAM_ADDR 0x00000000 -#define PATTERN (0x5aa5f00f) - -/* ddr pctl registers define */ -#define DDR_PCTL2_MSTR 0x0 -#define DDR_PCTL2_STAT 0x4 -#define DDR_PCTL2_MSTR1 0x8 -#define DDR_PCTL2_MRCTRL0 0x10 -#define DDR_PCTL2_MRCTRL1 0x14 -#define DDR_PCTL2_MRSTAT 0x18 -#define DDR_PCTL2_MRCTRL2 0x1c -#define DDR_PCTL2_DERATEEN 0x20 -#define DDR_PCTL2_DERATEINT 0x24 -#define DDR_PCTL2_PWRCTL 0x30 -#define DDR_PCTL2_PWRTMG 0x34 -#define DDR_PCTL2_HWLPCTL 0x38 -#define DDR_PCTL2_RFSHCTL0 0x50 -#define DDR_PCTL2_RFSHCTL1 0x54 -#define DDR_PCTL2_RFSHCTL2 0x58 -#define DDR_PCTL2_RFSHCTL4 0x5c -#define DDR_PCTL2_RFSHCTL3 0x60 -#define DDR_PCTL2_RFSHTMG 0x64 -#define DDR_PCTL2_RFSHTMG1 0x68 -#define DDR_PCTL2_RFSHCTL5 0x6c -#define DDR_PCTL2_INIT0 0xd0 -#define DDR_PCTL2_INIT1 0xd4 -#define DDR_PCTL2_INIT2 0xd8 -#define DDR_PCTL2_INIT3 0xdc -#define DDR_PCTL2_INIT4 0xe0 -#define DDR_PCTL2_INIT5 0xe4 -#define DDR_PCTL2_INIT6 0xe8 -#define DDR_PCTL2_INIT7 0xec -#define DDR_PCTL2_DIMMCTL 0xf0 -#define DDR_PCTL2_RANKCTL 0xf4 -#define DDR_PCTL2_CHCTL 0xfc -#define DDR_PCTL2_DRAMTMG0 0x100 -#define DDR_PCTL2_DRAMTMG1 0x104 -#define DDR_PCTL2_DRAMTMG2 0x108 -#define DDR_PCTL2_DRAMTMG3 0x10c -#define DDR_PCTL2_DRAMTMG4 0x110 -#define DDR_PCTL2_DRAMTMG5 0x114 -#define DDR_PCTL2_DRAMTMG6 0x118 -#define DDR_PCTL2_DRAMTMG7 0x11c -#define DDR_PCTL2_DRAMTMG8 0x120 -#define DDR_PCTL2_DRAMTMG9 0x124 -#define DDR_PCTL2_DRAMTMG10 0x128 -#define DDR_PCTL2_DRAMTMG11 0x12c -#define DDR_PCTL2_DRAMTMG12 0x130 -#define DDR_PCTL2_DRAMTMG13 0x134 -#define DDR_PCTL2_DRAMTMG14 0x138 -#define DDR_PCTL2_DRAMTMG15 0x13c -#define DDR_PCTL2_DRAMTMG16 0x140 -#define DDR_PCTL2_ZQCTL0 0x180 -#define DDR_PCTL2_ZQCTL1 0x184 -#define DDR_PCTL2_ZQCTL2 0x188 -#define DDR_PCTL2_ZQSTAT 0x18c -#define DDR_PCTL2_DFITMG0 0x190 -#define DDR_PCTL2_DFITMG1 0x194 -#define DDR_PCTL2_DFILPCFG0 0x198 -#define DDR_PCTL2_DFILPCFG1 0x19c -#define DDR_PCTL2_DFIUPD0 0x1a0 -#define DDR_PCTL2_DFIUPD1 0x1a4 -#define DDR_PCTL2_DFIUPD2 0x1a8 -#define DDR_PCTL2_DFIMISC 0x1b0 -#define DDR_PCTL2_DFITMG2 0x1b4 -#define DDR_PCTL2_DFITMG3 0x1b8 -#define DDR_PCTL2_DFISTAT 0x1bc -#define DDR_PCTL2_DBICTL 0x1c0 -#define DDR_PCTL2_ADDRMAP0 0x200 -#define DDR_PCTL2_ADDRMAP1 0x204 -#define DDR_PCTL2_ADDRMAP2 0x208 -#define DDR_PCTL2_ADDRMAP3 0x20c -#define DDR_PCTL2_ADDRMAP4 0x210 -#define DDR_PCTL2_ADDRMAP5 0x214 -#define DDR_PCTL2_ADDRMAP6 0x218 -#define DDR_PCTL2_ADDRMAP7 0x21c -#define DDR_PCTL2_ADDRMAP8 0x220 -#define DDR_PCTL2_ADDRMAP9 0x224 -#define DDR_PCTL2_ADDRMAP10 0x228 -#define DDR_PCTL2_ADDRMAP11 0x22c -#define DDR_PCTL2_ODTCFG 0x240 -#define DDR_PCTL2_ODTMAP 0x244 -#define DDR_PCTL2_SCHED 0x250 -#define DDR_PCTL2_SCHED1 0x254 -#define DDR_PCTL2_PERFHPR1 0x25c -#define DDR_PCTL2_PERFLPR1 0x264 -#define DDR_PCTL2_PERFWR1 0x26c -#define DDR_PCTL2_DQMAP0 0x280 -#define DDR_PCTL2_DQMAP1 0x284 -#define DDR_PCTL2_DQMAP2 0x288 -#define DDR_PCTL2_DQMAP3 0x28c -#define DDR_PCTL2_DQMAP4 0x290 -#define DDR_PCTL2_DQMAP5 0x294 -#define DDR_PCTL2_DBG0 0x300 -#define DDR_PCTL2_DBG1 0x304 -#define DDR_PCTL2_DBGCAM 0x308 -#define DDR_PCTL2_DBGCMD 0x30c -#define DDR_PCTL2_DBGSTAT 0x310 -#define DDR_PCTL2_SWCTL 0x320 -#define DDR_PCTL2_SWSTAT 0x324 -#define DDR_PCTL2_POISONCFG 0x36c -#define DDR_PCTL2_POISONSTAT 0x370 -#define DDR_PCTL2_ADVECCINDEX 0x374 -#define DDR_PCTL2_ADVECCSTAT 0x378 -#define DDR_PCTL2_PSTAT 0x3fc -#define DDR_PCTL2_PCCFG 0x400 -#define DDR_PCTL2_PCFGR_n 0x404 -#define DDR_PCTL2_PCFGW_n 0x408 -#define DDR_PCTL2_PCTRL_n 0x490 - -/* PCTL2_MRSTAT */ -#define MR_WR_BUSY BIT(0) - -/* PHY_REG0 */ -#define DIGITAL_DERESET BIT(3) -#define ANALOG_DERESET BIT(2) -#define DIGITAL_RESET (0 << 3) -#define ANALOG_RESET (0 << 2) - -/* PHY_REG1 */ -#define PHY_DDR2 (0) -#define PHY_LPDDR2 (1) -#define PHY_DDR3 (2) -#define PHY_LPDDR3 (3) -#define PHY_DDR4 (4) -#define PHY_BL_4 (0 << 2) -#define PHY_BL_8 BIT(2) - -/* PHY_REG2 */ -#define PHY_DTT_EN BIT(0) -#define PHY_DTT_DISB (0 << 0) -#define PHY_WRITE_LEVELING_EN BIT(2) -#define PHY_WRITE_LEVELING_DISB (0 << 2) -#define PHY_SELECT_CS0 (2) -#define PHY_SELECT_CS1 (1) -#define PHY_SELECT_CS0_1 (0) -#define PHY_WRITE_LEVELING_SELECTCS(n) (n << 6) -#define PHY_DATA_TRAINING_SELECTCS(n) (n << 4) - -#define PHY_DDR3_RON_RTT_DISABLE (0) -#define PHY_DDR3_RON_RTT_451ohm (1) -#define PHY_DDR3_RON_RTT_225ohm (2) -#define PHY_DDR3_RON_RTT_150ohm (3) -#define PHY_DDR3_RON_RTT_112ohm (4) -#define PHY_DDR3_RON_RTT_90ohm (5) -#define PHY_DDR3_RON_RTT_75ohm (6) -#define PHY_DDR3_RON_RTT_64ohm (7) -#define PHY_DDR3_RON_RTT_56ohm (16) -#define PHY_DDR3_RON_RTT_50ohm (17) -#define PHY_DDR3_RON_RTT_45ohm (18) -#define PHY_DDR3_RON_RTT_41ohm (19) -#define PHY_DDR3_RON_RTT_37ohm (20) -#define PHY_DDR3_RON_RTT_34ohm (21) -#define PHY_DDR3_RON_RTT_33ohm (22) -#define PHY_DDR3_RON_RTT_30ohm (23) -#define PHY_DDR3_RON_RTT_28ohm (24) -#define PHY_DDR3_RON_RTT_26ohm (25) -#define PHY_DDR3_RON_RTT_25ohm (26) -#define PHY_DDR3_RON_RTT_23ohm (27) -#define PHY_DDR3_RON_RTT_22ohm (28) -#define PHY_DDR3_RON_RTT_21ohm (29) -#define PHY_DDR3_RON_RTT_20ohm (30) -#define PHY_DDR3_RON_RTT_19ohm (31) - -#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0) -#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1) -#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2) -#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3) -#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4) -#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5) -#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6) -#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7) -#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16) -#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17) -#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18) -#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19) -#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20) -#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21) -#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22) -#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23) -#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24) -#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25) -#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26) -#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27) -#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28) -#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29) -#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30) -#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31) /* noc registers define */ #define DDRCONF 0x8 @@ -219,16 +36,16 @@ #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) /* CRU_SOFTRESET_CON5 */ -#define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | (n << 15)) -#define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | (n << 14)) -#define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | (n << 13)) -#define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | (n << 12)) -#define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | (n << 11)) -#define msch_srstn_req(n) (((0x1 << 9) << 16) | (n << 9)) -#define dfimon_srstn_req(n) (((0x1 << 8) << 16) | (n << 8)) -#define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | (n << 7)) +#define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | ((n) << 15)) +#define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | ((n) << 14)) +#define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | ((n) << 13)) +#define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | ((n) << 12)) +#define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | ((n) << 11)) +#define msch_srstn_req(n) (((0x1 << 9) << 16) | ((n) << 9)) +#define dfimon_srstn_req(n) (((0x1 << 8) << 16) | ((n) << 8)) +#define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | ((n) << 7)) /* CRU_SOFTRESET_CON9 */ -#define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | (n << 9)) +#define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | ((n) << 9)) /* CRU register */ #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) @@ -255,56 +72,46 @@ #define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6)) #define REFDIV(n) ((0x3F << 16) | (n)) -union noc_ddrtiming { - u32 d32; - struct { - unsigned acttoact:6; - unsigned rdtomiss:6; - unsigned wrtomiss:6; - unsigned burstlen:3; - unsigned rdtowr:5; - unsigned wrtord:5; - unsigned bwratio:1; - } b; -} NOC_TIMING_T; - -union noc_activate { - u32 d32; - struct { - unsigned rrd:4; - unsigned faw:6; - unsigned fawbank:1; - unsigned reserved1:21; - } b; -}; - -union noc_devtodev { - u32 d32; - struct { - unsigned busrdtord:2; - unsigned busrdtowr:2; - unsigned buswrtord:2; - unsigned reserved2:26; - } b; -}; - -union noc_ddr4timing { - u32 d32; - struct { - unsigned ccdl:3; - unsigned wrtordl:5; - unsigned rrdl:4; - unsigned reserved2:20; - } b; +u16 ddr_cfg_2_rbc[] = { + /* + * [5:4] row(13+n) + * [3] cs(0:0 cs, 1:2 cs) + * [2] bank(0:0bank,1:8bank) + * [1:0] col(11+n) + */ + /* row, cs, bank, col */ + ((3 << 4) | (0 << 3) | (1 << 2) | 0), + ((3 << 4) | (0 << 3) | (1 << 2) | 1), + ((2 << 4) | (0 << 3) | (1 << 2) | 2), + ((3 << 4) | (0 << 3) | (1 << 2) | 2), + ((2 << 4) | (0 << 3) | (1 << 2) | 3), + ((3 << 4) | (1 << 3) | (1 << 2) | 0), + ((3 << 4) | (1 << 3) | (1 << 2) | 1), + ((2 << 4) | (1 << 3) | (1 << 2) | 2), + ((3 << 4) | (0 << 3) | (0 << 2) | 1), + ((2 << 4) | (0 << 3) | (1 << 2) | 1), }; -union noc_ddrmode { - u32 d32; - struct { - unsigned autoprecharge:1; - unsigned bwratioextended:1; - unsigned reserved3:30; - } b; +u16 ddr4_cfg_2_rbc[] = { + /*************************** + * [6] cs 0:0cs 1:2 cs + * [5:3] row(13+n) + * [2] cs(0:0 cs, 1:2 cs) + * [1] bw 0: 16bit 1:32bit + * [0] diebw 0:8bit 1:16bit + ***************************/ + /* cs, row, cs, bw, diebw */ + ((0 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 0), + ((1 << 6) | (2 << 3) | (0 << 2) | (1 << 1) | 0), + ((0 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 0), + ((1 << 6) | (3 << 3) | (0 << 2) | (0 << 1) | 0), + ((0 << 6) | (4 << 3) | (0 << 2) | (1 << 1) | 1), + ((1 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 1), + ((1 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 1), + ((0 << 6) | (2 << 3) | (1 << 2) | (1 << 1) | 0), + ((0 << 6) | (3 << 3) | (1 << 2) | (0 << 1) | 0), + ((0 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | 1), + ((0 << 6) | (4 << 3) | (1 << 2) | (0 << 1) | 1), }; u32 addrmap[21][9] = { @@ -355,17 +162,65 @@ u32 addrmap[21][9] = { 0x07070707, 0x00000f07, 0x3f00} }; -struct rk3328_msch_timings { - union noc_ddrtiming ddrtiming; - union noc_ddrmode ddrmode; - u32 readlatency; - union noc_activate activate; - union noc_devtodev devtodev; - union noc_ddr4timing ddr4timing; - u32 agingx0; +struct rk3328_ddr_grf_regs { + u32 ddr_grf_con[4]; + u32 reserved[(0x100 - 0x10) / 4]; + u32 ddr_grf_status[11]; }; -struct rk3328_msch_regs { +union noc_ddrtiming { + u32 d32; + struct { + unsigned acttoact:6; + unsigned rdtomiss:6; + unsigned wrtomiss:6; + unsigned burstlen:3; + unsigned rdtowr:5; + unsigned wrtord:5; + unsigned bwratio:1; + } b; +}; + +union noc_activate { + u32 d32; + struct { + unsigned rrd:4; + unsigned faw:6; + unsigned fawbank:1; + unsigned reserved1:21; + } b; +}; + +union noc_devtodev { + u32 d32; + struct { + unsigned busrdtord:2; + unsigned busrdtowr:2; + unsigned buswrtord:2; + unsigned reserved2:26; + } b; +}; + +union noc_ddr4timing { + u32 d32; + struct { + unsigned ccdl:3; + unsigned wrtordl:5; + unsigned rrdl:4; + unsigned reserved2:20; + } b; +}; + +union noc_ddrmode { + u32 d32; + struct { + unsigned autoprecharge:1; + unsigned bwratioextended:1; + unsigned reserved3:30; + } b; +}; + +struct msch_regs { u32 coreid; u32 revisionid; u32 ddrconf; @@ -384,58 +239,27 @@ struct rk3328_msch_regs { u32 ddr4_timing; }; -struct rk3328_ddr_grf_regs { - u32 ddr_grf_con[4]; - u32 reserved[(0x100 - 0x10) / 4]; - u32 ddr_grf_status[11]; -}; - -struct rk3328_ddr_pctl_regs { - u32 pctl[30][2]; -}; - -struct rk3328_ddr_phy_regs { - u32 phy[5][2]; -}; - -struct rk3328_ddr_skew { - u32 a0_a1_skew[15]; - u32 cs0_dm0_skew[11]; - u32 cs0_dm1_skew[11]; - u32 cs0_dm2_skew[11]; - u32 cs0_dm3_skew[11]; - u32 cs1_dm0_skew[11]; - u32 cs1_dm1_skew[11]; - u32 cs1_dm2_skew[11]; - u32 cs1_dm3_skew[11]; +struct sdram_msch_timings { + union noc_ddrtiming ddrtiming; + union noc_ddrmode ddrmode; + u32 readlatency; + union noc_activate activate; + union noc_devtodev devtodev; + union noc_ddr4timing ddr4timing; + u32 agingx0; }; struct rk3328_sdram_channel { - unsigned int rank; - unsigned int col; - /* 3:8bank, 2:4bank */ - unsigned int bk; - /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ - unsigned int bw; - /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ - unsigned int dbw; - unsigned int row_3_4; - unsigned int cs0_row; - unsigned int cs1_row; - unsigned int ddrconfig; - struct rk3328_msch_timings noc_timings; + struct sdram_cap_info cap_info; + struct sdram_msch_timings noc_timings; }; struct rk3328_sdram_params { struct rk3328_sdram_channel ch; - unsigned int ddr_freq; - unsigned int dramtype; - unsigned int odt; - struct rk3328_ddr_pctl_regs pctl_regs; - struct rk3328_ddr_phy_regs phy_regs; - struct rk3328_ddr_skew skew; + struct sdram_base_params base; + struct ddr_pctl_regs pctl_regs; + struct ddr_phy_regs phy_regs; + struct ddr_phy_skew skew; }; -#define PHY_REG(base, n) (base + 4 * (n)) - #endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index dc65ae79243..267649fda4c 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -5,6 +5,8 @@ #ifndef _ASM_ARCH_SDRAM_RK3399_H #define _ASM_ARCH_SDRAM_RK3399_H +#include <asm/arch-rockchip/sdram_common.h> +#include <asm/arch-rockchip/sdram_msch.h> struct rk3399_ddr_pctl_regs { u32 denali_ctl[332]; @@ -18,55 +20,6 @@ struct rk3399_ddr_pi_regs { u32 denali_pi[200]; }; -union noc_ddrtimingc0 { - u32 d32; - struct { - unsigned burstpenalty : 4; - unsigned reserved0 : 4; - unsigned wrtomwr : 6; - unsigned reserved1 : 18; - } b; -}; - -union noc_ddrmode { - u32 d32; - struct { - unsigned autoprecharge : 1; - unsigned bypassfiltering : 1; - unsigned fawbank : 1; - unsigned burstsize : 2; - unsigned mwrsize : 2; - unsigned reserved2 : 1; - unsigned forceorder : 8; - unsigned forceorderstate : 8; - unsigned reserved3 : 8; - } b; -}; - -struct rk3399_msch_regs { - u32 coreid; - u32 revisionid; - u32 ddrconf; - u32 ddrsize; - u32 ddrtiminga0; - u32 ddrtimingb0; - u32 ddrtimingc0; - u32 devtodev0; - u32 reserved0[(0x110 - 0x20) / 4]; - u32 ddrmode; - u32 reserved1[(0x1000 - 0x114) / 4]; - u32 agingx0; -}; - -struct rk3399_msch_timings { - u32 ddrtiminga0; - u32 ddrtimingb0; - union noc_ddrtimingc0 ddrtimingc0; - u32 devtodev0; - union noc_ddrmode ddrmode; - u32 agingx0; -}; - struct rk3399_ddr_cic_regs { u32 cic_ctrl0; u32 cic_ctrl1; @@ -83,14 +36,38 @@ struct rk3399_ddr_cic_regs { #define START 1 /* DENALI_CTL_68 */ -#define PWRUP_SREFRESH_EXIT (1 << 16) +#define PWRUP_SREFRESH_EXIT BIT(16) /* DENALI_CTL_274 */ #define MEM_RST_VALID 1 +struct msch_regs { + u32 coreid; + u32 revisionid; + u32 ddrconf; + u32 ddrsize; + union noc_ddrtiminga0 ddrtiminga0; + union noc_ddrtimingb0 ddrtimingb0; + union noc_ddrtimingc0 ddrtimingc0; + union noc_devtodev0 devtodev0; + u32 reserved0[(0x110 - 0x20) / 4]; + union noc_ddrmode ddrmode; + u32 reserved1[(0x1000 - 0x114) / 4]; + u32 agingx0; +}; + +struct sdram_msch_timings { + union noc_ddrtiminga0 ddrtiminga0; + union noc_ddrtimingb0 ddrtimingb0; + union noc_ddrtimingc0 ddrtimingc0; + union noc_devtodev0 devtodev0; + union noc_ddrmode ddrmode; + u32 agingx0; +}; + struct rk3399_sdram_channel { struct sdram_cap_info cap_info; - struct rk3399_msch_timings noc_timings; + struct sdram_msch_timings noc_timings; }; struct rk3399_sdram_params { @@ -101,11 +78,20 @@ struct rk3399_sdram_params { struct rk3399_ddr_publ_regs phy_regs; }; -#define PI_CA_TRAINING (1 << 0) -#define PI_WRITE_LEVELING (1 << 1) -#define PI_READ_GATE_TRAINING (1 << 2) -#define PI_READ_LEVELING (1 << 3) -#define PI_WDQ_LEVELING (1 << 4) +#define PI_CA_TRAINING BIT(0) +#define PI_WRITE_LEVELING BIT(1) +#define PI_READ_GATE_TRAINING BIT(2) +#define PI_READ_LEVELING BIT(3) +#define PI_WDQ_LEVELING BIT(4) #define PI_FULL_TRAINING 0xff +enum { + STRIDE_128B = 0, + STRIDE_256B = 1, + STRIDE_512B = 2, + STRIDE_4KB = 3, + UN_STRIDE = 4, + PART_STRIDE = 5, +}; + #endif |