diff options
Diffstat (limited to 'arch/arm/include')
44 files changed, 712 insertions, 323 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index abc5b6b411..d748dd2787 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -19,16 +19,16 @@ #ifndef _CLOCKS_AM33XX_H_ #define _CLOCKS_AM33XX_H_ -#define OSC 24 +#define OSC (V_OSCK/1000000) /* MAIN PLL Fdll = 550 MHZ, */ #define MPUPLL_M 550 -#define MPUPLL_N 23 +#define MPUPLL_N (OSC-1) #define MPUPLL_M2 1 /* Core PLL Fdll = 1 GHZ, */ #define COREPLL_M 1000 -#define COREPLL_N 23 +#define COREPLL_N (OSC-1) #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ @@ -40,13 +40,13 @@ * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below */ #define PERPLL_M 960 -#define PERPLL_N 23 +#define PERPLL_N (OSC-1) #define PERPLL_M2 5 /* DDR Freq is 266 MHZ for now */ /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ #define DDRPLL_M 266 -#define DDRPLL_N 23 +#define DDRPLL_N (OSC-1) #define DDRPLL_M2 1 extern void pll_init(void); diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index cd002e632d..a027e3128f 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -53,8 +53,10 @@ /* Reset control */ #ifdef CONFIG_AM33XX #define PRM_RSTCTRL 0x44E00F00 +#define PRM_RSTST 0x44E00F08 #endif #define PRM_RSTCTRL_RESET 0x01 +#define PRM_RSTST_WARM_RESET_MASK 0x232 #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ @@ -62,7 +64,7 @@ struct cm_wkuppll { unsigned int wkclkstctrl; /* offset 0x00 */ unsigned int wkctrlclkctrl; /* offset 0x04 */ - unsigned int resv1[1]; + unsigned int wkgpio0clkctrl; /* offset 0x08 */ unsigned int wkl4wkclkctrl; /* offset 0x0c */ unsigned int resv2[4]; unsigned int idlestdpllmpu; /* offset 0x20 */ @@ -111,34 +113,54 @@ struct cm_perpll { unsigned int l3clkstctrl; /* offset 0x0c */ unsigned int resv1; unsigned int cpgmac0clkctrl; /* offset 0x14 */ - unsigned int resv2[4]; + unsigned int lcdclkctrl; /* offset 0x18 */ + unsigned int usb0clkctrl; /* offset 0x1C */ + unsigned int resv2; + unsigned int tptc0clkctrl; /* offset 0x24 */ unsigned int emifclkctrl; /* offset 0x28 */ unsigned int ocmcramclkctrl; /* offset 0x2c */ unsigned int gpmcclkctrl; /* offset 0x30 */ - unsigned int resv3[2]; + unsigned int mcasp0clkctrl; /* offset 0x34 */ + unsigned int uart5clkctrl; /* offset 0x38 */ unsigned int mmc0clkctrl; /* offset 0x3C */ unsigned int elmclkctrl; /* offset 0x40 */ unsigned int i2c2clkctrl; /* offset 0x44 */ unsigned int i2c1clkctrl; /* offset 0x48 */ unsigned int spi0clkctrl; /* offset 0x4C */ unsigned int spi1clkctrl; /* offset 0x50 */ - unsigned int resv4[3]; + unsigned int resv3[3]; unsigned int l4lsclkctrl; /* offset 0x60 */ unsigned int l4fwclkctrl; /* offset 0x64 */ - unsigned int resv5[6]; + unsigned int mcasp1clkctrl; /* offset 0x68 */ + unsigned int uart1clkctrl; /* offset 0x6C */ + unsigned int uart2clkctrl; /* offset 0x70 */ + unsigned int uart3clkctrl; /* offset 0x74 */ + unsigned int uart4clkctrl; /* offset 0x78 */ + unsigned int timer7clkctrl; /* offset 0x7C */ unsigned int timer2clkctrl; /* offset 0x80 */ - unsigned int resv6[11]; + unsigned int timer3clkctrl; /* offset 0x84 */ + unsigned int timer4clkctrl; /* offset 0x88 */ + unsigned int resv4[8]; + unsigned int gpio1clkctrl; /* offset 0xAC */ unsigned int gpio2clkctrl; /* offset 0xB0 */ - unsigned int resv7[7]; + unsigned int gpio3clkctrl; /* offset 0xB4 */ + unsigned int resv5; + unsigned int tpccclkctrl; /* offset 0xBC */ + unsigned int dcan0clkctrl; /* offset 0xC0 */ + unsigned int dcan1clkctrl; /* offset 0xC4 */ + unsigned int resv6[2]; unsigned int emiffwclkctrl; /* offset 0xD0 */ - unsigned int resv8[2]; + unsigned int resv7[2]; unsigned int l3instrclkctrl; /* offset 0xDC */ unsigned int l3clkctrl; /* Offset 0xE0 */ - unsigned int resv9[14]; + unsigned int resv8[4]; + unsigned int mmc1clkctrl; /* offset 0xF4 */ + unsigned int mmc2clkctrl; /* offset 0xF8 */ + unsigned int resv9[8]; unsigned int l4hsclkstctrl; /* offset 0x11C */ unsigned int l4hsclkctrl; /* offset 0x120 */ unsigned int resv10[8]; - unsigned int cpswclkctrl; /* offset 0x144 */ + unsigned int cpswclkstctrl; /* offset 0x144 */ }; /* Encapsulating Display pll registers */ @@ -213,8 +235,6 @@ struct ctrl_stat { unsigned int resv1[16]; unsigned int statusreg; /* ofset 0x40 */ }; - -void init_timer(void); #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h b/arch/arm/include/asm/arch-am33xx/i2c.h index 366e2bbec5..32b225800d 100644 --- a/arch/arm/include/asm/arch-am33xx/i2c.h +++ b/arch/arm/include/asm/arch-am33xx/i2c.h @@ -34,9 +34,9 @@ struct i2c { unsigned short revnb_lo; /* 0x00 */ unsigned short res1; unsigned short revnb_hi; /* 0x04 */ - unsigned short res2[13]; - unsigned short sysc; /* 0x20 */ - unsigned short res3; + unsigned short res2[5]; + unsigned short sysc; /* 0x10 */ + unsigned short res3[9]; unsigned short irqstatus_raw; /* 0x24 */ unsigned short res4; unsigned short stat; /* 0x28 */ @@ -76,6 +76,6 @@ struct i2c { }; #define I2C_IP_CLK 48000000 -#define I2C_INTERNAL_SAMLPING_CLK 12000000 +#define I2C_INTERNAL_SAMPLING_CLK 12000000 #endif /* _I2C_H_ */ diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h index 416cabf87c..0483c9820e 100644 --- a/arch/arm/include/asm/arch-at91/at91_pio.h +++ b/arch/arm/include/asm/arch-at91/at91_pio.h @@ -66,14 +66,50 @@ typedef struct at91_port { u32 puer; /* 0x64 Pull-up Enable Register */ u32 pusr; /* 0x68 Pad Pull-up Status Register */ u32 reserved4; +#if defined(CPU_HAS_PIO3) + u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */ + u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */ + u32 reserved5[2]; + u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */ + u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */ + u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */ + u32 scdr; /* 0x8C SCLK Divider Debouncing Register */ + u32 ppddr; /* 0x90 Pad Pull-down Disable Register */ + u32 ppder; /* 0x94 Pad Pull-down Enable Register */ + u32 ppdsr; /* 0x98 Pad Pull-down Status Register */ + u32 reserved6; /* */ +#else u32 asr; /* 0x70 Select A Register */ u32 bsr; /* 0x74 Select B Register */ u32 absr; /* 0x78 AB Select Status Register */ u32 reserved5[9]; /* */ +#endif u32 ower; /* 0xA0 Output Write Enable Register */ u32 owdr; /* 0xA4 Output Write Disable Register */ - u32 owsr; /* OxA8 utput Write Status Register */ + u32 owsr; /* OxA8 Output Write Status Register */ +#if defined(CPU_HAS_PIO3) + u32 reserved7; /* */ + u32 aimer; /* 0xB0 Additional INT Modes Enable Register */ + u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */ + u32 aimmr; /* 0xB8 Additional INT Modes Mask Register */ + u32 reserved8; /* */ + u32 esr; /* 0xC0 Edge Select Register */ + u32 lsr; /* 0xC4 Level Select Register */ + u32 elsr; /* 0xC8 Edge/Level Status Register */ + u32 reserved9; /* 0xCC */ + u32 fellsr; /* 0xD0 Falling /Low Level Select Register */ + u32 rehlsr; /* 0xD4 Rising /High Level Select Register */ + u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */ + u32 reserved10; /* */ + u32 locksr; /* 0xE0 Lock Status */ + u32 wpmr; /* 0xE4 Write Protect Mode Register */ + u32 wpsr; /* 0xE8 Write Protect Status Register */ + u32 reserved11[5]; /* */ + u32 schmitt; /* 0x100 Schmitt Trigger Register */ + u32 reserved12[63]; +#else u32 reserved6[85]; +#endif } at91_port_t; typedef union at91_pio { @@ -94,6 +130,13 @@ typedef union at91_pio { #ifdef CONFIG_AT91_GPIO int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); +#if defined(CPU_HAS_PIO3) +int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div); +int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on); +int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin); +#endif int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); int at91_set_pio_output(unsigned port, unsigned pin, int value); diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index ac4ddc7354..b1e22f2c15 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -24,6 +24,7 @@ #define DEVICE_NOT_AVAILABLE 0 +#define EXYNOS_CPU_NAME "Exynos" #define EXYNOS4_ADDR_BASE 0x10000000 /* EXYNOS4 */ @@ -93,29 +94,42 @@ static inline int s5p_get_cpu_rev(void) static inline void s5p_set_cpu_id(void) { - s5p_cpu_id = readl(EXYNOS4_PRO_ID); - s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12)); - - /* - * 0xC200: EXYNOS4210 EVT0 - * 0xC210: EXYNOS4210 EVT1 - */ - if (s5p_cpu_id == 0xC200) { - s5p_cpu_id |= 0x10; + unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12; + + switch (pro_id) { + case 0x200: + /* Exynos4210 EVT0 */ + s5p_cpu_id = 0x4210; s5p_cpu_rev = 0; - } else if (s5p_cpu_id == 0xC210) { - s5p_cpu_rev = 1; + break; + case 0x210: + /* Exynos4210 EVT1 */ + s5p_cpu_id = 0x4210; + break; + case 0x412: + /* Exynos4412 */ + s5p_cpu_id = 0x4412; + break; + case 0x520: + /* Exynos5250 */ + s5p_cpu_id = 0x5250; + break; } } +static inline char *s5p_get_cpu_name(void) +{ + return EXYNOS_CPU_NAME; +} + #define IS_SAMSUNG_TYPE(type, id) \ static inline int cpu_is_##type(void) \ { \ - return s5p_cpu_id == id ? 1 : 0; \ + return (s5p_cpu_id >> 12) == id; \ } -IS_SAMSUNG_TYPE(exynos4, 0xc210) -IS_SAMSUNG_TYPE(exynos5, 0xc520) +IS_SAMSUNG_TYPE(exynos4, 0x4) +IS_SAMSUNG_TYPE(exynos5, 0x5) #define SAMSUNG_BASE(device, base) \ static inline unsigned int samsung_get_base_##device(void) \ diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h new file mode 100644 index 0000000000..5db25aa88a --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Rajeshwari Shinde <rajeshwari.s@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals requiring clock/pinmux configuration. List will + * grow with support for more devices getting added. + * + */ +enum periph_id { + PERIPH_ID_SDMMC0, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_SDMMC3, + PERIPH_ID_SROMC, + PERIPH_ID_UART0, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h new file mode 100644 index 0000000000..10ea736c7d --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/pinmux.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Abhilash Kesavan <a.kesavan@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PINMUX_H +#define __ASM_ARM_ARCH_PINMUX_H + +#include "periph.h" + +/* + * Flags for setting specific configarations of peripherals. + * List will grow with support for more devices getting added. + */ +enum { + PINMUX_FLAG_NONE = 0x00000000, + + /* Flags for eMMC */ + PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */ + + /* Flags for SROM controller */ + PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ + PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */ +}; + +/** + * Configures the pinmux for a particular peripheral. + * + * Each gpio can be configured in many different ways (4 bits on exynos) + * such as "input", "output", "special function", "external interrupt" + * etc. This function will configure the peripheral pinmux along with + * pull-up/down and drive strength. + * + * @param peripheral peripheral to be configured + * @param flags configure flags + * @return 0 if ok, -1 on error (e.g. unsupported peripheral) + */ +int exynos_pinmux_config(int peripheral, int flags); + +#endif diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h index 91164eb402..a9499b70cd 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -82,9 +82,15 @@ #ifdef CONFIG_CMD_SF #define CONFIG_HARD_SPI 1 #define CONFIG_KIRKWOOD_SPI 1 -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */ +#ifndef CONFIG_ENV_SPI_BUS +# define CONFIG_ENV_SPI_BUS 0 +#endif +#ifndef CONFIG_ENV_SPI_CS +# define CONFIG_ENV_SPI_CS 0 +#endif +#ifndef CONFIG_ENV_SPI_MAX_HZ +# define CONFIG_ENV_SPI_MAX_HZ 50000000 +#endif #endif /* diff --git a/arch/arm/include/asm/arch-kirkwood/mpp.h b/arch/arm/include/asm/arch-kirkwood/mpp.h index b3c090edcd..8e50ee7f14 100644 --- a/arch/arm/include/asm/arch-kirkwood/mpp.h +++ b/arch/arm/include/asm/arch-kirkwood/mpp.h @@ -312,6 +312,6 @@ #define MPP_MAX 49 -void kirkwood_mpp_conf(unsigned int *mpp_list); +void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save); #endif diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h b/arch/arm/include/asm/arch-kirkwood/spi.h index 1d5043f94f..c79bed7ed9 100644 --- a/arch/arm/include/asm/arch-kirkwood/spi.h +++ b/arch/arm/include/asm/arch-kirkwood/spi.h @@ -37,6 +37,17 @@ struct kwspi_registers { u32 irq_mask; /* 0x10614 */ }; +/* They are used to define CONFIG_SYS_KW_SPI_MPP + * each of the below #defines selects which mpp is + * configured for each SPI signal in spi_claim_bus + * bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1) + * bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1) + * bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1) + */ +#define MOSI_MPP6 (1 << 0) +#define SCK_MPP10 (1 << 1) +#define MISO_MPP11 (1 << 2) + #define KWSPI_CLKPRESCL_MASK 0x1f #define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ #define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ diff --git a/arch/arm/include/asm/arch-mx28/regs-common.h b/arch/arm/include/asm/arch-mx28/regs-common.h index 94b512d18a..d2e19538af 100644 --- a/arch/arm/include/asm/arch-mx28/regs-common.h +++ b/arch/arm/include/asm/arch-mx28/regs-common.h @@ -70,7 +70,7 @@ struct mx28_register_32 { #define mx28_reg_8(name) \ union { \ struct { __mx28_reg_8(name) }; \ - struct mx28_register_32 name##_reg; \ + struct mx28_register_8 name##_reg; \ }; #define mx28_reg_32(name) \ diff --git a/arch/arm/include/asm/arch-mx6/mx6x_pins.h b/arch/arm/include/asm/arch-mx6/mx6x_pins.h index afaa068bb9..9979651b0f 100644 --- a/arch/arm/include/asm/arch-mx6/mx6x_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6x_pins.h @@ -48,8 +48,8 @@ #define PAD_CTL_SRE_FAST (1 << 0) #define PAD_CTL_SRE_SLOW (0 << 0) -#define NO_MUX_I 0x3FF -#define NO_PAD_I 0x7FF +#define NO_MUX_I 0 +#define NO_PAD_I 0 enum { MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 457f99d2c5..5683e16177 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -479,6 +479,8 @@ struct prm { #define PRM_RSTCTRL 0x48307250 #define PRM_RSTCTRL_RESET 0x04 +#define PRM_RSTST 0x48307258 +#define PRM_RSTST_WARM_RESET_MASK 0x7D2 #define SYSCLKDIV_1 (0x1 << 6) #define SYSCLKDIV_2 (0x1 << 7) diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 2a89e56534..9e52b12aa2 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -74,4 +74,5 @@ void power_init_r(void); void dieid_num_r(void); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); void omap3_gp_romcode_call(u32 service_id, u32 parameter); +u32 warm_reset(void); #endif diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index 617729c32b..be20fc0ce6 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -525,6 +525,11 @@ struct omap4_scrm_regs { #define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ +/* CM_DLL_CTRL */ +#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 +#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) +#define CM_DLL_CTRL_NO_OVERRIDE 0 + /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index feddb7de51..a8c4c60c8c 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -178,5 +178,7 @@ struct watchdog { #define PRM_RSTCTRL PRM_DEVICE_BASE #define PRM_RSTCTRL_RESET 0x01 +#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) +#define PRM_RSTST_WARM_RESET_MASK 0x07EA #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 47c5883025..03bd923145 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -112,7 +112,7 @@ #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C #define LPDDR2IO_GR10_WD_MASK (3 << 17) -#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 +#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F /* CONTROL_EFUSE_2 */ #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index c6e3ad26ff..d633573c25 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -57,6 +57,8 @@ void init_omap_revision(void); void do_io_settings(void); void omap_vc_init(u16 speed_khz); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); +u32 warm_reset(void); +void force_emif_self_refresh(void); /* * This is used to verify if the configuration header * was executed by Romcode prior to control of transfer diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index f32cf3eeef..5f1a7aa770 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -480,6 +480,13 @@ struct omap5_prcm_regs { u32 pad217[4]; u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */ u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */ + u32 pad218[2]; + u32 prm_sldo_core_setup; /* 4ae07bc4 */ + u32 prm_sldo_core_ctrl; /* 4ae07bc8 */ + u32 prm_sldo_mpu_setup; /* 4ae07bcc */ + u32 prm_sldo_mpu_ctrl; /* 4ae07bd0 */ + u32 prm_sldo_mm_setup; /* 4ae07bd4 */ + u32 prm_sldo_mm_ctrl; /* 4ae07bd8 */ }; /* DPLL register offsets */ @@ -490,6 +497,11 @@ struct omap5_prcm_regs { #define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ +/* CM_DLL_CTRL */ +#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 +#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) +#define CM_DLL_CTRL_NO_OVERRIDE 0 + /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) @@ -641,6 +653,9 @@ struct omap5_prcm_regs { #define VDD_MPU 1000 #define VDD_MM 1000 #define VDD_CORE 1040 +#define VDD_MPU_5432 1150 +#define VDD_MM_5432 1150 +#define VDD_CORE_5432 1150 /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000 diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 8ef17c9a14..5e62013236 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -182,5 +182,7 @@ struct watchdog { #define PRM_RSTCTRL PRM_DEVICE_BASE #define PRM_RSTCTRL_RESET 0x01 +#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) +#define PRM_RSTST_WARM_RESET_MASK 0x7FEA #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index e3f55d2020..7f05cb5b4a 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -40,7 +40,7 @@ #define OMAP54XX_L4_PER_BASE 0x48000000 #define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000 -#define OMAP54XX_DRAM_ADDR_SPACE_END 0xD0000000 +#define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF #define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START #define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END @@ -56,7 +56,8 @@ #define CONTROL_ID_CODE (CTRL_BASE + 0x204) /* To be verified */ -#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B85202F +#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F +#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F /* STD_FUSE_PROD_ID_1 */ #define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) @@ -178,7 +179,14 @@ struct omap_sys_ctrl_regs { u32 control_srcomp_east_side; /*0x4A002E7C*/ u32 control_srcomp_west_side; /*0x4A002E80*/ u32 control_srcomp_code_latch; /*0x4A002E84*/ - u32 pad4[3680198]; + u32 pad4[3679394]; + u32 control_port_emif1_sdram_config; /*0x4AE0C110*/ + u32 control_port_emif1_lpddr2_nvm_config; /*0x4AE0C114*/ + u32 control_port_emif2_sdram_config; /*0x4AE0C118*/ + u32 pad5[10]; + u32 control_emif1_sdram_config_ext; /* 0x4AE0C144 */ + u32 control_emif2_sdram_config_ext; /* 0x4AE0C148 */ + u32 pad6[789]; u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */ u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */ u32 control_padconf_mode; /* 0x4AE0CDA8 */ @@ -233,6 +241,12 @@ struct omap_sys_ctrl_regs { #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 +#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 +#define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC +#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 + #define EFUSE_1 0x45145100 #define EFUSE_2 0x45145100 #define EFUSE_3 0x45145100 diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 8396a22141..74feb90277 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -57,6 +57,8 @@ void init_omap_revision(void); void do_io_settings(void); void omap_vc_init(u16 speed_khz); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); +u32 warm_reset(void); +void force_emif_self_refresh(void); /* * This is used to verify if the configuration header diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h index 510ead4d99..2362b9985b 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h +++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h @@ -23,6 +23,7 @@ #ifndef _S5PC1XX_CPU_H #define _S5PC1XX_CPU_H +#define S5P_CPU_NAME "S5P" #define S5PC1XX_ADDR_BASE 0xE0000000 /* S5PC100 */ @@ -71,6 +72,11 @@ static inline void s5p_set_cpu_id(void) s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12); } +static inline char *s5p_get_cpu_name(void) +{ + return S5P_CPU_NAME; +} + #define IS_SAMSUNG_TYPE(type, id) \ static inline int cpu_is_##type(void) \ { \ diff --git a/arch/arm/include/asm/arch-spear/clk.h b/arch/arm/include/asm/arch-spear/clk.h new file mode 100644 index 0000000000..a45ec1861c --- /dev/null +++ b/arch/arm/include/asm/arch-spear/clk.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{ + return 83000000; +} diff --git a/arch/arm/include/asm/arch-spear/gpio.h b/arch/arm/include/asm/arch-spear/gpio.h new file mode 100644 index 0000000000..c3697de8c5 --- /dev/null +++ b/arch/arm/include/asm/arch-spear/gpio.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2012 Stefan Roese <sr@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __ASM_ARCH_SPEAR_GPIO_H +#define __ASM_ARCH_SPEAR_GPIO_H + +enum gpio_direction { + GPIO_DIRECTION_IN, + GPIO_DIRECTION_OUT, +}; + +struct gpio_regs { + u32 gpiodata[0x100]; /* 0x000 ... 0x3fc */ + u32 gpiodir; /* 0x400 */ +}; + +#define SPEAR_GPIO_COUNT 8 +#define DATA_REG_ADDR(gpio) (1 << (gpio + 2)) + +#endif /* __ASM_ARCH_SPEAR_GPIO_H */ diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index 818f36cc66..81509119dd 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -24,43 +24,68 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H -#define CONFIG_SYS_USBD_BASE (0xE1100000) -#define CONFIG_SYS_PLUG_BASE (0xE1200000) -#define CONFIG_SYS_FIFO_BASE (0xE1000800) -#define CONFIG_SYS_SMI_BASE (0xFC000000) -#define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000) -#define CONFIG_SPEAR_TIMERBASE (0xFC800000) -#define CONFIG_SPEAR_MISCBASE (0xFCA80000) +#define CONFIG_SYS_USBD_BASE 0xE1100000 +#define CONFIG_SYS_PLUG_BASE 0xE1200000 +#define CONFIG_SYS_FIFO_BASE 0xE1000800 +#define CONFIG_SYS_SMI_BASE 0xFC000000 +#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000 +#define CONFIG_SPEAR_TIMERBASE 0xFC800000 +#define CONFIG_SPEAR_MISCBASE 0xFCA80000 +#define CONFIG_SPEAR_ETHBASE 0xE0800000 +#define CONFIG_SPEAR_MPMCBASE 0xFC600000 +#define CONFIG_SSP1_BASE 0xD0100000 +#define CONFIG_SSP2_BASE 0xD0180000 +#define CONFIG_SSP3_BASE 0xD8180000 +#define CONFIG_GPIO_BASE 0xD8100000 #define CONFIG_SYS_NAND_CLE (1 << 16) #define CONFIG_SYS_NAND_ALE (1 << 17) #if defined(CONFIG_SPEAR600) -#define CONFIG_SYS_I2C_BASE (0xD0200000) -#define CONFIG_SPEAR_FSMCBASE (0xD1800000) +#define CONFIG_SYS_I2C_BASE 0xD0200000 +#define CONFIG_SYS_FSMC_BASE 0xD1800000 +#define CONFIG_FSMC_NAND_BASE 0xD2000000 + +#define CONFIG_SPEAR_BOOTSTRAPCFG 0xFCA80000 +#define CONFIG_SPEAR_BOOTSTRAPSHFT 16 +#define CONFIG_SPEAR_BOOTSTRAPMASK 0xB +#define CONFIG_SPEAR_ONLYSNORBOOT 0xA +#define CONFIG_SPEAR_NORNANDBOOT 0xB +#define CONFIG_SPEAR_NORNAND8BOOT 0x8 +#define CONFIG_SPEAR_NORNAND16BOOT 0x9 +#define CONFIG_SPEAR_USBBOOT 0x8 + +#define CONFIG_SPEAR_MPMCREGS 100 #elif defined(CONFIG_SPEAR300) -#define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x94000000) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#define CONFIG_SYS_FSMC_BASE 0x94000000 #elif defined(CONFIG_SPEAR310) -#define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x44000000) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#define CONFIG_SYS_FSMC_BASE 0x44000000 #undef CONFIG_SYS_NAND_CLE #undef CONFIG_SYS_NAND_ALE #define CONFIG_SYS_NAND_CLE (1 << 17) #define CONFIG_SYS_NAND_ALE (1 << 16) -#define CONFIG_SPEAR_EMIBASE (0x4F000000) -#define CONFIG_SPEAR_RASBASE (0xB4000000) +#define CONFIG_SPEAR_EMIBASE 0x4F000000 +#define CONFIG_SPEAR_RASBASE 0xB4000000 + +#define CONFIG_SYS_MACB0_BASE 0xB0000000 +#define CONFIG_SYS_MACB1_BASE 0xB0800000 +#define CONFIG_SYS_MACB2_BASE 0xB1000000 +#define CONFIG_SYS_MACB3_BASE 0xB1800000 #elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x4C000000) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#define CONFIG_SYS_FSMC_BASE 0x4C000000 + +#define CONFIG_SPEAR_EMIBASE 0x40000000 +#define CONFIG_SPEAR_RASBASE 0xB3000000 -#define CONFIG_SPEAR_EMIBASE (0x40000000) -#define CONFIG_SPEAR_RASBASE (0xB3000000) +#define CONFIG_SYS_MACB0_BASE 0xAA000000 #endif #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-spear/spr_defs.h b/arch/arm/include/asm/arch-spear/spr_defs.h index fa8412ccfc..71d64a1992 100644 --- a/arch/arm/include/asm/arch-spear/spr_defs.h +++ b/arch/arm/include/asm/arch-spear/spr_defs.h @@ -28,6 +28,23 @@ extern int spear_board_init(ulong); extern void setfreq(unsigned int, unsigned int); extern unsigned int setfreq_sz; +void plat_ddr_init(void); +void soc_init(void); +void spear_late_init(void); +void plat_late_init(void); + +int snor_boot_selected(void); +int nand_boot_selected(void); +int pnor_boot_selected(void); +int usb_boot_selected(void); +int uart_boot_selected(void); +int tftp_boot_selected(void); +int i2c_boot_selected(void); +int spi_boot_selected(void); +int mmc_boot_selected(void); + +extern u32 mpmc_conf_vals[]; + struct chip_data { int cpufreq; int dramfreq; @@ -43,4 +60,10 @@ struct chip_data { #define MAC_OFF 0x2 #define MAC_LEN 0x6 +#define PNOR_WIDTH_8 0 +#define PNOR_WIDTH_16 1 +#define PNOR_WIDTH_32 2 +#define PNOR_WIDTH_NUM 3 +#define PNOR_WIDTH_SEARCH 0xff + #endif diff --git a/arch/arm/include/asm/arch-spear/spr_gpt.h b/arch/arm/include/asm/arch-spear/spr_gpt.h index 965b5abb9a..d95ba52597 100644 --- a/arch/arm/include/asm/arch-spear/spr_gpt.h +++ b/arch/arm/include/asm/arch-spear/spr_gpt.h @@ -79,7 +79,7 @@ struct gpt_regs { #define GPT_FREE_RUNNING 0xFFFF /* Timer, HZ specific defines */ -#define CONFIG_SPEAR_HZ (1000) -#define CONFIG_SPEAR_HZ_CLOCK (8300000) +#define CONFIG_SPEAR_HZ 1000 +#define CONFIG_SPEAR_HZ_CLOCK 8300000 #endif diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h index 8b96d9b52a..5f67a5fa20 100644 --- a/arch/arm/include/asm/arch-spear/spr_misc.h +++ b/arch/arm/include/asm/arch-spear/spr_misc.h @@ -37,7 +37,7 @@ struct misc_regs { u32 amba_clk_cfg; /* 0x24 */ u32 periph_clk_cfg; /* 0x28 */ u32 periph1_clken; /* 0x2C */ - u32 periph2_clken; /* 0x30 */ + u32 soc_core_id; /* 0x30 */ u32 ras_clken; /* 0x34 */ u32 periph1_rst; /* 0x38 */ u32 periph2_rst; /* 0x3C */ @@ -46,7 +46,7 @@ struct misc_regs { u32 prsc2_clk_cfg; /* 0x48 */ u32 prsc3_clk_cfg; /* 0x4C */ u32 amem_cfg_ctrl; /* 0x50 */ - u32 port_cfg_ctrl; /* 0x54 */ + u32 expi_clk_cfg; /* 0x54 */ u32 reserved_1; /* 0x58 */ u32 clcd_synth_clk; /* 0x5C */ u32 irda_synth_clk; /* 0x60 */ @@ -101,6 +101,37 @@ struct misc_regs { u32 ras_gpp2_out; /* 0x800C */ }; +/* SYNTH_CLK value*/ +#define SYNTH23 0x00020003 + +/* PLLx_FRQ value */ +#if defined(CONFIG_SPEAR3XX) +#define FREQ_332 0xA600010C +#define FREQ_266 0x8500010C +#elif defined(CONFIG_SPEAR600) +#define FREQ_332 0xA600010F +#define FREQ_266 0x8500010F +#endif + +/* PLL_CTR_REG */ +#define MEM_CLK_SEL_MSK 0x70000000 +#define MEM_CLK_HCLK 0x00000000 +#define MEM_CLK_2HCLK 0x10000000 +#define MEM_CLK_PLL2 0x30000000 + +#define EXPI_CLK_CFG_LOW_COMPR 0x2000 +#define EXPI_CLK_CFG_CLK_EN 0x0400 +#define EXPI_CLK_CFG_RST 0x0200 +#define EXPI_CLK_SYNT_EN 0x0010 +#define EXPI_CLK_CFG_SEL_PLL2 0x0004 +#define EXPI_CLK_CFG_INT_CLK_EN 0x0001 + +#define PLL2_CNTL_6UA 0x1c00 +#define PLL2_CNTL_SAMPLE 0x0008 +#define PLL2_CNTL_ENABLE 0x0004 +#define PLL2_CNTL_RESETN 0x0002 +#define PLL2_CNTL_LOCK 0x0001 + /* AUTO_CFG_REG value */ #define MISC_SOCCFGMSK 0x0000003F #define MISC_SOCCFG30 0x0000000C @@ -110,6 +141,8 @@ struct misc_regs { /* PERIPH_CLK_CFG value */ #define MISC_GPT3SYNTH 0x00000400 #define MISC_GPT4SYNTH 0x00000800 +#define CONFIG_SPEAR_UART48M 0 +#define CONFIG_SPEAR_UARTCLKMSK (0x1 << 4) /* PRSC_CLK_CFG value */ /* @@ -126,5 +159,115 @@ struct misc_regs { /* PERIPH1_CLKEN, PERIPH1_RST value */ #define MISC_USBDENB 0x01000000 +#define MISC_ETHENB 0x00800000 +#define MISC_SMIENB 0x00200000 +#define MISC_GPT3ENB 0x00010000 +#define MISC_GPIO4ENB 0x00002000 +#define MISC_GPT2ENB 0x00000800 +#define MISC_FSMCENB 0x00000200 +#define MISC_I2CENB 0x00000080 +#define MISC_SSP2ENB 0x00000070 +#define MISC_UART0ENB 0x00000008 + +/* PERIPH_CLK_CFG */ +#define XTALTIMEEN 0x00000001 +#define PLLTIMEEN 0x00000002 +#define CLCDCLK_SYNTH 0x00000000 +#define CLCDCLK_48MHZ 0x00000004 +#define CLCDCLK_EXT 0x00000008 +#define UARTCLK_MASK (0x1 << 4) +#define UARTCLK_48MHZ 0x00000000 +#define UARTCLK_SYNTH 0x00000010 +#define IRDACLK_48MHZ 0x00000000 +#define IRDACLK_SYNTH 0x00000020 +#define IRDACLK_EXT 0x00000040 +#define RTC_DISABLE 0x00000080 +#define GPT1CLK_48MHZ 0x00000000 +#define GPT1CLK_SYNTH 0x00000100 +#define GPT2CLK_48MHZ 0x00000000 +#define GPT2CLK_SYNTH 0x00000200 +#define GPT3CLK_48MHZ 0x00000000 +#define GPT3CLK_SYNTH 0x00000400 +#define GPT4CLK_48MHZ 0x00000000 +#define GPT4CLK_SYNTH 0x00000800 +#define GPT5CLK_48MHZ 0x00000000 +#define GPT5CLK_SYNTH 0x00001000 +#define GPT1_FREEZE 0x00002000 +#define GPT2_FREEZE 0x00004000 +#define GPT3_FREEZE 0x00008000 +#define GPT4_FREEZE 0x00010000 +#define GPT5_FREEZE 0x00020000 + +/* PERIPH1_CLKEN bits */ +#define PERIPH_ARM1_WE 0x00000001 +#define PERIPH_ARM1 0x00000002 +#define PERIPH_ARM2 0x00000004 +#define PERIPH_UART1 0x00000008 +#define PERIPH_UART2 0x00000010 +#define PERIPH_SSP1 0x00000020 +#define PERIPH_SSP2 0x00000040 +#define PERIPH_I2C 0x00000080 +#define PERIPH_JPEG 0x00000100 +#define PERIPH_FSMC 0x00000200 +#define PERIPH_FIRDA 0x00000400 +#define PERIPH_GPT4 0x00000800 +#define PERIPH_GPT5 0x00001000 +#define PERIPH_GPIO4 0x00002000 +#define PERIPH_SSP3 0x00004000 +#define PERIPH_ADC 0x00008000 +#define PERIPH_GPT3 0x00010000 +#define PERIPH_RTC 0x00020000 +#define PERIPH_GPIO3 0x00040000 +#define PERIPH_DMA 0x00080000 +#define PERIPH_ROM 0x00100000 +#define PERIPH_SMI 0x00200000 +#define PERIPH_CLCD 0x00400000 +#define PERIPH_GMAC 0x00800000 +#define PERIPH_USBD 0x01000000 +#define PERIPH_USBH1 0x02000000 +#define PERIPH_USBH2 0x04000000 +#define PERIPH_MPMC 0x08000000 +#define PERIPH_RAMW 0x10000000 +#define PERIPH_MPMC_EN 0x20000000 +#define PERIPH_MPMC_WE 0x40000000 +#define PERIPH_MPMCMSK 0x60000000 + +#define PERIPH_CLK_ALL 0x0FFFFFF8 +#define PERIPH_RST_ALL 0x00000004 + +/* DDR_PAD values */ +#define DDR_PAD_CNF_MSK 0x0000ffff +#define DDR_PAD_SW_CONF 0x00060000 +#define DDR_PAD_SSTL_SEL 0x00000001 +#define DDR_PAD_DRAM_TYPE 0x00008000 + +/* DDR_COMP values */ +#define DDR_COMP_ACCURATE 0x00000010 + +/* SoC revision stuff */ +#define SOC_PRI_SHFT 16 +#define SOC_SEC_SHFT 8 + +/* Revision definitions */ +#define SOC_SPEAR_NA 0 + +/* + * The definitons have started from + * 101 for SPEAr6xx + * 201 for SPEAr3xx + * 301 for SPEAr13xx + */ +#define SOC_SPEAR600_AA 101 +#define SOC_SPEAR600_AB 102 +#define SOC_SPEAR600_BA 103 +#define SOC_SPEAR600_BB 104 +#define SOC_SPEAR600_BC 105 +#define SOC_SPEAR600_BD 106 + +#define SOC_SPEAR300 201 +#define SOC_SPEAR310 202 +#define SOC_SPEAR320 203 + +extern int get_socrev(void); #endif diff --git a/arch/arm/include/asm/arch-spear/spr_nand.h b/arch/arm/include/asm/arch-spear/spr_nand.h deleted file mode 100644 index 2b63dc7e8e..0000000000 --- a/arch/arm/include/asm/arch-spear/spr_nand.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __SPR_NAND_H__ -#define __SPR_NAND_H__ - -struct fsmc_regs { - u32 reserved_1[0x10]; - u32 genmemctrl_pc; - u32 reserved_2; - u32 genmemctrl_comm; - u32 genmemctrl_attrib; - u32 reserved_3; - u32 genmemctrl_ecc; -}; - -/* genmemctrl_pc register definitions */ -#define FSMC_RESET (1 << 0) -#define FSMC_WAITON (1 << 1) -#define FSMC_ENABLE (1 << 2) -#define FSMC_DEVTYPE_NAND (1 << 3) -#define FSMC_DEVWID_8 (0 << 4) -#define FSMC_DEVWID_16 (1 << 4) -#define FSMC_ECCEN (1 << 6) -#define FSMC_ECCPLEN_512 (0 << 7) -#define FSMC_ECCPLEN_256 (1 << 7) -#define FSMC_TCLR_1 (1 << 9) -#define FSMC_TAR_1 (1 << 13) - -/* genmemctrl_comm register definitions */ -#define FSMC_TSET_0 (0 << 0) -#define FSMC_TWAIT_6 (6 << 8) -#define FSMC_THOLD_4 (4 << 16) -#define FSMC_THIZ_1 (1 << 24) - -extern int spear_nand_init(struct nand_chip *nand); -#endif diff --git a/arch/arm/include/asm/arch-spear/spr_smi.h b/arch/arm/include/asm/arch-spear/spr_smi.h deleted file mode 100644 index 06df74557f..0000000000 --- a/arch/arm/include/asm/arch-spear/spr_smi.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef SPR_SMI_H -#define SPR_SMI_H - -/* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ -/* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ - -#define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE -#define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE - -#define SMIBANK0_BASE (FLASH_START_ADDRESS) -#define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE) -#define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE) -#define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE) - -#define BANK0 0 -#define BANK1 1 -#define BANK2 2 -#define BANK3 3 - -struct smi_regs { - u32 smi_cr1; - u32 smi_cr2; - u32 smi_sr; - u32 smi_tr; - u32 smi_rr; -}; - -/* CONTROL REG 1 */ -#define BANK_EN 0x0000000F /* enables all banks */ -#define DSEL_TIME 0x00000060 /* Deselect time */ -#define PRESCAL5 0x00000500 /* AHB_CK prescaling value */ -#define PRESCALA 0x00000A00 /* AHB_CK prescaling value */ -#define PRESCAL3 0x00000300 /* AHB_CK prescaling value */ -#define PRESCAL4 0x00000400 /* AHB_CK prescaling value */ -#define SW_MODE 0x10000000 /* enables SW Mode */ -#define WB_MODE 0x20000000 /* Write Burst Mode */ -#define FAST_MODE 0x00008000 /* Fast Mode */ -#define HOLD1 0x00010000 - -/* CONTROL REG 2 */ -#define RD_STATUS_REG 0x00000400 /* reads status reg */ -#define WE 0x00000800 /* Write Enable */ -#define BANK0_SEL 0x00000000 /* Select Banck0 */ -#define BANK1_SEL 0x00001000 /* Select Banck1 */ -#define BANK2_SEL 0x00002000 /* Select Banck2 */ -#define BANK3_SEL 0x00003000 /* Select Banck3 */ -#define BANKSEL_SHIFT 12 -#define SEND 0x00000080 /* Send data */ -#define TX_LEN_1 0x00000001 /* data length = 1 byte */ -#define TX_LEN_2 0x00000002 /* data length = 2 byte */ -#define TX_LEN_3 0x00000003 /* data length = 3 byte */ -#define TX_LEN_4 0x00000004 /* data length = 4 byte */ -#define RX_LEN_1 0x00000010 /* data length = 1 byte */ -#define RX_LEN_2 0x00000020 /* data length = 2 byte */ -#define RX_LEN_3 0x00000030 /* data length = 3 byte */ -#define RX_LEN_4 0x00000040 /* data length = 4 byte */ -#define TFIE 0x00000100 /* Tx Flag Interrupt Enable */ -#define WCIE 0x00000200 /* WCF Interrupt Enable */ - -/* STATUS_REG */ -#define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */ -#define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */ -#define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */ -#define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */ -#define RSR 0x00000005 /* Read Status regiser */ -#define TFF 0x00000100 /* Transfer Finished FLag */ -#define WCF 0x00000200 /* Transfer Finished FLag */ -#define ERF1 0x00000400 /* Error Flag 1 */ -#define ERF2 0x00000800 /* Error Flag 2 */ -#define WM0 0x00001000 /* WM Bank 0 */ -#define WM1 0x00002000 /* WM Bank 1 */ -#define WM2 0x00004000 /* WM Bank 2 */ -#define WM3 0x00008000 /* WM Bank 3 */ -#define WM_SHIFT 12 - -/* TR REG */ -#define READ_ID 0x0000009F /* Read Identification */ -#define BULK_ERASE 0x000000C7 /* BULK erase */ -#define SECTOR_ERASE 0x000000D8 /* SECTOR erase */ -#define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */ - -struct flash_dev { - u32 density; - ulong size; - ushort sector_count; -}; - -#define SFLASH_PAGE_SIZE 0x100 /* flash page size */ -#define XFER_FINISH_TOUT 2 /* xfer finish timeout */ -#define WMODE_TOUT 2 /* write enable timeout */ - -#endif diff --git a/arch/arm/include/asm/arch-spear/spr_ssp.h b/arch/arm/include/asm/arch-spear/spr_ssp.h new file mode 100644 index 0000000000..4f144ee4d6 --- /dev/null +++ b/arch/arm/include/asm/arch-spear/spr_ssp.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2012 Stefan Roese <sr@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPR_SSP_H +#define _SPR_SSP_H + +struct ssp_regs { + u32 sspcr0; + u32 sspcr1; + u32 sspdr; + u32 sspsr; + u32 sspcpsr; + u32 sspimsc; + u32 sspicr; + u32 sspdmacr; +}; + +#define SSPCR0_FRF_MOT_SPI 0x0000 +#define SSPCR0_DSS_16BITS 0x000f + +#define SSPCR1_SSE 0x0002 + +#define SSPSR_TNF 0x2 +#define SSPSR_TFE 0x1 + +#endif diff --git a/arch/arm/include/asm/arch-spear/spr_syscntl.h b/arch/arm/include/asm/arch-spear/spr_syscntl.h index 3c92f094cf..2393d89c0f 100644 --- a/arch/arm/include/asm/arch-spear/spr_syscntl.h +++ b/arch/arm/include/asm/arch-spear/spr_syscntl.h @@ -21,6 +21,9 @@ * MA 02111-1307 USA */ +#ifndef __SYSCTRL_H +#define __SYSCTRL_H + struct syscntl_regs { u32 scctrl; u32 scsysstat; @@ -36,3 +39,14 @@ struct syscntl_regs { const u32 scperclken; const u32 scperstat; }; + +#define MODE_SHIFT 0x00000003 + +#define NORMAL 0x00000004 +#define SLOW 0x00000002 +#define DOZE 0x00000001 +#define SLEEP 0x00000000 + +#define PLL_TIM 0x01FFFFFF + +#endif diff --git a/arch/arm/include/asm/arch-spear/spr_xloader_table.h b/arch/arm/include/asm/arch-spear/spr_xloader_table.h deleted file mode 100644 index 7e3da18578..0000000000 --- a/arch/arm/include/asm/arch-spear/spr_xloader_table.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SPR_XLOADER_TABLE_H -#define _SPR_XLOADER_TABLE_H - -#define XLOADER_TABLE_VERSION_1_1 2 -#define XLOADER_TABLE_VERSION_1_2 3 - -#define XLOADER_TABLE_ADDRESS 0xD2801FF0 - -#define DDRMOBILE 1 -#define DDR2 2 - -#define REV_BA 1 -#define REV_AA 2 -#define REV_AB 3 - -struct xloader_table_1_1 { - unsigned short ddrfreq; - unsigned char ddrsize; - unsigned char ddrtype; - - unsigned char soc_rev; -} __attribute__ ((packed)); - -struct xloader_table_1_2 { - unsigned const char *version; - - unsigned short ddrfreq; - unsigned char ddrsize; - unsigned char ddrtype; - - unsigned char soc_rev; -} __attribute__ ((packed)); - -union table_contents { - struct xloader_table_1_1 table_1_1; - struct xloader_table_1_2 table_1_2; -}; - -struct xloader_table { - unsigned char table_version; - union table_contents table; -} __attribute__ ((packed)); - -#endif diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h index 1d3ae38644..ff83bbf293 100644 --- a/arch/arm/include/asm/arch-tegra2/clock.h +++ b/arch/arm/include/asm/arch-tegra2/clock.h @@ -186,8 +186,9 @@ enum periph_id { /* Mask value for a clock (within PERIPH_REG(id)) */ #define PERIPH_MASK(id) (1 << ((id) & 0x1f)) -/* return 1 if a PLL ID is in range */ -#define clock_id_isvalid(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) +/* return 1 if a PLL ID is in range, and not a simple PLL */ +#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \ + (id) < CLOCK_ID_FIRST_SIMPLE) /* PLL stabilization delay in usec */ #define CLOCK_PLL_STABLE_DELAY_US 300 diff --git a/arch/arm/include/asm/arch-tegra2/funcmux.h b/arch/arm/include/asm/arch-tegra2/funcmux.h index ae73c72ebe..b16c496122 100644 --- a/arch/arm/include/asm/arch-tegra2/funcmux.h +++ b/arch/arm/include/asm/arch-tegra2/funcmux.h @@ -30,6 +30,9 @@ enum { /* UART configs */ FUNCMUX_UART1_IRRX_IRTX = 0, + FUNCMUX_UART1_UAA_UAB, + FUNCMUX_UART1_GPU, + FUNCMUX_UART1_SDIO1, FUNCMUX_UART2_IRDA = 0, FUNCMUX_UART4_GMC = 0, @@ -41,6 +44,7 @@ enum { FUNCMUX_I2C3_DTF = 0, /* SDMMC configs */ + FUNCMUX_SDMMC1_SDIO1_4BIT = 0, FUNCMUX_SDMMC2_DTA_DTD_8BIT = 0, FUNCMUX_SDMMC3_SDB_4BIT = 0, FUNCMUX_SDMMC3_SDB_SLXA_8BIT, diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h b/arch/arm/include/asm/arch-tegra2/gpio.h index 41e66fe1b1..40ddb02565 100644 --- a/arch/arm/include/asm/arch-tegra2/gpio.h +++ b/arch/arm/include/asm/arch-tegra2/gpio.h @@ -2,6 +2,7 @@ * Copyright (c) 2011, Google Inc. All rights reserved. * See file CREDITS for list of people who contributed to this * project. + * Portions Copyright 2011-2012 NVIDIA Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,8 +20,8 @@ * MA 02111-1307 USA */ -#ifndef _TEGRA2_GPIO_H_ -#define _TEGRA2_GPIO_H_ +#ifndef _TEGRA_GPIO_H_ +#define _TEGRA_GPIO_H_ /* * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports, @@ -286,4 +287,4 @@ enum gpio_pin { void gpio_info(void); #define gpio_status() gpio_info() -#endif /* TEGRA2_GPIO_H_ */ +#endif /* TEGRA_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/pinmux.h b/arch/arm/include/asm/arch-tegra2/pinmux.h index 469d742cc3..03fa7ca643 100644 --- a/arch/arm/include/asm/arch-tegra2/pinmux.h +++ b/arch/arm/include/asm/arch-tegra2/pinmux.h @@ -67,7 +67,7 @@ enum pmux_pingrp { PINGRP_KBCF, PINGRP_GMA, PINGRP_GMC, - PINGRP_SDMMC1, + PINGRP_SDIO1, PINGRP_OWC, /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h index d4ada10ea8..3c8d8a84b5 100644 --- a/arch/arm/include/asm/arch-tegra2/tegra2.h +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h @@ -60,6 +60,10 @@ struct timerus { /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */ #define AP20_WB_RUN_ADDRESS 0x40020000 +#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */ +#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */ +#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ + /* These are the available SKUs (product types) for Tegra */ enum { SKU_ID_T20 = 0x8, diff --git a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h b/arch/arm/include/asm/arch-tegra2/tegra_spi.h index ceec4287a3..892d90c00b 100644 --- a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h +++ b/arch/arm/include/asm/arch-tegra2/tegra_spi.h @@ -1,7 +1,7 @@ /* * NVIDIA Tegra2 SPI-FLASH controller * - * Copyright 2010-2011 NVIDIA Corporation + * Copyright 2010-2012 NVIDIA Corporation * * This software may be used and distributed according to the * terms of the GNU Public License, Version 2, incorporated @@ -22,8 +22,8 @@ * MA 02111-1307 USA */ -#ifndef _TEGRA2_SPI_H_ -#define _TEGRA2_SPI_H_ +#ifndef _TEGRA_SPI_H_ +#define _TEGRA_SPI_H_ #include <asm/types.h> @@ -72,5 +72,4 @@ struct spi_tegra { #define SPI_TIMEOUT 1000 #define TEGRA2_SPI_MAX_FREQ 52000000 - -#endif /* _TEGRA2_SPI_H_ */ +#endif /* _TEGRA_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h b/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h index e4503b15b0..82ac180acd 100644 --- a/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h +++ b/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h @@ -29,7 +29,7 @@ * time! If the board file provides this, the board config will declare it. * Let this be a lesson for others. */ -void pinmux_select_uart(NS16550_t regs); +void pinmux_select_uart(void); /* * Signal that we are about the use the SPI bus. @@ -38,7 +38,7 @@ void pinmux_select_spi(void); #else /* not CONFIG_SPI_UART_SWITCH */ -static inline void pinmux_select_uart(NS16550_t regs) {} +static inline void pinmux_select_uart(void) {} static inline void pinmux_select_spi(void) {} #endif diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index f1e3ad212e..674c3de661 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -471,6 +471,49 @@ #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 #define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) +/*EMIF_READ_WRITE_LEVELING_CONTROL*/ +#define EMIF_REG_RDWRLVLFULL_START_SHIFT 31 +#define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31) +#define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24 +#define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24) +#define EMIF_REG_RDLVLINC_INT_SHIFT 16 +#define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16) +#define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8 +#define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8) +#define EMIF_REG_WRLVLINC_INT_SHIFT 0 +#define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0) + +/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/ +#define EMIF_REG_RDWRLVL_EN_SHIFT 31 +#define EMIF_REG_RDWRLVL_EN_MASK (1 << 31) +#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24 +#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24) +#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16 +#define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16) +#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8 +#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8) +#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0 +#define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0) + +/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/ +#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0 +#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0) + +/*Leveling Fields */ +#define DDR3_WR_LVL_INT 0x73 +#define DDR3_RD_LVL_INT 0x33 +#define DDR3_RD_LVL_GATE_INT 0x59 +#define RD_RW_LVL_INC_PRE 0x0 +#define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT) + +#define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \ + | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \ + | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \ + | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT)) + +#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 +#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 + /* DMM */ #define DMM_BASE 0x4E000040 @@ -650,6 +693,7 @@ struct dmm_lisa_map_regs { }; extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; +extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; #define CS0 0 #define CS1 1 @@ -1073,6 +1117,10 @@ struct emif_regs { u32 emif_ddr_ext_phy_ctrl_3; u32 emif_ddr_ext_phy_ctrl_4; u32 emif_ddr_ext_phy_ctrl_5; + u32 emif_rd_wr_lvl_rmp_win; + u32 emif_rd_wr_lvl_rmp_ctl; + u32 emif_rd_wr_lvl_ctl; + u32 emif_rd_wr_exec_thresh; }; /* assert macros */ @@ -1093,11 +1141,13 @@ void emif_get_device_timings(u32 emif_nr, const struct lpddr2_device_timings **cs1_device_timings); #endif +void do_ext_phy_settings(u32 base, const struct emif_regs *regs); + #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS extern u32 *const T_num; extern u32 *const T_den; extern u32 *const emif_sizes; #endif - +void config_data_eye_leveling_samples(u32 emif_base); #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 459b6b16e2..4e95eee59b 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -136,4 +136,5 @@ static inline u32 omap_revision(void) /* omap5 */ #define OMAP5430_SILICON_ID_INVALID 0 #define OMAP5430_ES1_0 0x54300100 +#define OMAP5432_ES1_0 0x54320100 #endif /* _OMAP_COMMON_H_ */ diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index 4ca75f9f93..9f3cae5ece 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -52,6 +52,7 @@ void cpu_init_cp15(void); /* cpu/.../arch/cpu.c */ int arch_cpu_init(void); int arch_misc_init(void); +int arch_early_init_r(void); /* board/.../... */ int board_init(void); |