diff options
Diffstat (limited to 'arch/arm/include/asm/arch-vybrid')
| -rw-r--r-- | arch/arm/include/asm/arch-vybrid/clock.h | 49 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vybrid/crm_regs.h | 25 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vybrid/iomux.h | 322 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vybrid/sys_proto.h | 39 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vybrid/timer.h | 405 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vybrid/vybrid-pins.h | 88 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vybrid/vybrid-regs.h | 697 |
7 files changed, 1625 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-vybrid/clock.h b/arch/arm/include/asm/arch-vybrid/clock.h new file mode 100644 index 0000000000..6a90e023c6 --- /dev/null +++ b/arch/arm/include/asm/arch-vybrid/clock.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +enum vybrid_clock { + VYBRID_ARM_CLK = 0, + VYBRID_AHB_CLK, + VYBRID_IPG_CLK, + VYBRID_IPG_PERCLK, + VYBRID_UART_CLK, + VYBRID_CSPI_CLK, + VYBRID_FEC_CLK, +}; + +unsigned int vybrid_decode_pll(unsigned int pll, unsigned int f_ref); + +u32 vybrid_get_uartclk(void); +u32 vybrid_get_fecclk(void); +unsigned int vybrid_get_clock(enum vybrid_clock clk); + +void set_usb_phy2_clk(void); +void enable_usb_phy2_clk(unsigned char enable); +void set_usboh3_clk(void); +void enable_usboh3_clk(unsigned char enable); + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-vybrid/crm_regs.h b/arch/arm/include/asm/arch-vybrid/crm_regs.h new file mode 100644 index 0000000000..f7894d2d72 --- /dev/null +++ b/arch/arm/include/asm/arch-vybrid/crm_regs.h @@ -0,0 +1,25 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARCH_ARM_MACH_VYBRID_CRM_REGS_H__ +#define __ARCH_ARM_MACH_VYBRID_CRM_REGS_H__ + +#endif /* __ARCH_ARM_MACH_VYBRID_CRM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-vybrid/iomux.h b/arch/arm/include/asm/arch-vybrid/iomux.h new file mode 100644 index 0000000000..e5ec5ddc03 --- /dev/null +++ b/arch/arm/include/asm/arch-vybrid/iomux.h @@ -0,0 +1,322 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MACH_VYBRID_IOMUX_H__ +#define __MACH_VYBRID_IOMUX_H__ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/vybrid-regs.h> +#include <asm/arch/vybrid-pins.h> + +#define IOMUXC_PAD_000 (IOMUXC_BASE_ADDR + 0x0000) +#define IOMUXC_PAD_001 (IOMUXC_BASE_ADDR + 0x0004) +#define IOMUXC_PAD_002 (IOMUXC_BASE_ADDR + 0x0008) +#define IOMUXC_PAD_003 (IOMUXC_BASE_ADDR + 0x000C) +#define IOMUXC_PAD_004 (IOMUXC_BASE_ADDR + 0x0010) +#define IOMUXC_PAD_005 (IOMUXC_BASE_ADDR + 0x0014) +#define IOMUXC_PAD_006 (IOMUXC_BASE_ADDR + 0x0018) +#define IOMUXC_PAD_007 (IOMUXC_BASE_ADDR + 0x001C) +#define IOMUXC_PAD_008 (IOMUXC_BASE_ADDR + 0x0020) +#define IOMUXC_PAD_009 (IOMUXC_BASE_ADDR + 0x0024) +#define IOMUXC_PAD_010 (IOMUXC_BASE_ADDR + 0x0028) +#define IOMUXC_PAD_011 (IOMUXC_BASE_ADDR + 0x002C) +#define IOMUXC_PAD_012 (IOMUXC_BASE_ADDR + 0x0030) +#define IOMUXC_PAD_013 (IOMUXC_BASE_ADDR + 0x0034) +#define IOMUXC_PAD_014 (IOMUXC_BASE_ADDR + 0x0038) +#define IOMUXC_PAD_015 (IOMUXC_BASE_ADDR + 0x003C) +#define IOMUXC_PAD_016 (IOMUXC_BASE_ADDR + 0x0040) +#define IOMUXC_PAD_017 (IOMUXC_BASE_ADDR + 0x0044) +#define IOMUXC_PAD_018 (IOMUXC_BASE_ADDR + 0x0048) +#define IOMUXC_PAD_019 (IOMUXC_BASE_ADDR + 0x004C) +#define IOMUXC_PAD_020 (IOMUXC_BASE_ADDR + 0x0050) +#define IOMUXC_PAD_021 (IOMUXC_BASE_ADDR + 0x0054) +#define IOMUXC_PAD_022 (IOMUXC_BASE_ADDR + 0x0058) +#define IOMUXC_PAD_023 (IOMUXC_BASE_ADDR + 0x005C) +#define IOMUXC_PAD_024 (IOMUXC_BASE_ADDR + 0x0060) +#define IOMUXC_PAD_025 (IOMUXC_BASE_ADDR + 0x0064) +#define IOMUXC_PAD_026 (IOMUXC_BASE_ADDR + 0x0068) +#define IOMUXC_PAD_027 (IOMUXC_BASE_ADDR + 0x006C) +#define IOMUXC_PAD_028 (IOMUXC_BASE_ADDR + 0x0070) +#define IOMUXC_PAD_029 (IOMUXC_BASE_ADDR + 0x0074) +#define IOMUXC_PAD_030 (IOMUXC_BASE_ADDR + 0x0078) +#define IOMUXC_PAD_031 (IOMUXC_BASE_ADDR + 0x007C) +#define IOMUXC_PAD_032 (IOMUXC_BASE_ADDR + 0x0080) +#define IOMUXC_PAD_033 (IOMUXC_BASE_ADDR + 0x0084) +#define IOMUXC_PAD_034 (IOMUXC_BASE_ADDR + 0x0088) +#define IOMUXC_PAD_035 (IOMUXC_BASE_ADDR + 0x008C) +#define IOMUXC_PAD_036 (IOMUXC_BASE_ADDR + 0x0090) +#define IOMUXC_PAD_037 (IOMUXC_BASE_ADDR + 0x0094) +#define IOMUXC_PAD_038 (IOMUXC_BASE_ADDR + 0x0098) +#define IOMUXC_PAD_039 (IOMUXC_BASE_ADDR + 0x009C) +#define IOMUXC_PAD_040 (IOMUXC_BASE_ADDR + 0x00A0) +#define IOMUXC_PAD_041 (IOMUXC_BASE_ADDR + 0x00A4) +#define IOMUXC_PAD_042 (IOMUXC_BASE_ADDR + 0x00A8) +#define IOMUXC_PAD_043 (IOMUXC_BASE_ADDR + 0x00AC) +#define IOMUXC_PAD_044 (IOMUXC_BASE_ADDR + 0x00B0) +#define IOMUXC_PAD_045 (IOMUXC_BASE_ADDR + 0x00B4) +#define IOMUXC_PAD_046 (IOMUXC_BASE_ADDR + 0x00B8) +#define IOMUXC_PAD_047 (IOMUXC_BASE_ADDR + 0x00BC) +#define IOMUXC_PAD_048 (IOMUXC_BASE_ADDR + 0x00C0) +#define IOMUXC_PAD_049 (IOMUXC_BASE_ADDR + 0x00C4) +#define IOMUXC_PAD_050 (IOMUXC_BASE_ADDR + 0x00C8) +#define IOMUXC_PAD_051 (IOMUXC_BASE_ADDR + 0x00CC) +#define IOMUXC_PAD_052 (IOMUXC_BASE_ADDR + 0x00D0) +#define IOMUXC_PAD_053 (IOMUXC_BASE_ADDR + 0x00D4) +#define IOMUXC_PAD_054 (IOMUXC_BASE_ADDR + 0x00D8) +#define IOMUXC_PAD_055 (IOMUXC_BASE_ADDR + 0x00DC) +#define IOMUXC_PAD_056 (IOMUXC_BASE_ADDR + 0x00E0) +#define IOMUXC_PAD_057 (IOMUXC_BASE_ADDR + 0x00E4) +#define IOMUXC_PAD_058 (IOMUXC_BASE_ADDR + 0x00E8) +#define IOMUXC_PAD_059 (IOMUXC_BASE_ADDR + 0x00EC) +#define IOMUXC_PAD_060 (IOMUXC_BASE_ADDR + 0x00F0) +#define IOMUXC_PAD_061 (IOMUXC_BASE_ADDR + 0x00F4) +#define IOMUXC_PAD_062 (IOMUXC_BASE_ADDR + 0x00F8) +#define IOMUXC_PAD_063 (IOMUXC_BASE_ADDR + 0x00FC) +#define IOMUXC_PAD_064 (IOMUXC_BASE_ADDR + 0x0100) +#define IOMUXC_PAD_065 (IOMUXC_BASE_ADDR + 0x0104) +#define IOMUXC_PAD_066 (IOMUXC_BASE_ADDR + 0x0108) +#define IOMUXC_PAD_067 (IOMUXC_BASE_ADDR + 0x010C) +#define IOMUXC_PAD_068 (IOMUXC_BASE_ADDR + 0x0110) +#define IOMUXC_PAD_069 (IOMUXC_BASE_ADDR + 0x0114) +#define IOMUXC_PAD_070 (IOMUXC_BASE_ADDR + 0x0118) +#define IOMUXC_PAD_071 (IOMUXC_BASE_ADDR + 0x011C) +#define IOMUXC_PAD_072 (IOMUXC_BASE_ADDR + 0x0120) +#define IOMUXC_PAD_073 (IOMUXC_BASE_ADDR + 0x0124) +#define IOMUXC_PAD_074 (IOMUXC_BASE_ADDR + 0x0128) +#define IOMUXC_PAD_075 (IOMUXC_BASE_ADDR + 0x012C) +#define IOMUXC_PAD_076 (IOMUXC_BASE_ADDR + 0x0130) +#define IOMUXC_PAD_077 (IOMUXC_BASE_ADDR + 0x0134) +#define IOMUXC_PAD_078 (IOMUXC_BASE_ADDR + 0x0138) +#define IOMUXC_PAD_079 (IOMUXC_BASE_ADDR + 0x013C) +#define IOMUXC_PAD_080 (IOMUXC_BASE_ADDR + 0x0140) +#define IOMUXC_PAD_081 (IOMUXC_BASE_ADDR + 0x0144) +#define IOMUXC_PAD_082 (IOMUXC_BASE_ADDR + 0x0148) +#define IOMUXC_PAD_083 (IOMUXC_BASE_ADDR + 0x014C) +#define IOMUXC_PAD_084 (IOMUXC_BASE_ADDR + 0x0150) +#define IOMUXC_PAD_085 (IOMUXC_BASE_ADDR + 0x0154) +#define IOMUXC_PAD_086 (IOMUXC_BASE_ADDR + 0x0158) +#define IOMUXC_PAD_087 (IOMUXC_BASE_ADDR + 0x015C) +#define IOMUXC_PAD_088 (IOMUXC_BASE_ADDR + 0x0160) +#define IOMUXC_PAD_089 (IOMUXC_BASE_ADDR + 0x0164) +#define IOMUXC_PAD_090 (IOMUXC_BASE_ADDR + 0x0168) +#define IOMUXC_PAD_091 (IOMUXC_BASE_ADDR + 0x016C) +#define IOMUXC_PAD_092 (IOMUXC_BASE_ADDR + 0x0170) +#define IOMUXC_PAD_093 (IOMUXC_BASE_ADDR + 0x0174) +#define IOMUXC_PAD_094 (IOMUXC_BASE_ADDR + 0x0178) +#define IOMUXC_PAD_095 (IOMUXC_BASE_ADDR + 0x017C) +#define IOMUXC_PAD_096 (IOMUXC_BASE_ADDR + 0x0180) +#define IOMUXC_PAD_097 (IOMUXC_BASE_ADDR + 0x0184) +#define IOMUXC_PAD_098 (IOMUXC_BASE_ADDR + 0x0188) +#define IOMUXC_PAD_099 (IOMUXC_BASE_ADDR + 0x018C) +#define IOMUXC_PAD_100 (IOMUXC_BASE_ADDR + 0x0190) +#define IOMUXC_PAD_101 (IOMUXC_BASE_ADDR + 0x0194) +#define IOMUXC_PAD_102 (IOMUXC_BASE_ADDR + 0x0198) +#define IOMUXC_PAD_103 (IOMUXC_BASE_ADDR + 0x019C) +#define IOMUXC_PAD_104 (IOMUXC_BASE_ADDR + 0x01A0) +#define IOMUXC_PAD_105 (IOMUXC_BASE_ADDR + 0x01A4) +#define IOMUXC_PAD_106 (IOMUXC_BASE_ADDR + 0x01A8) +#define IOMUXC_PAD_107 (IOMUXC_BASE_ADDR + 0x01AC) +#define IOMUXC_PAD_108 (IOMUXC_BASE_ADDR + 0x01B0) +#define IOMUXC_PAD_109 (IOMUXC_BASE_ADDR + 0x01B4) +#define IOMUXC_PAD_110 (IOMUXC_BASE_ADDR + 0x01B8) +#define IOMUXC_PAD_111 (IOMUXC_BASE_ADDR + 0x01BC) +#define IOMUXC_PAD_112 (IOMUXC_BASE_ADDR + 0x01C0) +#define IOMUXC_PAD_113 (IOMUXC_BASE_ADDR + 0x01C4) +#define IOMUXC_PAD_114 (IOMUXC_BASE_ADDR + 0x01C8) +#define IOMUXC_PAD_115 (IOMUXC_BASE_ADDR + 0x01CC) +#define IOMUXC_PAD_116 (IOMUXC_BASE_ADDR + 0x01D0) +#define IOMUXC_PAD_117 (IOMUXC_BASE_ADDR + 0x01D4) +#define IOMUXC_PAD_118 (IOMUXC_BASE_ADDR + 0x01D8) +#define IOMUXC_PAD_119 (IOMUXC_BASE_ADDR + 0x01DC) +#define IOMUXC_PAD_120 (IOMUXC_BASE_ADDR + 0x01E0) +#define IOMUXC_PAD_121 (IOMUXC_BASE_ADDR + 0x01E4) +#define IOMUXC_PAD_122 (IOMUXC_BASE_ADDR + 0x01E8) +#define IOMUXC_PAD_123 (IOMUXC_BASE_ADDR + 0x01EC) +#define IOMUXC_PAD_124 (IOMUXC_BASE_ADDR + 0x01F0) +#define IOMUXC_PAD_125 (IOMUXC_BASE_ADDR + 0x01F4) +#define IOMUXC_PAD_126 (IOMUXC_BASE_ADDR + 0x01F8) +#define IOMUXC_PAD_127 (IOMUXC_BASE_ADDR + 0x01FC) +#define IOMUXC_PAD_128 (IOMUXC_BASE_ADDR + 0x0200) +#define IOMUXC_PAD_129 (IOMUXC_BASE_ADDR + 0x0204) +#define IOMUXC_PAD_130 (IOMUXC_BASE_ADDR + 0x0208) +#define IOMUXC_PAD_131 (IOMUXC_BASE_ADDR + 0x020C) +#define IOMUXC_PAD_132 (IOMUXC_BASE_ADDR + 0x0210) +#define IOMUXC_PAD_133 (IOMUXC_BASE_ADDR + 0x0214) +#define IOMUXC_PAD_134 (IOMUXC_BASE_ADDR + 0x0218) + +#define IOMUXC_DDR_RESET (IOMUXC_BASE_ADDR + 0x021C) +#define IOMUXC_DDR_A15 (IOMUXC_BASE_ADDR + 0x0220) +#define IOMUXC_DDR_A14 (IOMUXC_BASE_ADDR + 0x0224) +#define IOMUXC_DDR_A13 (IOMUXC_BASE_ADDR + 0x0228) +#define IOMUXC_DDR_A12 (IOMUXC_BASE_ADDR + 0x022C) +#define IOMUXC_DDR_A11 (IOMUXC_BASE_ADDR + 0x0230) +#define IOMUXC_DDR_A10 (IOMUXC_BASE_ADDR + 0x0234) +#define IOMUXC_DDR_A9 (IOMUXC_BASE_ADDR + 0x0238) +#define IOMUXC_DDR_A8 (IOMUXC_BASE_ADDR + 0x023C) +#define IOMUXC_DDR_A7 (IOMUXC_BASE_ADDR + 0x0240) +#define IOMUXC_DDR_A6 (IOMUXC_BASE_ADDR + 0x0244) +#define IOMUXC_DDR_A5 (IOMUXC_BASE_ADDR + 0x0248) +#define IOMUXC_DDR_A4 (IOMUXC_BASE_ADDR + 0x024C) +#define IOMUXC_DDR_A3 (IOMUXC_BASE_ADDR + 0x0250) +#define IOMUXC_DDR_A2 (IOMUXC_BASE_ADDR + 0x0254) +#define IOMUXC_DDR_A1 (IOMUXC_BASE_ADDR + 0x0258) +#define IOMUXC_DDR_A0 (IOMUXC_BASE_ADDR + 0x025C) + +#define IOMUXC_DDR_BA2 (IOMUXC_BASE_ADDR + 0x0260) +#define IOMUXC_DDR_BA1 (IOMUXC_BASE_ADDR + 0x0264) +#define IOMUXC_DDR_BA0 (IOMUXC_BASE_ADDR + 0x0268) + +#define IOMUXC_DDR_CAS (IOMUXC_BASE_ADDR + 0x026C) + +#define IOMUXC_DDR_CKE (IOMUXC_BASE_ADDR + 0x0270) + +#define IOMUXC_DDR_CLK (IOMUXC_BASE_ADDR + 0x0274) + +#define IOMUXC_DDR_CS (IOMUXC_BASE_ADDR + 0x0278) + +#define IOMUXC_DDR_D15 (IOMUXC_BASE_ADDR + 0x027C) +#define IOMUXC_DDR_D14 (IOMUXC_BASE_ADDR + 0x0280) +#define IOMUXC_DDR_D13 (IOMUXC_BASE_ADDR + 0x0284) +#define IOMUXC_DDR_D12 (IOMUXC_BASE_ADDR + 0x0288) +#define IOMUXC_DDR_D11 (IOMUXC_BASE_ADDR + 0x028C) +#define IOMUXC_DDR_D10 (IOMUXC_BASE_ADDR + 0x0290) +#define IOMUXC_DDR_D9 (IOMUXC_BASE_ADDR + 0x0294) +#define IOMUXC_DDR_D8 (IOMUXC_BASE_ADDR + 0x0298) +#define IOMUXC_DDR_D7 (IOMUXC_BASE_ADDR + 0x029C) +#define IOMUXC_DDR_D6 (IOMUXC_BASE_ADDR + 0x02A0) +#define IOMUXC_DDR_D5 (IOMUXC_BASE_ADDR + 0x02A4) +#define IOMUXC_DDR_D4 (IOMUXC_BASE_ADDR + 0x02A8) +#define IOMUXC_DDR_D3 (IOMUXC_BASE_ADDR + 0x02AC) +#define IOMUXC_DDR_D2 (IOMUXC_BASE_ADDR + 0x02B0) +#define IOMUXC_DDR_D1 (IOMUXC_BASE_ADDR + 0x02B4) +#define IOMUXC_DDR_D0 (IOMUXC_BASE_ADDR + 0x02B8) + +#define IOMUXC_DDR_DQM1 (IOMUXC_BASE_ADDR + 0x02BC) +#define IOMUXC_DDR_DQM0 (IOMUXC_BASE_ADDR + 0x02C0) + +#define IOMUXC_DDR_DQS1 (IOMUXC_BASE_ADDR + 0x02C4) +#define IOMUXC_DDR_DQS0 (IOMUXC_BASE_ADDR + 0x02C8) + +#define IOMUXC_DDR_RAS (IOMUXC_BASE_ADDR + 0x02CC) +#define IOMUXC_DDR_WE (IOMUXC_BASE_ADDR + 0x02D0) + +#define IOMUXC_DDR_ODT0 (IOMUXC_BASE_ADDR + 0x02D4) +#define IOMUXC_DDR_ODT1 (IOMUXC_BASE_ADDR + 0x02D8) + +#define IOMUXC_DDR_DDRBYTE1 (IOMUXC_BASE_ADDR + 0x02DC) +#define IOMUXC_DDR_DDRBYTE0 (IOMUXC_BASE_ADDR + 0x02E0) + +#define IOMUXC_SDHC_DUMMY1 (IOMUXC_BASE_ADDR + 0x02E4) +#define IOMUXC_SDHC_DUMMY2 (IOMUXC_BASE_ADDR + 0x02E8) + +#define IOMUXC_AUD_EXTCLK_INP (IOMUXC_BASE_ADDR + 0x02EC) +#define IOMUXC_ENET_EXTCLK_INP (IOMUXC_BASE_ADDR + 0x02F0) +#define IOMUXC_ENET_TSCLK_INP (IOMUXC_BASE_ADDR + 0x02F4) + +typedef struct pad_iomux { + u8 mod; + u8 spd; + u8 sre; + u8 ode; + u8 hys; + u8 dse; + u8 pus; + u8 pke; + u8 pue; + u8 obe; + u8 ibe; +} pad_iomux_t; + +#define PADIOMUX_SET(val, mod, spd, sre, ode, hys, dse, pus, pke, pue, obe, ibe)\ + (val = (((mod & 7) << 20) | ((spd & 3) << 12) | \ + ((sre & 1) << 11) | ((ode & 1) << 10) | \ + ((hys & 1) << 9) | ((dse & 7) << 6) | \ + ((pus & 3) << 4) | ((pke & 1) << 3) | \ + ((pue & 1) << 2) | ((obe & 1) << 1) | \ + (ibe & 1))) + +#define DDRIOMUX_SET(inp, trim, hys, dse, pus, pke, pue) \ + (((inp & 1) << 16) | ((trim & 3) << 14) | \ + ((hys & 1) << 9) | ((dse & 7) << 6) | \ + ((pus & 3) << 4) | ((pke & 1) << 3) | \ + ((pue & 1) << 2)) + +#define MUX_MODE_ALT0 0x00 +#define MUX_MODE_ALT1 0x01 +#define MUX_MODE_ALT2 0x02 +#define MUX_MODE_ALT3 0x03 +#define MUX_MODE_ALT4 0x04 +#define MUX_MODE_ALT5 0x05 +#define MUX_MODE_ALT6 0x06 +#define MUX_MODE_ALT7 0x07 + +#define MUX_SPD_50MHZ 0x00 +#define MUX_SPD_100MHZ 0x02 +#define MUX_SPD_200MHZ 0x03 + +#define MUX_SRE_SLOW 0 +#define MUX_SRE_FAST 1 + +#define MUX_ODE_CMOS 0 +#define MUX_ODE_OPEN 1 + +#define MUX_HYS_CMOS 0 +#define MUX_HYS_SCHMITT 1 + +#define MUX_DSE_20_OHM 7 +#define MUX_DSE_25_OHM 6 +#define MUX_DSE_30_OHM 5 +#define MUX_DSE_37_OHM 4 +#define MUX_DSE_50_OHM 3 +#define MUX_DSE_75_OHM 2 +#define MUX_DSE_150_OHM 1 +#define MUX_DSE_DIS 0 + +#define MUX_PUS_22KOHM_UP 3 +#define MUX_PUS_100KOHM_UP 2 +#define MUX_PUS_47KOHM_UP 1 +#define MUX_PUS_100KOHM_DN 0 + +#define MUX_PKE_EN 1 +#define MUX_PKE_DIS 0 + +#define MUX_PUE_PULLEN 1 +#define MUX_PUE_KEEPEREN 0 + +#define MUX_OBE_EN 1 +#define MUX_OBE_DIS 0 + +#define MUX_IBE_EN 1 +#define MUX_IBE_DIS 0 + +#define MUX_DDR_INPUT_DIFF 1 +#define MUX_DDR_INPUT_CMOS 0 + +#define MUX_DDR_TRIM_150PS 3 +#define MUX_DDR_TRIM_100PS 2 +#define MUX_DDR_TRIM_50PS 1 +#define MUX_DDR_TRIM_MIN 0 + +void pad_iomux_set(u32 pad_addr, pad_iomux_t *padio); + +#endif /* __MACH_VYBRID_IOMUX_H__ */ diff --git a/arch/arm/include/asm/arch-vybrid/sys_proto.h b/arch/arm/include/asm/arch-vybrid/sys_proto.h new file mode 100644 index 0000000000..13d12ee1a4 --- /dev/null +++ b/arch/arm/include/asm/arch-vybrid/sys_proto.h @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +u32 get_cpu_rev(void); +#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +void sdelay(unsigned long); +void set_chipselect_size(int const); + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ + +int fecmxc_initialize(bd_t *bis); + +#endif diff --git a/arch/arm/include/asm/arch-vybrid/timer.h b/arch/arm/include/asm/arch-vybrid/timer.h new file mode 100644 index 0000000000..681a2acfa9 --- /dev/null +++ b/arch/arm/include/asm/arch-vybrid/timer.h @@ -0,0 +1,405 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_TIMER_H +#define __ASM_ARCH_TIMER_H + +struct ftm_regs { + u32 sc; /* 0x00 */ + u32 cnt; /* 0x04 */ + u32 mod; /* 0x08 */ + u32 c0sc; /* 0x0C */ + u32 c0v; /* 0x10 */ + u32 c1sc; /* 0x14 */ + u32 c1v; /* 0x18 */ + u32 c2sc; /* 0x1C */ + u32 c2v; /* 0x20 */ + u32 c3sc; /* 0x24 */ + u32 c3v; /* 0x28 */ + u32 c4sc; /* 0x2C */ + u32 c4v; /* 0x30 */ + u32 c5sc; /* 0x34 */ + u32 c5v; /* 0x38 */ + u32 c6sc; /* 0x3C */ + u32 c6v; /* 0x40 */ + u32 c7sc; /* 0x44 */ + u32 c7v; /* 0x48 */ + u32 cntin; /* 0x4C */ + u32 status; /* 0x50 */ + u32 mode; /* 0x54 */ + u32 sync; /* 0x58 */ + u32 outinit; /* 0x5C */ + u32 outmask; /* 0x60 */ + u32 combine; /* 0x64 */ + u32 deadtime; /* 0x68 */ + u32 exttrig; /* 0x6C */ + u32 pol; /* 0x70 */ + u32 fms; /* 0x74 */ + u32 filter; /* 0x78 */ + u32 fltctrl; /* 0x7C */ + u32 qdctrl; /* 0x80 */ + u32 conf; /* 0x84 */ + u32 fltpol; /* 0x88 */ + u32 synconf; /* 0x8C */ + u32 invctrl; /* 0x90 */ + u32 swoctrl; /* 0x94 */ + u32 pwmload; /* 0x98 */ +}; + +struct pit2_regs { + u32 ldval; /* 0x00 */ + u32 cval; /* 0x04 */ + u32 tctrl; /* 0x08 */ + u32 tflg; /* 0x0C */ +}; + +struct pit_regs { + u32 mcr; /* 0x00 */ + u32 rsvd0[55]; + u32 ltmr64h; /* 0xE0 */ + u32 ltmr64l; /* 0xE4 */ + u32 rsvd1[6]; + struct pit2_regs counter[8]; /* 0x100 */ +}; + +struct lptmr_regs { + u32 csr; /* 0x00 */ + u32 psr; /* 0x04 */ + u32 cmr; /* 0x08 */ + u32 cnr; /* 0x0C */ +}; + +/* Flex Timer */ +#define FTM_SC (FTM_BASE_ADDR + 0x00) +#define FTM_CNT (FTM_BASE_ADDR + 0x04) +#define FTM_MOD (FTM_BASE_ADDR + 0x08) +#define FTM_C0SC (FTM_BASE_ADDR + 0x0C) +#define FTM_C0V (FTM_BASE_ADDR + 0x10) +#define FTM_C1SC (FTM_BASE_ADDR + 0x14) +#define FTM_C1V (FTM_BASE_ADDR + 0x18) +#define FTM_C2SC (FTM_BASE_ADDR + 0x1C) +#define FTM_C2V (FTM_BASE_ADDR + 0x20) +#define FTM_C3SC (FTM_BASE_ADDR + 0x24) +#define FTM_C3V (FTM_BASE_ADDR + 0x28) +#define FTM_C4SC (FTM_BASE_ADDR + 0x2C) +#define FTM_C4V (FTM_BASE_ADDR + 0x30) +#define FTM_C5SC (FTM_BASE_ADDR + 0x34) +#define FTM_C5V (FTM_BASE_ADDR + 0x38) +#define FTM_C6SC (FTM_BASE_ADDR + 0x3C) +#define FTM_C6V (FTM_BASE_ADDR + 0x40) +#define FTM_C7SC (FTM_BASE_ADDR + 0x44) +#define FTM_C7V (FTM_BASE_ADDR + 0x48) +#define FTM_CNTIN (FTM_BASE_ADDR + 0x4C) +#define FTM_STATUS (FTM_BASE_ADDR + 0x50) +#define FTM_MODE (FTM_BASE_ADDR + 0x54) +#define FTM_SYNC (FTM_BASE_ADDR + 0x58) +#define FTM_OUTINIT (FTM_BASE_ADDR + 0x5C) +#define FTM_OUTMASK (FTM_BASE_ADDR + 0x60) +#define FTM_COMBINE (FTM_BASE_ADDR + 0x64) +#define FTM_DEADTIME (FTM_BASE_ADDR + 0x68) +#define FTM_EXTTRIG (FTM_BASE_ADDR + 0x6C) +#define FTM_POL (FTM_BASE_ADDR + 0x70) +#define FTM_FMS (FTM_BASE_ADDR + 0x74) +#define FTM_FILTER (FTM_BASE_ADDR + 0x78) +#define FTM_FLTCTRL (FTM_BASE_ADDR + 0x7C) +#define FTM_QDCTRL (FTM_BASE_ADDR + 0x80) +#define FTM_CONF (FTM_BASE_ADDR + 0x84) +#define FTM_FLTPOL (FTM_BASE_ADDR + 0x88) +#define FTM_SYNCONF (FTM_BASE_ADDR + 0x8C) +#define FTM_INVCTRL (FTM_BASE_ADDR + 0x90) +#define FTM_SWOCTRL (FTM_BASE_ADDR + 0x94) +#define FTM_PWMLOAD (FTM_BASE_ADDR + 0x98) + +#define FTM_SC_TOF (1 << 7) +#define FTM_SC_TOIE (1 << 6) +#define FTM_SC_CPWMS (1 << 5) +#define FTM_SC_CLKS(x) ((x & 3) << 3) +#define FTM_SC_PS(x) ((x & 7) << 0) + +#define FTM_CNT_COUNT(x) (x & 0xFFFF) + +#define FTM_MOD_MOD(x) (x & 0xFFFF) + +#define FTM_CnSC_CHF (1 << 7) +#define FTM_CnSC_CHIE (1 << 6) +#define FTM_CnSC_MSB (1 << 5) +#define FTM_CnSC_MSA (1 << 4) +#define FTM_CnSC_ELSB (1 << 3) +#define FTM_CnSC_ELSA (1 << 2) +#define FTM_CnSC_DMA (1 << 0) + +#define FTM_CnV_VAL(x) (x & 0xFFFF) + +#define FTM_CNTIN_INIT(x) (x & 0xFFFF) + +#define FTM_STATUS_CH7F (1 << 7) +#define FTM_STATUS_CH6F (1 << 6) +#define FTM_STATUS_CH5F (1 << 5) +#define FTM_STATUS_CH4F (1 << 4) +#define FTM_STATUS_CH3F (1 << 3) +#define FTM_STATUS_CH2F (1 << 2) +#define FTM_STATUS_CH1F (1 << 1) +#define FTM_STATUS_CH0F (1 << 0) + +#define FTM_MODE_FAULTIE (1 << 7) +#define FTM_MODE_FAULTM(x) ((x & 3) << 5) +#define FTM_MODE_CAPTEST (1 << 4) +#define FTM_MODE_PWMSYNC (1 << 3) +#define FTM_MODE_WPDIS (1 << 2) +#define FTM_MODE_INIT (1 << 1) +#define FTM_MODE_FTMEN (1 << 0) + +#define FTM_SYNC_SWSYNC (1 << 7) +#define FTM_SYNC_TRIG2 (1 << 6) +#define FTM_SYNC_TRIG1 (1 << 5) +#define FTM_SYNC_TRIG0 (1 << 4) +#define FTM_SYNC_SYNCHOM (1 << 3) +#define FTM_SYNC_REINIT (1 << 2) +#define FTM_SYNC_CNTMAX (1 << 1) +#define FTM_SYNC_CNTMIN (1 << 0) + +#define FTM_OUTINIT_CH7OI (1 << 7) +#define FTM_OUTINIT_CH6OI (1 << 6) +#define FTM_OUTINIT_CH5OI (1 << 5) +#define FTM_OUTINIT_CH4OI (1 << 4) +#define FTM_OUTINIT_CH3OI (1 << 3) +#define FTM_OUTINIT_CH2OI (1 << 2) +#define FTM_OUTINIT_CH1OI (1 << 1) +#define FTM_OUTINIT_CH0OI (1 << 0) + +#define FTM_OUTMASK_CH7OM (1 << 7) +#define FTM_OUTMASK_CH6OM (1 << 6) +#define FTM_OUTMASK_CH5OM (1 << 5) +#define FTM_OUTMASK_CH4OM (1 << 4) +#define FTM_OUTMASK_CH3OM (1 << 3) +#define FTM_OUTMASK_CH2OM (1 << 2) +#define FTM_OUTMASK_CH1OM (1 << 1) +#define FTM_OUTMASK_CH0OM (1 << 0) + +#define FTM_COMBINE_FAULTEN3 (1 << 30) +#define FTM_COMBINE_SYNCEN3 (1 << 29) +#define FTM_COMBINE_DTEN3 (1 << 28) +#define FTM_COMBINE_DECAP3 (1 << 27) +#define FTM_COMBINE_DECAPEN3 (1 << 26) +#define FTM_COMBINE_COMP3 (1 << 25) +#define FTM_COMBINE_COMBINE3 (1 << 24) +#define FTM_COMBINE_FAULTEN2 (1 << 22) +#define FTM_COMBINE_SYNCEN2 (1 << 21) +#define FTM_COMBINE_DTEN2 (1 << 20) +#define FTM_COMBINE_DECAP2 (1 << 19) +#define FTM_COMBINE_DECAPEN2 (1 << 18) +#define FTM_COMBINE_COMP2 (1 << 17) +#define FTM_COMBINE_COMBINE2 (1 << 16) +#define FTM_COMBINE_FAULTEN1 (1 << 14) +#define FTM_COMBINE_SYNCEN1 (1 << 13) +#define FTM_COMBINE_DTEN1 (1 << 12) +#define FTM_COMBINE_DECAP1 (1 << 11) +#define FTM_COMBINE_DECAPEN1 (1 << 10) +#define FTM_COMBINE_COMP1 (1 << 9) +#define FTM_COMBINE_COMBINE1 (1 << 8) +#define FTM_COMBINE_FAULTEN0 (1 << 6) +#define FTM_COMBINE_SYNCEN0 (1 << 5) +#define FTM_COMBINE_DTEN0 (1 << 4) +#define FTM_COMBINE_DECAP0 (1 << 3) +#define FTM_COMBINE_DECAPEN0 (1 << 2) +#define FTM_COMBINE_COMP0 (1 << 1) +#define FTM_COMBINE_COMBINE0 (1 << 0) + +#define FTM_DEADTIME_DTPS(x) ((x & 3) << 6) +#define FTM_DEADTIME_DTVAL(x) ((x & 0x3F) << 0) + +#define FTM_EXTTRIG_TRIGF (1 << 7) +#define FTM_EXTTRIG_INITTRIGEN (1 << 6) +#define FTM_EXTTRIG_CH1TRIG (1 << 5) +#define FTM_EXTTRIG_CH0TRIG (1 << 4) +#define FTM_EXTTRIG_CH5TRIG (1 << 3) +#define FTM_EXTTRIG_CH4TRIG (1 << 2) +#define FTM_EXTTRIG_CH3TRIG (1 << 1) +#define FTM_EXTTRIG_CH2TRIG (1 << 0) + +#define FTM_POL_POL7 (1 << 7) +#define FTM_POL_POL6 (1 << 6) +#define FTM_POL_POL5 (1 << 5) +#define FTM_POL_POL4 (1 << 4) +#define FTM_POL_POL3 (1 << 3) +#define FTM_POL_POL2 (1 << 2) +#define FTM_POL_POL1 (1 << 1) +#define FTM_POL_POL0 (1 << 0) + +#define FTM_FMS_FAULTF (1 << 7) +#define FTM_FMS_WPEN (1 << 6) +#define FTM_FMS_FAULTIN (1 << 5) +#define FTM_FMS_FAULTF3 (1 << 3) +#define FTM_FMS_FAULTF2 (1 << 2) +#define FTM_FMS_FAULTF1 (1 << 1) +#define FTM_FMS_FAULTF0 (1 << 0) + +#define FTM_FILTER_CH3FVAL(x) ((x & 0xF) << 12) +#define FTM_FILTER_CH2FVAL(x) ((x & 0xF) << 8) +#define FTM_FILTER_CH1FVAL(x) ((x & 0xF) << 4) +#define FTM_FILTER_CH0FVAL(x) ((x & 0xF) << 0) + +#define FTM_FLTCTRL_FFVAL(x) ((x & 0xF) << 8) +#define FTM_FLTCTRL_FFLTR3EN (1 << 7) +#define FTM_FLTCTRL_FFLTR2EN (1 << 6) +#define FTM_FLTCTRL_FFLTR1EN (1 << 5) +#define FTM_FLTCTRL_FFLTR0EN (1 << 4) +#define FTM_FLTCTRL_FAULT3EN (1 << 3) +#define FTM_FLTCTRL_FAULT2EN (1 << 2) +#define FTM_FLTCTRL_FAULT1EN (1 << 1) +#define FTM_FLTCTRL_FAULT0EN (1 << 0) + +#define FTM_QDCTRL_PHAFLTREN (1 << 7) +#define FTM_QDCTRL_PHBFLTREN (1 << 6) +#define FTM_QDCTRL_PHAPOL (1 << 5) +#define FTM_QDCTRL_PHBPOL (1 << 4) +#define FTM_QDCTRL_QUADMODE (1 << 3) +#define FTM_QDCTRL_QUADIR (1 << 2) +#define FTM_QDCTRL_TOFDIR (1 << 1) +#define FTM_QDCTRL_QUADEN (1 << 0) + +#define FTM_CONF_GTBEOUT (1 << 10) +#define FTM_CONF_GTBEEN (1 << 9) +#define FTM_CONF_BDMMODE(x) ((x & 3) << 6) +#define FTM_CONF_NUMTOF(x) ((x & 0x1F) << 0) + +#define FTM_FLTPOL_FLT3POL (1 << 3) +#define FTM_FLTPOL_FLT2POL (1 << 2) +#define FTM_FLTPOL_FLT1POL (1 << 1) +#define FTM_FLTPOL_FLT0POL (1 << 0) + +#define FTM_SYNCONF_HWSOC (1 << 20) +#define FTM_SYNCONF_HWINVC (1 << 19) +#define FTM_SYNCONF_HWOM (1 << 18) +#define FTM_SYNCONF_HWWRBUF (1 << 17) +#define FTM_SYNCONF_HWRSTCNT (1 << 16) +#define FTM_SYNCONF_SWSOC (1 << 12) +#define FTM_SYNCONF_SWINVC (1 << 11) +#define FTM_SYNCONF_SWOM (1 << 10) +#define FTM_SYNCONF_SWWRBUF (1 << 9) +#define FTM_SYNCONF_SWRSTCNT (1 << 8) +#define FTM_SYNCONF_SYNCMODE (1 << 7) +#define FTM_SYNCONF_SWOC (1 << 5) +#define FTM_SYNCONF_INVC (1 << 4) +#define FTM_SYNCONF_CNTINC (1 << 2) +#define FTM_SYNCONF_HWTRIGMODE (1 << 0) + +#define FTM_INVCTRL_INV3EN (1 << 3) +#define FTM_INVCTRL_INV2EN (1 << 2) +#define FTM_INVCTRL_INV1EN (1 << 1) +#define FTM_INVCTRL_INV0EN (1 << 0) + +#define FTM_SWOCTRL_CH7OCV (1 << 15) +#define FTM_SWOCTRL_CH6OCV (1 << 14) +#define FTM_SWOCTRL_CH5OCV (1 << 13) +#define FTM_SWOCTRL_CH4OCV (1 << 12) +#define FTM_SWOCTRL_CH3OCV (1 << 11) +#define FTM_SWOCTRL_CH2OCV (1 << 10) +#define FTM_SWOCTRL_CH1OCV (1 << 9) +#define FTM_SWOCTRL_CH0OCV (1 << 8) +#define FTM_SWOCTRL_CH7OC (1 << 7) +#define FTM_SWOCTRL_CH6OC (1 << 6) +#define FTM_SWOCTRL_CH5OC (1 << 5) +#define FTM_SWOCTRL_CH4OC (1 << 4) +#define FTM_SWOCTRL_CH3OC (1 << 3) +#define FTM_SWOCTRL_CH2OC (1 << 2) +#define FTM_SWOCTRL_CH1OC (1 << 1) +#define FTM_SWOCTRL_CH0OC (1 << 0) + +#define FTM_PWMLOAD_LDOK (1 << 9) +#define FTM_PWMLOAD_CH7SEL (1 << 7) +#define FTM_PWMLOAD_CH6SEL (1 << 6) +#define FTM_PWMLOAD_CH5SEL (1 << 5) +#define FTM_PWMLOAD_CH4SEL (1 << 4) +#define FTM_PWMLOAD_CH3SEL (1 << 3) +#define FTM_PWMLOAD_CH2SEL (1 << 2) +#define FTM_PWMLOAD_CH1SEL (1 << 1) +#define FTM_PWMLOAD_CH0SEL (1 << 0) + +/* Periodic Interrupt Timer */ +#define PIT_MCR (PIT_BASE_ADDR + 0x00) +#define PIT_LTMR64H (PIT_BASE_ADDR + 0xE0) +#define PIT_LTMR64L (PIT_BASE_ADDR + 0xE4) +#define PIT_LDVAL0 (PIT_BASE_ADDR + 0x100) +#define PIT_CVAL0 (PIT_BASE_ADDR + 0x104) +#define PIT_TCTRL0 (PIT_BASE_ADDR + 0x108) +#define PIT_TFLG0 (PIT_BASE_ADDR + 0x10C) +#define PIT_LDVAL1 (PIT_BASE_ADDR + 0x110) +#define PIT_CVAL1 (PIT_BASE_ADDR + 0x114) +#define PIT_TCTRL1 (PIT_BASE_ADDR + 0x118) +#define PIT_TFLG1 (PIT_BASE_ADDR + 0x11C) +#define PIT_LDVAL2 (PIT_BASE_ADDR + 0x120) +#define PIT_CVAL2 (PIT_BASE_ADDR + 0x124) +#define PIT_TCTRL2 (PIT_BASE_ADDR + 0x128) +#define PIT_TFLG2 (PIT_BASE_ADDR + 0x12C) +#define PIT_LDVAL3 (PIT_BASE_ADDR + 0x130) +#define PIT_CVAL3 (PIT_BASE_ADDR + 0x134) +#define PIT_TCTRL3 (PIT_BASE_ADDR + 0x138) +#define PIT_TFLG3 (PIT_BASE_ADDR + 0x13C) +#define PIT_LDVAL4 (PIT_BASE_ADDR + 0x140) +#define PIT_CVAL4 (PIT_BASE_ADDR + 0x144) +#define PIT_TCTRL4 (PIT_BASE_ADDR + 0x148) +#define PIT_TFLG4 (PIT_BASE_ADDR + 0x14C) +#define PIT_LDVAL5 (PIT_BASE_ADDR + 0x150) +#define PIT_CVAL5 (PIT_BASE_ADDR + 0x154) +#define PIT_TCTRL5 (PIT_BASE_ADDR + 0x158) +#define PIT_TFLG5 (PIT_BASE_ADDR + 0x15C) +#define PIT_LDVAL6 (PIT_BASE_ADDR + 0x160) +#define PIT_CVAL6 (PIT_BASE_ADDR + 0x164) +#define PIT_TCTRL6 (PIT_BASE_ADDR + 0x168) +#define PIT_TFLG6 (PIT_BASE_ADDR + 0x16C) +#define PIT_LDVAL7 (PIT_BASE_ADDR + 0x170) +#define PIT_CVAL7 (PIT_BASE_ADDR + 0x174) +#define PIT_TCTRL7 (PIT_BASE_ADDR + 0x178) +#define PIT_TFLG7 (PIT_BASE_ADDR + 0x17C) + +#define PIT_MCR_MDIS (1 << 1) +#define PIT_MCR_FRZ (1 << 0) + +#define PIT_TCTRL_CHN (1 << 2) +#define PIT_TCTRL_TIE (1 << 1) +#define PIT_TCTRL_TEN (1 << 0) + +#define PIT_TFLG_TIF (1 << 0) + +/* Low Power Timer */ +#define LPTMR_CSR (LPTMR_BASE_ADDR + 0x00) +#define LPTMR_PSR (LPTMR_BASE_ADDR + 0x04) +#define LPTMR_CMR (LPTMR_BASE_ADDR + 0x08) +#define LPTMR_CNR (LPTMR_BASE_ADDR + 0x0C) + +#define LPTMR_CSR_TCF (1 << 7) +#define LPTMR_CSR_TIE (1 << 6) +#define LPTMR_CSR_TPS(x) ((x & 3) << 4) +#define LPTMR_CSR_TPP (1 << 3) +#define LPTMR_CSR_TFC (1 << 2) +#define LPTMR_CSR_TMS (1 << 1) +#define LPTMR_CSR_TEN (1 << 0) + +#define LPTMR_PSR_PRESCALE(x) ((x & 0x0F) << 3) +#define LPTMR_PSR_PBYP (1 << 2) +#define LPTMR_PSR_PCS(x) ((x & 0x03) << 0) + +#define LPTMR_CMR_COMPARE(x) (x & 0xFFFF) +#define LPTMR_CNR_COUNTER(x) (x & 0xFFFF) + +#endif /* __ASM_ARCH_TIMER_H */ diff --git a/arch/arm/include/asm/arch-vybrid/vybrid-pins.h b/arch/arm/include/asm/arch-vybrid/vybrid-pins.h new file mode 100644 index 0000000000..b29f83c919 --- /dev/null +++ b/arch/arm/include/asm/arch-vybrid/vybrid-pins.h @@ -0,0 +1,88 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_VYBRID_PINS_H__ +#define __ASM_ARCH_VYBRID_PINS_H__ + +#ifndef __ASSEMBLY__ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 +/*! + * Starting bit position within each entry of \b iomux_pins to represent which + * mux mode is for GPIO (0-based) + */ +#define GPIO_I 21 + +#define MUX_IO_P 29 +#define MUX_IO_I 24 +#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \ + GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\ + ((1 << (MUX_IO_P - MUX_IO_I)) - 1))) +#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin)) +#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN) +#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN) + +#define NON_GPIO_PORT 0x7 +#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1) +#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1) + +#define NON_MUX_I PIN_TO_MUX_MASK +#define NON_PAD_I PIN_TO_PAD_MASK + +#define MUX_I_START 0x001C +#define PAD_I_START 0x3F0 +#define INPUT_CTL_START 0x8C4 +#define MUX_I_END (PAD_I_START - 4) + +#define _VYBRID_BUILD_PIN(gp, gi, ga, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | \ + ((pi - PAD_I_START) << PAD_I) | \ + ((ga) << GPIO_I)) + +#define _VYBRID_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \ + _VYBRID_BUILD_PIN(gp, gi, ga, mi, pi) + +#define _VYBRID_BUILD_NON_GPIO_PIN(mi, pi) \ + _VYBRID_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi) + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) +#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK) +#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2) + +typedef enum iomux_input_select { + AUDMUX_P4_INPUT = 0, +} iomux_input_select_t; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_VYBRID_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-vybrid/vybrid-regs.h b/arch/arm/include/asm/arch-vybrid/vybrid-regs.h new file mode 100644 index 0000000000..d1647f0c18 --- /dev/null +++ b/arch/arm/include/asm/arch-vybrid/vybrid-regs.h @@ -0,0 +1,697 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_VYBRID_REGS_H__ +#define __ASM_ARCH_VYBRID_REGS_H__ + +#define IRAM_BASE_ADDR 0x3F000000 /* internal ram */ +#define AIPS0_BASE_ADDR 0x40000000 +#define AIPS1_BASE_ADDR 0x40080000 +#define CSD0_BASE_ADDR 0x80000000 /* ddr 0 */ +#define CSD1_BASE_ADDR 0xa0000000 /* ddr 1 */ + +#define IRAM_SIZE 0x00040000 /* 256 KB */ + +/* AIPS 0 */ +#define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000) +#define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000) +#define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000) +#define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000) +#define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000) +#define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000) +#define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000) +#define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000) +#define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000) +#define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000) +#define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000) +#define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000) +#define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000) +#define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000) +#define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000) +#define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000) +#define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000) +#define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000) +#define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000) +#define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000) +#define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000) +#define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000) +#define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000) +#define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000) +#define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000) +#define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000) +#define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000) +#define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000) +#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000) +#define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000) +#define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000) +#define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000) +#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000) +#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000) +#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000) +#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000) +#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000) +#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000) +#define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000) +#define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000) +#define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000) +#define WDOG_A5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000) +#define WDOG_M4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000) +#define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000) +#define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000) +#define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000) +#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000) +#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) +#define ANATOP_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000) +#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) +#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000) +#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000) +#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000) +#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000) +#define EWDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000) +#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000) +#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000) +#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000) +#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000) +#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000) +#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000) +#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000) + +/* AIPS 1 */ +#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000) +#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) +#define ESDHC2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) +#define QSPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000) +#define MACNET0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) +#define MACNET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000) + +/* WEIM CSnGCR1 */ +#define CSEN 1 +#define SWR (1 << 1) +#define SRD (1 << 2) +#define MUM (1 << 3) +#define WFL (1 << 4) +#define RFL (1 << 5) +#define CRE (1 << 6) +#define CREP (1 << 7) +#define BL(x) (((x) & 0x7) << 8) +#define WC (1 << 11) +#define BCD(x) (((x) & 0x3) << 12) +#define BCS(x) (((x) & 0x3) << 14) +#define DSZ(x) (((x) & 0x7) << 16) +#define SP (1 << 19) +#define CSREC(x) (((x) & 0x7) << 20) +#define AUS (1 << 23) +#define GBC(x) (((x) & 0x7) << 24) +#define WP (1 << 27) +#define PSZ(x) (((x) & 0x0f << 28) + +/* WEIM CSnGCR2 */ +#define ADH(x) (((x) & 0x3)) +#define DAPS(x) (((x) & 0x0f << 4) +#define DAE (1 << 8) +#define DAP (1 << 9) +#define MUX16_BYP (1 << 12) + +/* WEIM CSnRCR1 */ +#define RCSN(x) (((x) & 0x7)) +#define RCSA(x) (((x) & 0x7) << 4) +#define OEN(x) (((x) & 0x7) << 8) +#define OEA(x) (((x) & 0x7) << 12) +#define RADVN(x) (((x) & 0x7) << 16) +#define RAL (1 << 19) +#define RADVA(x) (((x) & 0x7) << 20) +#define RWSC(x) (((x) & 0x3f) << 24) + +/* WEIM CSnRCR2 */ +#define RBEN(x) (((x) & 0x7)) +#define RBE (1 << 3) +#define RBEA(x) (((x) & 0x7) << 4) +#define RL(x) (((x) & 0x3) << 8) +#define PAT(x) (((x) & 0x7) << 12) +#define APR (1 << 15) + +/* WEIM CSnWCR1 */ +#define WCSN(x) (((x) & 0x7)) +#define WCSA(x) (((x) & 0x7) << 3) +#define WEN(x) (((x) & 0x7) << 6) +#define WEA(x) (((x) & 0x7) << 9) +#define WBEN(x) (((x) & 0x7) << 12) +#define WBEA(x) (((x) & 0x7) << 15) +#define WADVN(x) (((x) & 0x7) << 18) +#define WADVA(x) (((x) & 0x7) << 21) +#define WWSC(x) (((x) & 0x3f) << 24) +#define WBED1 (1 << 30) +#define WAL (1 << 31) + +/* WEIM CSnWCR2 */ +#define WBED 1 + +/* WEIM WCR */ +#define BCM 1 +#define GBCD(x) (((x) & 0x3) << 1) +#define INTEN (1 << 4) +#define INTPOL (1 << 5) +#define WDOG_EN (1 << 8) +#define WDOG_LIMIT(x) (((x) & 0x3) << 9) + +/* Number of GPIO pins per port */ +#define GPIO_NUM_PIN 32 + +#define IIM_SREV 0x24 +#define ROM_SI_REV 0x80 + +#define NFC_BUF_SIZE 0x1000 + +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_1 0x11 +#define CHIP_REV_2_0 0x20 +#define CHIP_REV_2_5 0x25 +#define CHIP_REV_3_0 0x30 + +#define BOARD_REV_1_0 0x0 +#define BOARD_REV_2_0 0x1 + +/*#define IMX_IIM_BASE (IIM_BASE_ADDR)*/ + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) + +struct clkctl { + u32 ccr; /* 0x00 */ + u32 csr; /* 0x04 */ + u32 ccsr; /* 0x08 */ + u32 cacrr; /* 0x0C */ + u32 cscmr1; /* 0x10 */ + u32 cscdr1; /* 0x14 */ + u32 cscdr2; /* 0x18 */ + u32 cscdr3; /* 0x1C */ + u32 cscmr2; /* 0x20 */ + u32 cscdr4; /* 0x24 */ + u32 ctor; /* 0x28 */ + u32 clpcr; /* 0x2C */ + u32 cisr; /* 0x30 */ + u32 cimr; /* 0x34 */ + u32 ccosr; /* 0x38 */ + u32 cgpr; /* 0x3C */ + u32 ccgr0; /* 0x40 */ + u32 ccgr1; /* 0x44 */ + u32 ccgr2; /* 0x48 */ + u32 ccgr3; /* 0x4C */ + u32 ccgr4; /* 0x50 */ + u32 ccgr5; /* 0x54 */ + u32 ccgr6; /* 0x58 */ + u32 ccgr7; /* 0x5C */ + u32 ccgr8; /* 0x60 */ + u32 ccgr9; /* 0x64 */ + u32 ccgr10; /* 0x68 */ + u32 ccgr11; /* 0x6C */ + u32 cmeor0; /* 0x70 */ + u32 cmeor1; /* 0x74 */ + u32 cmeor2; /* 0x78 */ + u32 cmeor3; /* 0x7C */ + u32 cmeor4; /* 0x80 */ + u32 cmeor5; /* 0x84 */ + u32 cppdsr; /* 0x88 */ + u32 ccowr; /* 0x8C */ + u32 ccpgr0; /* 0x90 */ + u32 ccpgr1; /* 0x94 */ + u32 ccpgr2; /* 0x98 */ + u32 ccpgr3; /* 0x9C */ +}; + +/* WEIM registers */ +struct weim { + u32 cs0gcr1; + u32 cs0gcr2; + u32 cs0rcr1; + u32 cs0rcr2; + u32 cs0wcr1; + u32 cs0wcr2; + u32 cs1gcr1; + u32 cs1gcr2; + u32 cs1rcr1; + u32 cs1rcr2; + u32 cs1wcr1; + u32 cs1wcr2; + u32 cs2gcr1; + u32 cs2gcr2; + u32 cs2rcr1; + u32 cs2rcr2; + u32 cs2wcr1; + u32 cs2wcr2; + u32 cs3gcr1; + u32 cs3gcr2; + u32 cs3rcr1; + u32 cs3rcr2; + u32 cs3wcr1; + u32 cs3wcr2; + u32 cs4gcr1; + u32 cs4gcr2; + u32 cs4rcr1; + u32 cs4rcr2; + u32 cs4wcr1; + u32 cs4wcr2; + u32 cs5gcr1; + u32 cs5gcr2; + u32 cs5rcr1; + u32 cs5rcr2; + u32 cs5wcr1; + u32 cs5wcr2; + u32 wcr; + u32 wiar; + u32 ear; +}; + +struct anadig { + u32 usb1_pll_ctrl; + u32 usb2_pll_ctrl; + u32 pll_528_ctrl; + u32 pll_528_ss; + u32 pll_528_num; + u32 pll_528_denom; + u32 pll_aud_ctrl; + u32 pll_aud_num; + u32 pll_aud_denom; + u32 pll_vid_ctrl; + u32 pll_vid_num; + u32 pll_vid_denom; + u32 pll_enet_ctrl; + u32 pll_pfd_480_usb1; + u32 pll_pfd_528; + u32 reg_1p1; + u32 reg_3p0; + u32 reg_2p5; + u32 ana_misc0; + u32 ana_misc1; + u32 tempsens0; + u32 usb1_vbus_det; + u32 usb1_vbus_chrg_det; + u32 usb1_vbus_detsta; + u32 usb1_chrg_detsta; + u32 usb1_loopback; + u32 usb1_misc; + u32 usb2_vbus_det; + u32 usb2_vbus_chrg_det; + u32 usb2_vbus_detsta; + u32 usb2_chrg_detsta; + u32 usb2_loopback; + u32 usb2_misc; + u32 digprog; + u32 pll_sys_ctrl; + u32 pll_sys_ss; + u32 pll_sys_num; + u32 pll_sys_denom; + u32 pfd_528_sys; + u32 pll_lock; +}; + +struct iomuxc { + u32 gpr0; + u32 gpr1; + u32 omux0; + u32 omux1; + u32 omux2; + u32 omux3; + u32 omux4; +}; + +/* System Reset Controller (SRC) */ +struct src { + u32 scr; /* 0x00 */ + u32 sbmr1; /* 0x04 */ + u32 srsr; /* 0x08 */ + u32 secr; /* 0x0C */ + u32 gpsr; /* 0x10 */ + u32 sicr; /* 0x14 */ + u32 simr; /* 0x18 */ + u32 sbmr2; /* 0x1C */ + u32 gpr0; /* 0x20 */ + u32 gpr1; /* 0x24 */ + u32 gpr2; /* 0x28 */ + u32 gpr3; /* 0x2C */ + u32 gpr4; /* 0x30 */ + u32 hab0; /* 0x34 */ + u32 hab1; /* 0x38 */ + u32 hab2; /* 0x3C */ + u32 hab3; /* 0x40 */ + u32 hab4; /* 0x44 */ + u32 hab5; /* 0x48 */ + u32 misc0; /* 0x4C */ + u32 misc1; /* 0x50 */ + u32 misc2; /* 0x54 */ + u32 misc3; /* 0x58 */ +}; + +struct fuse_bank1_regs { + u32 fuse0_8[9]; + u32 mac_addr[6]; + u32 fuse15_31[0x11]; +}; + +#define ANADIG_USB1_PLL_CTRL (0x10) +#define ANADIG_USB2_PLL_CTRL (0x20) +#define ANADIG_PLL_528_CTRL (0x30) +#define ANADIG_PLL_528_SS (0x40) +#define ANADIG_PLL_528_NUM (0x50) +#define ANADIG_PLL_528_DENOM (0x60) +#define ANADIG_PLL_AUD_CTRL (0x70) +#define ANADIG_PLL_AUD_NUM (0x80) +#define ANADIG_PLL_AUD_DENOM (0x90) +#define ANADIG_PLL_VID_CTRL (0xA0) +#define ANADIG_PLL_VID_NUM (0xB0) +#define ANADIG_PLL_VID_DENOM (0xC0) +#define ANADIG_PLL_ENET_CTRL (0xE0) +#define ANADIG_PLL_PFD_480_USB1 (0xF0) +#define ANADIG_PLL_PFD_528 (0x100) +#define ANADIG_REG_1P1 (0x110) +#define ANADIG_REG_3P0 (0x120) +#define ANADIG_REG_2P5 (0x130) +#define ANADIG_ANA_MISC0 (0x150) +#define ANADIG_ANA_MISC1 (0x160) +#define ANADIG_TEMPSENS0 (0x180) +#define ANADIG_USB1_VBUS_DET (0x1A0) +#define ANADIG_USB1_CHRG_DET (0x1B0) +#define ANADIG_USB1_VBUS_DETSTA (0x1C0) +#define ANADIG_UAB1_CHRG_DETSTA (0x1D0) +#define ANADIG_USB1_LOOPBACK (0x1E0) +#define ANADIG_USB1_MISC (0x1F0) +#define ANADIG_USB2_VBUS_DET (0x200) +#define ANADIG_USB2_CHRG_DET (0x210) +#define ANADIG_USB2_VBUS_DETSTA (0x220) +#define ANADIG_USB2_CHRG_DETSTA (0x230) +#define ANADIG_USB2_LOOPBACK (0x240) +#define ANADIG_USB2_MISC (0x250) +#define ANADIG_DIGPROG (0x260) +#define ANADIG_PLL_SYS_CTRL (0x270) +#define ANADIG_PLL_SYS_SS (0x280) +#define ANADIG_PLL_SYS_NUM (0x290) +#define ANADIG_PLL_SYS_DENOM (0x2A0) +#define ANADIG_PFD_528_SYS (0x2B0) +#define ANADIG_PLL_LOCK (0x2C0) + +#define DDR_CR_BASE DDR_BASE_ADDR +#define DDR_PHY_BASE (DDR_BASE_ADDR + 0x400) + +#define DDR_CR000 (DDR_CR_BASE + 0x000) +#define DDR_CR001 (DDR_CR_BASE + 0x004) +#define DDR_CR002 (DDR_CR_BASE + 0x008) +#define DDR_CR003 (DDR_CR_BASE + 0x00C) +#define DDR_CR004 (DDR_CR_BASE + 0x010) +#define DDR_CR005 (DDR_CR_BASE + 0x014) +#define DDR_CR006 (DDR_CR_BASE + 0x018) +#define DDR_CR007 (DDR_CR_BASE + 0x01C) +#define DDR_CR008 (DDR_CR_BASE + 0x020) +#define DDR_CR009 (DDR_CR_BASE + 0x024) + +#define DDR_CR010 (DDR_CR_BASE + 0x028) +#define DDR_CR011 (DDR_CR_BASE + 0x02C) +#define DDR_CR012 (DDR_CR_BASE + 0x030) +#define DDR_CR013 (DDR_CR_BASE + 0x034) +#define DDR_CR014 (DDR_CR_BASE + 0x038) +#define DDR_CR015 (DDR_CR_BASE + 0x03C) +#define DDR_CR016 (DDR_CR_BASE + 0x040) +#define DDR_CR017 (DDR_CR_BASE + 0x044) +#define DDR_CR018 (DDR_CR_BASE + 0x048) +#define DDR_CR019 (DDR_CR_BASE + 0x04C) + +#define DDR_CR020 (DDR_CR_BASE + 0x050) +#define DDR_CR021 (DDR_CR_BASE + 0x054) +#define DDR_CR022 (DDR_CR_BASE + 0x058) +#define DDR_CR023 (DDR_CR_BASE + 0x05C) +#define DDR_CR024 (DDR_CR_BASE + 0x060) +#define DDR_CR025 (DDR_CR_BASE + 0x064) +#define DDR_CR026 (DDR_CR_BASE + 0x068) +#define DDR_CR027 (DDR_CR_BASE + 0x06C) +#define DDR_CR028 (DDR_CR_BASE + 0x070) +#define DDR_CR029 (DDR_CR_BASE + 0x074) + +#define DDR_CR030 (DDR_CR_BASE + 0x078) +#define DDR_CR031 (DDR_CR_BASE + 0x07C) +#define DDR_CR032 (DDR_CR_BASE + 0x080) +#define DDR_CR033 (DDR_CR_BASE + 0x084) +#define DDR_CR034 (DDR_CR_BASE + 0x088) +#define DDR_CR035 (DDR_CR_BASE + 0x08C) +#define DDR_CR036 (DDR_CR_BASE + 0x090) +#define DDR_CR037 (DDR_CR_BASE + 0x094) +#define DDR_CR038 (DDR_CR_BASE + 0x098) +#define DDR_CR039 (DDR_CR_BASE + 0x09C) + +#define DDR_CR040 (DDR_CR_BASE + 0x0A0) +#define DDR_CR041 (DDR_CR_BASE + 0x0A4) +#define DDR_CR042 (DDR_CR_BASE + 0x0A8) +#define DDR_CR043 (DDR_CR_BASE + 0x0AC) +#define DDR_CR044 (DDR_CR_BASE + 0x0B0) +#define DDR_CR045 (DDR_CR_BASE + 0x0B4) +#define DDR_CR046 (DDR_CR_BASE + 0x0B8) +#define DDR_CR047 (DDR_CR_BASE + 0x0BC) +#define DDR_CR048 (DDR_CR_BASE + 0x0C0) +#define DDR_CR049 (DDR_CR_BASE + 0x0C4) + +#define DDR_CR050 (DDR_CR_BASE + 0x0C8) +#define DDR_CR051 (DDR_CR_BASE + 0x0CC) +#define DDR_CR052 (DDR_CR_BASE + 0x0D0) +#define DDR_CR053 (DDR_CR_BASE + 0x0D4) +#define DDR_CR054 (DDR_CR_BASE + 0x0D8) +#define DDR_CR055 (DDR_CR_BASE + 0x0DC) +#define DDR_CR056 (DDR_CR_BASE + 0x0E0) +#define DDR_CR057 (DDR_CR_BASE + 0x0E4) +#define DDR_CR058 (DDR_CR_BASE + 0x0E8) +#define DDR_CR059 (DDR_CR_BASE + 0x0EC) + +#define DDR_CR060 (DDR_CR_BASE + 0x0F0) +#define DDR_CR061 (DDR_CR_BASE + 0x0F4) +#define DDR_CR062 (DDR_CR_BASE + 0x0F8) +#define DDR_CR063 (DDR_CR_BASE + 0x0FC) +#define DDR_CR064 (DDR_CR_BASE + 0x100) +#define DDR_CR065 (DDR_CR_BASE + 0x104) +#define DDR_CR066 (DDR_CR_BASE + 0x108) +#define DDR_CR067 (DDR_CR_BASE + 0x10C) +#define DDR_CR068 (DDR_CR_BASE + 0x110) +#define DDR_CR069 (DDR_CR_BASE + 0x114) + +#define DDR_CR070 (DDR_CR_BASE + 0x118) +#define DDR_CR071 (DDR_CR_BASE + 0x11C) +#define DDR_CR072 (DDR_CR_BASE + 0x120) +#define DDR_CR073 (DDR_CR_BASE + 0x124) +#define DDR_CR074 (DDR_CR_BASE + 0x128) +#define DDR_CR075 (DDR_CR_BASE + 0x12C) +#define DDR_CR076 (DDR_CR_BASE + 0x130) +#define DDR_CR077 (DDR_CR_BASE + 0x134) +#define DDR_CR078 (DDR_CR_BASE + 0x138) +#define DDR_CR079 (DDR_CR_BASE + 0x13C) + +#define DDR_CR080 (DDR_CR_BASE + 0x140) +#define DDR_CR081 (DDR_CR_BASE + 0x144) +#define DDR_CR082 (DDR_CR_BASE + 0x148) +#define DDR_CR083 (DDR_CR_BASE + 0x14C) +#define DDR_CR084 (DDR_CR_BASE + 0x150) +#define DDR_CR085 (DDR_CR_BASE + 0x154) +#define DDR_CR086 (DDR_CR_BASE + 0x158) +#define DDR_CR087 (DDR_CR_BASE + 0x15C) +#define DDR_CR088 (DDR_CR_BASE + 0x160) +#define DDR_CR089 (DDR_CR_BASE + 0x164) + +#define DDR_CR090 (DDR_CR_BASE + 0x168) +#define DDR_CR091 (DDR_CR_BASE + 0x16C) +#define DDR_CR092 (DDR_CR_BASE + 0x170) +#define DDR_CR093 (DDR_CR_BASE + 0x174) +#define DDR_CR094 (DDR_CR_BASE + 0x178) +#define DDR_CR095 (DDR_CR_BASE + 0x17C) +#define DDR_CR096 (DDR_CR_BASE + 0x180) +#define DDR_CR097 (DDR_CR_BASE + 0x184) +#define DDR_CR098 (DDR_CR_BASE + 0x188) +#define DDR_CR099 (DDR_CR_BASE + 0x18C) + +#define DDR_CR100 (DDR_CR_BASE + 0x190) +#define DDR_CR101 (DDR_CR_BASE + 0x194) +#define DDR_CR102 (DDR_CR_BASE + 0x198) +#define DDR_CR103 (DDR_CR_BASE + 0x19C) +#define DDR_CR104 (DDR_CR_BASE + 0x1A0) +#define DDR_CR105 (DDR_CR_BASE + 0x1A4) +#define DDR_CR106 (DDR_CR_BASE + 0x1A8) +#define DDR_CR107 (DDR_CR_BASE + 0x1AC) +#define DDR_CR108 (DDR_CR_BASE + 0x1B0) +#define DDR_CR109 (DDR_CR_BASE + 0x1B4) + +#define DDR_CR110 (DDR_CR_BASE + 0x1B8) +#define DDR_CR111 (DDR_CR_BASE + 0x1BC) +#define DDR_CR112 (DDR_CR_BASE + 0x1C0) +#define DDR_CR113 (DDR_CR_BASE + 0x1C4) +#define DDR_CR114 (DDR_CR_BASE + 0x1C8) +#define DDR_CR115 (DDR_CR_BASE + 0x1CC) +#define DDR_CR116 (DDR_CR_BASE + 0x1D0) +#define DDR_CR117 (DDR_CR_BASE + 0x1D4) +#define DDR_CR118 (DDR_CR_BASE + 0x1D8) +#define DDR_CR119 (DDR_CR_BASE + 0x1DC) + +#define DDR_CR120 (DDR_CR_BASE + 0x1E0) +#define DDR_CR121 (DDR_CR_BASE + 0x1E4) +#define DDR_CR122 (DDR_CR_BASE + 0x1E8) +#define DDR_CR123 (DDR_CR_BASE + 0x1EC) +#define DDR_CR124 (DDR_CR_BASE + 0x1F0) +#define DDR_CR125 (DDR_CR_BASE + 0x1F4) +#define DDR_CR126 (DDR_CR_BASE + 0x1F8) +#define DDR_CR127 (DDR_CR_BASE + 0x1FC) +#define DDR_CR128 (DDR_CR_BASE + 0x200) +#define DDR_CR129 (DDR_CR_BASE + 0x204) + +#define DDR_CR130 (DDR_CR_BASE + 0x208) +#define DDR_CR131 (DDR_CR_BASE + 0x20C) +#define DDR_CR132 (DDR_CR_BASE + 0x210) +#define DDR_CR133 (DDR_CR_BASE + 0x214) +#define DDR_CR134 (DDR_CR_BASE + 0x218) +#define DDR_CR135 (DDR_CR_BASE + 0x21C) +#define DDR_CR136 (DDR_CR_BASE + 0x220) +#define DDR_CR137 (DDR_CR_BASE + 0x224) +#define DDR_CR138 (DDR_CR_BASE + 0x228) +#define DDR_CR139 (DDR_CR_BASE + 0x22C) + +#define DDR_CR140 (DDR_CR_BASE + 0x230) +#define DDR_CR141 (DDR_CR_BASE + 0x234) +#define DDR_CR142 (DDR_CR_BASE + 0x238) +#define DDR_CR143 (DDR_CR_BASE + 0x23C) +#define DDR_CR144 (DDR_CR_BASE + 0x240) +#define DDR_CR145 (DDR_CR_BASE + 0x244) +#define DDR_CR146 (DDR_CR_BASE + 0x248) +#define DDR_CR147 (DDR_CR_BASE + 0x24C) +#define DDR_CR148 (DDR_CR_BASE + 0x250) +#define DDR_CR149 (DDR_CR_BASE + 0x254) + +#define DDR_CR150 (DDR_CR_BASE + 0x258) +#define DDR_CR151 (DDR_CR_BASE + 0x25C) +#define DDR_CR152 (DDR_CR_BASE + 0x260) +#define DDR_CR153 (DDR_CR_BASE + 0x264) +#define DDR_CR154 (DDR_CR_BASE + 0x268) +#define DDR_CR155 (DDR_CR_BASE + 0x26C) +#define DDR_CR156 (DDR_CR_BASE + 0x270) +#define DDR_CR157 (DDR_CR_BASE + 0x274) +#define DDR_CR158 (DDR_CR_BASE + 0x278) +#define DDR_CR159 (DDR_CR_BASE + 0x27C) + +#define DDR_CR160 (DDR_CR_BASE + 0x280) +#define DDR_CR161 (DDR_CR_BASE + 0x284) +#define DDR_CR162 (DDR_CR_BASE + 0x288) +#define DDR_CR163 (DDR_CR_BASE + 0x28C) +#define DDR_CR164 (DDR_CR_BASE + 0x290) +#define DDR_CR165 (DDR_CR_BASE + 0x294) +#define DDR_CR166 (DDR_CR_BASE + 0x298) +#define DDR_CR167 (DDR_CR_BASE + 0x29C) +#define DDR_CR168 (DDR_CR_BASE + 0x2A0) +#define DDR_CR169 (DDR_CR_BASE + 0x2A4) + +#define DDR_CR170 (DDR_CR_BASE + 0x2A8) +#define DDR_CR171 (DDR_CR_BASE + 0x2AC) +#define DDR_CR172 (DDR_CR_BASE + 0x2B0) +#define DDR_CR173 (DDR_CR_BASE + 0x2B4) +#define DDR_CR174 (DDR_CR_BASE + 0x2B8) +#define DDR_CR175 (DDR_CR_BASE + 0x2BC) +#define DDR_CR176 (DDR_CR_BASE + 0x2C0) +#define DDR_CR177 (DDR_CR_BASE + 0x2C4) +#define DDR_CR178 (DDR_CR_BASE + 0x2C8) +#define DDR_CR179 (DDR_CR_BASE + 0x2CC) + +/* + * PHY + */ +#define DDR_PHY000 (DDR_PHY_BASE + 0x000) +#define DDR_PHY001 (DDR_PHY_BASE + 0x004) +#define DDR_PHY002 (DDR_PHY_BASE + 0x008) +#define DDR_PHY003 (DDR_PHY_BASE + 0x00C) +#define DDR_PHY004 (DDR_PHY_BASE + 0x010) +#define DDR_PHY005 (DDR_PHY_BASE + 0x014) +#define DDR_PHY006 (DDR_PHY_BASE + 0x018) +#define DDR_PHY007 (DDR_PHY_BASE + 0x01C) +#define DDR_PHY008 (DDR_PHY_BASE + 0x020) +#define DDR_PHY009 (DDR_PHY_BASE + 0x024) + +#define DDR_PHY010 (DDR_PHY_BASE + 0x028) +#define DDR_PHY011 (DDR_PHY_BASE + 0x02C) +#define DDR_PHY012 (DDR_PHY_BASE + 0x030) +#define DDR_PHY013 (DDR_PHY_BASE + 0x034) +#define DDR_PHY014 (DDR_PHY_BASE + 0x038) +#define DDR_PHY015 (DDR_PHY_BASE + 0x03C) +#define DDR_PHY016 (DDR_PHY_BASE + 0x040) +#define DDR_PHY017 (DDR_PHY_BASE + 0x044) +#define DDR_PHY018 (DDR_PHY_BASE + 0x048) +#define DDR_PHY019 (DDR_PHY_BASE + 0x04C) + +#define DDR_PHY020 (DDR_PHY_BASE + 0x050) +#define DDR_PHY021 (DDR_PHY_BASE + 0x054) +#define DDR_PHY022 (DDR_PHY_BASE + 0x058) +#define DDR_PHY023 (DDR_PHY_BASE + 0x05C) +#define DDR_PHY024 (DDR_PHY_BASE + 0x060) +#define DDR_PHY025 (DDR_PHY_BASE + 0x064) +#define DDR_PHY026 (DDR_PHY_BASE + 0x068) +#define DDR_PHY027 (DDR_PHY_BASE + 0x06C) +#define DDR_PHY028 (DDR_PHY_BASE + 0x070) +#define DDR_PHY029 (DDR_PHY_BASE + 0x074) + +#define DDR_PHY030 (DDR_PHY_BASE + 0x078) +#define DDR_PHY031 (DDR_PHY_BASE + 0x07C) +#define DDR_PHY032 (DDR_PHY_BASE + 0x080) +#define DDR_PHY033 (DDR_PHY_BASE + 0x084) +#define DDR_PHY034 (DDR_PHY_BASE + 0x088) +#define DDR_PHY035 (DDR_PHY_BASE + 0x08C) +#define DDR_PHY036 (DDR_PHY_BASE + 0x090) +#define DDR_PHY037 (DDR_PHY_BASE + 0x094) +#define DDR_PHY038 (DDR_PHY_BASE + 0x098) +#define DDR_PHY039 (DDR_PHY_BASE + 0x09C) + +#define DDR_PHY040 (DDR_PHY_BASE + 0x0A0) +#define DDR_PHY041 (DDR_PHY_BASE + 0x0A4) +#define DDR_PHY042 (DDR_PHY_BASE + 0x0A8) +#define DDR_PHY043 (DDR_PHY_BASE + 0x0AC) +#define DDR_PHY044 (DDR_PHY_BASE + 0x0B0) +#define DDR_PHY045 (DDR_PHY_BASE + 0x0B4) +#define DDR_PHY046 (DDR_PHY_BASE + 0x0B8) +#define DDR_PHY047 (DDR_PHY_BASE + 0x0BC) +#define DDR_PHY048 (DDR_PHY_BASE + 0x0C0) +#define DDR_PHY049 (DDR_PHY_BASE + 0x0C4) + +#define DDR_PHY050 (DDR_PHY_BASE + 0x0C8) +#define DDR_PHY051 (DDR_PHY_BASE + 0x0CC) +#define DDR_PHY052 (DDR_PHY_BASE + 0x0D0) +#define DDR_PHY053 (DDR_PHY_BASE + 0x0D4) +#define DDR_PHY054 (DDR_PHY_BASE + 0x0D8) +#define DDR_PHY055 (DDR_PHY_BASE + 0x0DC) +#define DDR_PHY056 (DDR_PHY_BASE + 0x0E0) +#define DDR_PHY057 (DDR_PHY_BASE + 0x0E4) +#define DDR_PHY058 (DDR_PHY_BASE + 0x0E8) +#define DDR_PHY059 (DDR_PHY_BASE + 0x0EC) + +#define DDR_PHY060 (DDR_PHY_BASE + 0x0F0) +#define DDR_PHY061 (DDR_PHY_BASE + 0x0F4) +#define DDR_PHY062 (DDR_PHY_BASE + 0x0F8) +#define DDR_PHY063 (DDR_PHY_BASE + 0x0FC) +#define DDR_PHY064 (DDR_PHY_BASE + 0x100) +#define DDR_PHY065 (DDR_PHY_BASE + 0x104) +#define DDR_PHY066 (DDR_PHY_BASE + 0x108) +#define DDR_PHY067 (DDR_PHY_BASE + 0x10C) +#define DDR_PHY068 (DDR_PHY_BASE + 0x110) + +#endif /* __ASSEMBLER__*/ + +#endif /* __ASM_ARCH_VYBRID_REGS_H__ */ |