diff options
Diffstat (limited to 'arch/arm/include/asm/arch-tegra2/clock.h')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra2/clock.h | 149 |
1 files changed, 123 insertions, 26 deletions
diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h index d01aec825d..49e9904b57 100644 --- a/arch/arm/include/asm/arch-tegra2/clock.h +++ b/arch/arm/include/asm/arch-tegra2/clock.h @@ -22,7 +22,7 @@ /* Tegra2 clock control functions */ #ifndef _CLOCK_H - +#define _CLOCK_H /* Set of oscillator frequencies supported in the internal API. */ enum clock_osc_freq { @@ -36,22 +36,27 @@ enum clock_osc_freq { }; /* The PLLs supported by the hardware */ -enum clock_pll_id { - CLOCK_PLL_ID_FIRST, - CLOCK_PLL_ID_CGENERAL = CLOCK_PLL_ID_FIRST, - CLOCK_PLL_ID_MEMORY, - CLOCK_PLL_ID_PERIPH, - CLOCK_PLL_ID_AUDIO, - CLOCK_PLL_ID_USB, - CLOCK_PLL_ID_DISPLAY, +enum clock_id { + CLOCK_ID_FIRST, + CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, + CLOCK_ID_MEMORY, + CLOCK_ID_PERIPH, + CLOCK_ID_AUDIO, + CLOCK_ID_USB, + CLOCK_ID_DISPLAY, /* now the simple ones */ - CLOCK_PLL_ID_FIRST_SIMPLE, - CLOCK_PLL_ID_XCPU = CLOCK_PLL_ID_FIRST_SIMPLE, - CLOCK_PLL_ID_EPCI, - CLOCK_PLL_ID_SFROM32KHZ, + CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, + CLOCK_ID_EPCI, + CLOCK_ID_SFROM32KHZ, + + /* These are the base clocks (inputs to the Tegra SOC) */ + CLOCK_ID_32KHZ, + CLOCK_ID_OSC, - CLOCK_PLL_ID_COUNT, + CLOCK_ID_COUNT, /* number of clocks */ + CLOCK_ID_NONE = -1, }; /* The clocks supported by the hardware */ @@ -80,7 +85,7 @@ enum periph_id { /* 16 */ PERIPH_ID_TWC, - PERIPH_ID_PWC, + PERIPH_ID_PWM, PERIPH_ID_I2S2, PERIPH_ID_EPP, PERIPH_ID_VI, @@ -181,12 +186,7 @@ enum periph_id { #define PERIPH_MASK(id) (1 << ((id) & 0x1f)) /* return 1 if a PLL ID is in range */ -#define clock_pll_id_isvalid(id) ((id) >= CLOCK_PLL_ID_FIRST && \ - (id) < CLOCK_PLL_ID_COUNT) - -/* return 1 if a peripheral ID is in range */ -#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ - (id) < PERIPH_ID_COUNT) +#define clock_id_isvalid(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) /* PLL stabilization delay in usec */ #define CLOCK_PLL_STABLE_DELAY_US 300 @@ -194,7 +194,7 @@ enum periph_id { /* return the current oscillator clock frequency */ enum clock_osc_freq clock_get_osc_freq(void); -/* +/** * Start PLL using the provided configuration parameters. * * @param id clock id @@ -206,7 +206,7 @@ enum clock_osc_freq clock_get_osc_freq(void); * * @returns monotonic time in us that the PLL will be stable */ -unsigned long clock_start_pll(enum clock_pll_id id, u32 divm, u32 divn, +unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, u32 divp, u32 cpcon, u32 lfcon); /* @@ -217,6 +217,13 @@ unsigned long clock_start_pll(enum clock_pll_id id, u32 divm, u32 divn, void clock_enable(enum periph_id clkid); /* + * Disable a clock + * + * @param id clock id + */ +void clock_disable(enum periph_id clkid); + +/* * Set whether a clock is enabled or disabled. * * @param id clock id @@ -224,7 +231,7 @@ void clock_enable(enum periph_id clkid); */ void clock_set_enable(enum periph_id clkid, int enable); -/* +/** * Reset a peripheral. This puts it in reset, waits for a delay, then takes * it out of reset and waits for th delay again. * @@ -233,7 +240,7 @@ void clock_set_enable(enum periph_id clkid, int enable); */ void reset_periph(enum periph_id periph_id, int us_delay); -/* +/** * Put a peripheral into or out of reset. * * @param periph_id peripheral to reset @@ -251,7 +258,7 @@ enum crc_reset_id { crc_rst_debug = 1 << 4, }; -/* +/** * Put parts of the CPU complex into or out of reset.\ * * @param cpu cpu number (0 or 1 on Tegra2) @@ -260,4 +267,94 @@ enum crc_reset_id { */ void reset_cmplx_set_enable(int cpu, int which, int reset); +/** + * Set the source for a peripheral clock. This plus the divisor sets the + * clock rate. You need to look up the datasheet to see the meaning of the + * source parameter as it changes for each peripheral. + * + * Warning: This function is only for use pre-relocation. Please use + * clock_start_periph_pll() instead. + * + * @param periph_id peripheral to adjust + * @param source source clock (0, 1, 2 or 3) + */ +void clock_ll_set_source(enum periph_id periph_id, unsigned source); + +/** + * Set the source and divisor for a peripheral clock. This sets the + * clock rate. You need to look up the datasheet to see the meaning of the + * source parameter as it changes for each peripheral. + * + * Warning: This function is only for use pre-relocation. Please use + * clock_start_periph_pll() instead. + * + * @param periph_id peripheral to adjust + * @param source source clock (0, 1, 2 or 3) + * @param divisor divisor value to use + */ +void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, + unsigned divisor); + +/** + * Start a peripheral PLL clock at the given rate. This also resets the + * peripheral. + * + * @param periph_id peripheral to start + * @param parent PLL id of required parent clock + * @param rate Required clock rate in Hz + * @return rate selected in Hz, or -1U if something went wrong + */ +unsigned clock_start_periph_pll(enum periph_id periph_id, + enum clock_id parent, unsigned rate); + +/** + * Returns the rate of a peripheral clock in Hz. Since the caller almost + * certainly knows the parent clock (having just set it) we require that + * this be passed in so we don't need to work it out. + * + * @param periph_id peripheral to start + * @param parent PLL id of parent clock (used to calculate rate, you + * must know this!) + * @return clock rate of peripheral in Hz + */ +unsigned long clock_get_periph_rate(enum periph_id periph_id, + enum clock_id parent); + +/** + * Adjust peripheral PLL clock to the given rate. This does not reset the + * peripheral. If a second stage divisor is not available, pass NULL for + * extra_div. If it is available, then this parameter will return the + * divisor selected (which will be a power of 2 from 1 to 256). + * + * @param periph_id peripheral to start + * @param parent PLL id of required parent clock + * @param rate Required clock rate in Hz + * @param extra_div value for the second-stage divisor (NULL if one is + not available) + * @return rate selected in Hz, or -1U if something went wrong + */ +unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, + enum clock_id parent, unsigned rate, int *extra_div); + +/** + * Returns the clock rate of a specified clock, in Hz. + * + * @param parent PLL id of clock to check + * @return rate of clock in Hz + */ +unsigned clock_get_rate(enum clock_id clkid); + +/* + * Checks that clocks are valid and prints a warning if not + * + * @return 0 if ok, -1 on error + */ +int clock_verify(void); + +/* Initialize the clocks */ +void clock_init(void); + +/* Initialize the PLLs */ +void clock_early_init(void); + #endif |