diff options
Diffstat (limited to 'arch/arm/include/asm/arch-s5pc2xx')
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc2xx/clk.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc2xx/cpu.h | 12 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc2xx/gpio.h | 7 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc2xx/mmc.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc2xx/sromc.h | 51 |
5 files changed, 67 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-s5pc2xx/clk.h b/arch/arm/include/asm/arch-s5pc2xx/clk.h index 5a1cdf1510..ff0f6415d8 100644 --- a/arch/arm/include/asm/arch-s5pc2xx/clk.h +++ b/arch/arm/include/asm/arch-s5pc2xx/clk.h @@ -32,5 +32,6 @@ unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); +void set_mmc_clk(int dev_index, unsigned int div); #endif diff --git a/arch/arm/include/asm/arch-s5pc2xx/cpu.h b/arch/arm/include/asm/arch-s5pc2xx/cpu.h index d56ee802fc..f9015c76f1 100644 --- a/arch/arm/include/asm/arch-s5pc2xx/cpu.h +++ b/arch/arm/include/asm/arch-s5pc2xx/cpu.h @@ -51,6 +51,12 @@ #include <asm/io.h> /* CPU detection macros */ extern unsigned int s5p_cpu_id; +extern unsigned int s5p_cpu_rev; + +static inline int s5p_get_cpu_rev(void) +{ + return s5p_cpu_rev; +} static inline void s5p_set_cpu_id(void) { @@ -61,8 +67,12 @@ static inline void s5p_set_cpu_id(void) * 0xC200: S5PC210 EVT0 * 0xC210: S5PC210 EVT1 */ - if (s5p_cpu_id == 0xC200) + if (s5p_cpu_id == 0xC200) { s5p_cpu_id |= 0x10; + s5p_cpu_rev = 0; + } else if (s5p_cpu_id == 0xC210) { + s5p_cpu_rev = 1; + } } #define IS_SAMSUNG_TYPE(type, id) \ diff --git a/arch/arm/include/asm/arch-s5pc2xx/gpio.h b/arch/arm/include/asm/arch-s5pc2xx/gpio.h index 05e5b3e0b7..38303e4f0c 100644 --- a/arch/arm/include/asm/arch-s5pc2xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc2xx/gpio.h @@ -99,14 +99,13 @@ void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); /* Pull mode */ #define GPIO_PULL_NONE 0x0 #define GPIO_PULL_DOWN 0x1 -#define GPIO_PULL_UP 0x2 +#define GPIO_PULL_UP 0x3 /* Drive Strength level */ #define GPIO_DRV_1X 0x0 -#define GPIO_DRV_2X 0x1 -#define GPIO_DRV_3X 0x2 +#define GPIO_DRV_3X 0x1 +#define GPIO_DRV_2X 0x2 #define GPIO_DRV_4X 0x3 #define GPIO_DRV_FAST 0x0 #define GPIO_DRV_SLOW 0x1 - #endif diff --git a/arch/arm/include/asm/arch-s5pc2xx/mmc.h b/arch/arm/include/asm/arch-s5pc2xx/mmc.h index 04827cad75..30f82b8aaf 100644 --- a/arch/arm/include/asm/arch-s5pc2xx/mmc.h +++ b/arch/arm/include/asm/arch-s5pc2xx/mmc.h @@ -64,6 +64,7 @@ struct mmc_host { struct s5p_mmc *reg; unsigned int version; /* SDHCI spec. version */ unsigned int clock; /* Current clock (MHz) */ + int dev_index; }; int s5p_mmc_init(int dev_index, int bus_width); diff --git a/arch/arm/include/asm/arch-s5pc2xx/sromc.h b/arch/arm/include/asm/arch-s5pc2xx/sromc.h new file mode 100644 index 0000000000..f616bcb37b --- /dev/null +++ b/arch/arm/include/asm/arch-s5pc2xx/sromc.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Naveen Krishna Ch <ch.naveen@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: This file contains the register description for SROMC + * + */ + +#ifndef __ASM_ARCH_SROMC_H_ +#define __ASM_ARCH_SROMC_H_ + +#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0)) +#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ + /* 1-> Byte base address*/ +#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2)) +#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3)) + +#define SROMC_BC_TACS(x) (x << 28) /* address set-up */ +#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */ +#define SROMC_BC_TACC(x) (x << 16) /* access cycle */ +#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */ +#define SROMC_BC_TAH(x) (x << 8) /* address holding time */ +#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */ +#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ + +#ifndef __ASSEMBLY__ +struct s5p_sromc { + unsigned int bw; + unsigned int bc[4]; +}; +#endif /* __ASSEMBLY__ */ + +/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ +void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); + +#endif /* __ASM_ARCH_SROMC_H_ */ |