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Diffstat (limited to 'arch/arm/include/asm/arch-s5pc1xx')
-rw-r--r--arch/arm/include/asm/arch-s5pc1xx/clk.h1
-rw-r--r--arch/arm/include/asm/arch-s5pc1xx/gpio.h4
-rw-r--r--arch/arm/include/asm/arch-s5pc1xx/mmc.h1
-rw-r--r--arch/arm/include/asm/arch-s5pc1xx/sromc.h (renamed from arch/arm/include/asm/arch-s5pc1xx/smc.h)8
4 files changed, 8 insertions, 6 deletions
diff --git a/arch/arm/include/asm/arch-s5pc1xx/clk.h b/arch/arm/include/asm/arch-s5pc1xx/clk.h
index 4c389c1fc5..692dfe0633 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/clk.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/clk.h
@@ -33,5 +33,6 @@ unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
unsigned long get_pwm_clk(void);
unsigned long get_uart_clk(int dev_index);
+void set_mmc_clk(int dev_index, unsigned int div);
#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
index 2df33a607c..485b9bf8e0 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
@@ -149,8 +149,8 @@ void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
/* Drive Strength level */
#define GPIO_DRV_1X 0x0
-#define GPIO_DRV_2X 0x1
-#define GPIO_DRV_3X 0x2
+#define GPIO_DRV_3X 0x1
+#define GPIO_DRV_2X 0x2
#define GPIO_DRV_4X 0x3
#define GPIO_DRV_FAST 0x0
#define GPIO_DRV_SLOW 0x1
diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
index d458d3bb8e..adef4ee21d 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
@@ -64,6 +64,7 @@ struct mmc_host {
struct s5p_mmc *reg;
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
+ int dev_index;
};
int s5p_mmc_init(int dev_index, int bus_width);
diff --git a/arch/arm/include/asm/arch-s5pc1xx/smc.h b/arch/arm/include/asm/arch-s5pc1xx/sromc.h
index 88f4ffe33a..3800a8dbae 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/smc.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/sromc.h
@@ -23,8 +23,8 @@
* Only SROMC is defined as of now
*/
-#ifndef __ASM_ARCH_SMC_H_
-#define __ASM_ARCH_SMC_H_
+#ifndef __ASM_ARCH_SROMC_H_
+#define __ASM_ARCH_SROMC_H_
#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
@@ -41,13 +41,13 @@
#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
#ifndef __ASSEMBLY__
-struct s5pc1xx_smc {
+struct s5p_sromc {
unsigned int bw;
unsigned int bc[6];
};
#endif /* __ASSEMBLY__ */
/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
-void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
#endif /* __ASM_ARCH_SMC_H_ */