7 files changed, 458 insertions, 131 deletions

diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index b9f1ca4da9..1698d061e7 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -7,7 +7,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
 obj-y	= iomux-v3.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
@@ -18,7 +18,13 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
 obj-y	+= misc.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 endif
-ifeq ($(SOC),$(filter $(SOC),mx6))
+ifeq ($(SOC),$(filter $(SOC),mx7))
+obj-y 	+= cpu.o
+obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
+obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
+endif
+ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
+obj-y 	+= cache.o init.o
 obj-$(CONFIG_CMD_SATA) += sata.o
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 endif
diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c
new file mode 100644
index 0000000000..54b021cfed
--- /dev/null
+++ b/arch/arm/imx-common/cache.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv7.h>
+#include <asm/pl310.h>
+#include <asm/io.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+	enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+	enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+	/* Avoid random hang when download by usb */
+	invalidate_dcache_all();
+
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+
+	/* Enable caching on OCRAM and ROM */
+	mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
+					ROMCP_ARB_END_ADDR,
+					option);
+	mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
+					IRAM_SIZE,
+					option);
+}
+#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#ifdef CONFIG_SYS_L2_PL310
+#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
+void v7_outer_cache_enable(void)
+{
+	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+	unsigned int val;
+
+
+	/*
+	 * Set bit 22 in the auxiliary control register. If this bit
+	 * is cleared, PL310 treats Normal Shared Non-cacheable
+	 * accesses as Cacheable no-allocate.
+	 */
+	setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+#if defined CONFIG_MX6SL
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	val = readl(&iomux->gpr[11]);
+	if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
+		/* L2 cache configured as OCRAM, reset it */
+		val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
+		writel(val, &iomux->gpr[11]);
+	}
+#endif
+
+	/* Must disable the L2 before changing the latency parameters */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+	writel(0x132, &pl310->pl310_tag_latency_ctrl);
+	writel(0x132, &pl310->pl310_data_latency_ctrl);
+
+	val = readl(&pl310->pl310_prefetch_ctrl);
+
+	/* Turn on the L2 I/D prefetch */
+	val |= 0x30000000;
+
+	/*
+	 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
+	 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
+	 * But according to ARM PL310 errata: 752271
+	 * ID: 752271: Double linefill feature can cause data corruption
+	 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
+	 * Workaround: The only workaround to this erratum is to disable the
+	 * double linefill feature. This is the default behavior.
+	 */
+
+#ifndef CONFIG_MX6Q
+	val |= 0x40800000;
+#endif
+	writel(val, &pl310->pl310_prefetch_ctrl);
+
+	val = readl(&pl310->pl310_power_ctrl);
+	val |= L2X0_DYNAMIC_CLK_GATING_EN;
+	val |= L2X0_STNDBY_MODE_EN;
+	writel(val, &pl310->pl310_power_ctrl);
+
+	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+#endif /* !CONFIG_SYS_L2_PL310 */
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index e27546c906..d3d1fc5afa 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -46,13 +46,28 @@ static char *get_reset_cause(void)
 	case 0x00008:
 		return "IPP USER";
 	case 0x00010:
+#ifdef	CONFIG_MX7
+		return "WDOG1";
+#else
 		return "WDOG";
+#endif
 	case 0x00020:
 		return "JTAG HIGH-Z";
 	case 0x00040:
 		return "JTAG SW";
+	case 0x00080:
+		return "WDOG3";
+#ifdef CONFIG_MX7
+	case 0x00100:
+		return "WDOG4";
+	case 0x00200:
+		return "TEMPSENSE";
+#else
+	case 0x00100:
+		return "TEMPSENSE";
 	case 0x10000:
 		return "WARM BOOT";
+#endif
 	default:
 		return "unknown reset";
 	}
@@ -122,6 +137,8 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
+	case MXC_CPU_MX7D:
+		return "7D";	/* Dual-core version of the mx7 */
 	case MXC_CPU_MX6QP:
 		return "6QP";	/* Quad-Plus version of the mx6 */
 	case MXC_CPU_MX6DP:
@@ -154,14 +171,12 @@ int print_cpuinfo(void)
 	u32 cpurev;
 	__maybe_unused u32 max_freq;
 
-#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
+	cpurev = get_cpu_rev();
+
+#if defined(CONFIG_IMX_THERMAL)
 	struct udevice *thermal_dev;
 	int cpu_tmp, minc, maxc, ret;
-#endif
-
-	cpurev = get_cpu_rev();
 
-#if defined(CONFIG_MX6)
 	printf("CPU:   Freescale i.MX%s rev%d.%d",
 	       get_imx_type((cpurev & 0xFF000) >> 12),
 	       (cpurev & 0x000F0) >> 4,
@@ -181,7 +196,7 @@ int print_cpuinfo(void)
 		mxc_get_clock(MXC_ARM_CLK) / 1000000);
 #endif
 
-#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
+#if defined(CONFIG_IMX_THERMAL)
 	puts("CPU:   ");
 	switch (get_cpu_temp_grade(&minc, &maxc)) {
 	case TEMP_AUTOMOTIVE:
@@ -205,9 +220,9 @@ int print_cpuinfo(void)
 		if (!ret)
 			printf(" at %dC\n", cpu_tmp);
 		else
-			puts(" - invalid sensor data\n");
+			debug(" - invalid sensor data\n");
 	} else {
-		puts(" - invalid sensor device\n");
+		debug(" - invalid sensor device\n");
 	}
 #endif
 
@@ -238,6 +253,7 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifndef CONFIG_MX7
 u32 get_ahb_clk(void)
 {
 	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -249,6 +265,7 @@ u32 get_ahb_clk(void)
 
 	return get_periph_clk() / (ahb_podf + 1);
 }
+#endif
 
 void arch_preboot_os(void)
 {
diff --git a/arch/arm/imx-common/ddrmc-vf610.c b/arch/arm/imx-common/ddrmc-vf610.c
index e46263144d..daf3c7ebfa 100644
--- a/arch/arm/imx-common/ddrmc-vf610.c
+++ b/arch/arm/imx-common/ddrmc-vf610.c
@@ -12,9 +12,9 @@
 #include <asm/arch/iomux-vf610.h>
 #include <asm/arch/ddrmc-vf610.h>
 
-void ddrmc_setup_iomux(void)
+void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
 {
-	static const iomux_v3_cfg_t ddr_pads[] = {
+	static const iomux_v3_cfg_t default_pads[] = {
 		VF610_PAD_DDR_A15__DDR_A_15,
 		VF610_PAD_DDR_A14__DDR_A_14,
 		VF610_PAD_DDR_A13__DDR_A_13,
@@ -65,76 +65,54 @@ void ddrmc_setup_iomux(void)
 		VF610_PAD_DDR_RESETB,
 	};
 
-	imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
-}
+	if ((pads == NULL) || (pads_count == 0)) {
+		pads = default_pads;
+		pads_count = ARRAY_SIZE(default_pads);
+	}
 
-void ddrmc_phy_init(void)
-{
-	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+	imx_iomux_v3_setup_multiple_pads(pads, pads_count);
+}
 
-	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
-	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
-	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
+static struct ddrmc_phy_setting default_phy_settings[] = {
+	{ DDRMC_PHY_DQ_TIMING,  0 },
+	{ DDRMC_PHY_DQ_TIMING, 16 },
+	{ DDRMC_PHY_DQ_TIMING, 32 },
 
-	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
-	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
+	{ DDRMC_PHY_DQS_TIMING,  1 },
+	{ DDRMC_PHY_DQS_TIMING, 17 },
 
-	writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
-	writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
-	writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
+	{ DDRMC_PHY_CTRL,  2 },
+	{ DDRMC_PHY_CTRL, 18 },
+	{ DDRMC_PHY_CTRL, 34 },
 
-	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
-	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
-	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
+	{ DDRMC_PHY_MASTER_CTRL,  3 },
+	{ DDRMC_PHY_MASTER_CTRL, 19 },
+	{ DDRMC_PHY_MASTER_CTRL, 35 },
 
-	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
-	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
-	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
+	{ DDRMC_PHY_SLAVE_CTRL,  4 },
+	{ DDRMC_PHY_SLAVE_CTRL, 20 },
+	{ DDRMC_PHY_SLAVE_CTRL, 36 },
 
 	/* LPDDR2 only parameter */
-	writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
+	{ DDRMC_PHY_OFF, 49 },
 
-	writel(DDRMC_PHY50_DDR3_MODE |
-		   DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]);
+	{ DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
 
 	/* Processor Pad ODT settings */
-	writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
-}
-
-static void ddrmc_ctrl_lvl_init(struct ddrmc_lvl_info *lvl)
-{
-	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
-	u32 cr102 = 0, cr105 = 0, cr106 = 0, cr110 = 0;
+	{ DDRMC_PHY_PROC_PAD_ODT, 52 },
 
-	if (lvl->wrlvl_reg_en) {
-		writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
-		writel(DDRMC_CR98_WRLVL_DL_0(lvl->wrlvl_dl_0), &ddrmr->cr[98]);
-		writel(DDRMC_CR99_WRLVL_DL_1(lvl->wrlvl_dl_1), &ddrmr->cr[99]);
-	}
-
-	if (lvl->rdlvl_reg_en) {
-		cr102 |= DDRMC_CR102_RDLVL_REG_EN;
-		cr105 |= DDRMC_CR105_RDLVL_DL_0(lvl->rdlvl_dl_0);
-		cr110 |= DDRMC_CR110_RDLVL_DL_1(lvl->rdlvl_dl_1);
-	}
-
-	if (lvl->rdlvl_gt_reg_en) {
-		cr102 |= DDRMC_CR102_RDLVL_GT_REGEN;
-		cr106 |= DDRMC_CR106_RDLVL_GTDL_0(lvl->rdlvl_gt_dl_0);
-		cr110 |= DDRMC_CR110_RDLVL_GTDL_1(lvl->rdlvl_gt_dl_1);
-	}
-
-	writel(cr102, &ddrmr->cr[102]);
-	writel(cr105, &ddrmr->cr[105]);
-	writel(cr106, &ddrmr->cr[106]);
-	writel(cr110, &ddrmr->cr[110]);
-}
+	/* end marker */
+	{ 0, -1 }
+};
 
 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
-						  struct ddrmc_lvl_info *lvl,
-						  int col_diff, int row_diff)
+			  struct ddrmc_cr_setting *board_cr_settings,
+			  struct ddrmc_phy_setting *board_phy_settings,
+			  int col_diff, int row_diff)
 {
 	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+	struct ddrmc_cr_setting *cr_setting;
+	struct ddrmc_phy_setting *phy_setting;
 
 	writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
 	writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
@@ -144,7 +122,9 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 	writel(DDRMC_CR12_WRLAT(timings->wrlat) |
 		   DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
 	writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
-		   DDRMC_CR13_TCCD(timings->tccd), &ddrmr->cr[13]);
+		   DDRMC_CR13_TCCD(timings->tccd) |
+		   DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval),
+		   &ddrmr->cr[13]);
 	writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
 		   DDRMC_CR14_TWTR(timings->twtr) |
 		   DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
@@ -156,18 +136,19 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 		   DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
 
 	writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
-	writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) |
-		   DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
+	writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | DDRMC_CR21_CCMAP_EN |
+		   DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout),
+		   &ddrmr->cr[21]);
 
 	writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
-	writel(DDRMC_CR23_BSTLEN(3) |
+	writel(DDRMC_CR23_BSTLEN(timings->bstlen) |
 		   DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
 	writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
 
 	writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
 	writel(DDRMC_CR26_TREF(timings->tref) |
 		   DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
-	writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]);
+	writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]);
 	writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
 
 	writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
@@ -177,7 +158,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 	writel(DDRMC_CR34_CKSRX(timings->cksrx) |
 		   DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
 
-	writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]);
+	writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]);
 	writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
 		   DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
 
@@ -191,13 +172,14 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 	writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
 
 	writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
-	writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
+	writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]);
 
 	writel(DDRMC_CR73_APREBIT(timings->aprebit) |
 		   DDRMC_CR73_COL_DIFF(col_diff) |
 		   DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
 	writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
-		   DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
+		   DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) |
+		   DDRMC_CR74_AGE_CNT(timings->age_cnt),
 		   &ddrmr->cr[74]);
 	writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
 		   DDRMC_CR75_PLEN, &ddrmr->cr[75]);
@@ -205,13 +187,15 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 		   DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
 	writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
 		   DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
-	writel(DDRMC_CR78_Q_FULLNESS(7) |
+	writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
 		   DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
 	writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
 
 	writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
 
-	writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
+	writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) |
+		   DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0),
+		   &ddrmr->cr[87]);
 	writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
 	writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
 
@@ -219,58 +203,33 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 	writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
 		   DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
 
-	if (lvl != NULL)
-		ddrmc_ctrl_lvl_init(lvl);
-
-	writel(DDRMC_CR117_AXI0_W_PRI(0) |
-		   DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]);
-	writel(DDRMC_CR118_AXI1_W_PRI(1) |
-		   DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]);
-
-	writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) |
-		   DDRMC_CR120_AXI0_PRI0_RPRI(2), &ddrmr->cr[120]);
-	writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) |
-		   DDRMC_CR121_AXI0_PRI2_RPRI(2), &ddrmr->cr[121]);
-	writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
-		   DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
-	writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
-		   DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
-	writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
-
-	writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]);
-	writel(DDRMC_CR132_WRLAT_ADJ(5) |
-		   DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]);
-	writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
-	writel(DDRMC_CR138_PHY_WRLV_MXDL(256) |
-		   DDRMC_CR138_PHYDRAM_CK_EN(1), &ddrmr->cr[138]);
-	writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
-		   DDRMC_CR139_PHY_WRLV_DLL(3) |
-		   DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]);
-	writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
-	writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) |
-		   DDRMC_CR143_RDLV_MXDL(128), &ddrmr->cr[143]);
-	writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
-		   DDRMC_CR144_PHY_RDLV_DLL(3) |
-		   DDRMC_CR144_PHY_RDLV_EN(3), &ddrmr->cr[144]);
-	writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
-	writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
-	writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
-	writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
-	writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
-		   DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
-
-	writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
-		   DDRMC_CR154_PAD_ZQ_MODE(1) |
-		   DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
-		   DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
-	writel(DDRMC_CR155_PAD_ODT_BYTE1(2) |
-		   DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]);
-	writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
-	writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
-		   DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
-
-	ddrmc_phy_init();
+	/* execute custom CR setting sequence (may be NULL) */
+	cr_setting = board_cr_settings;
+	if (cr_setting != NULL)
+		while (cr_setting->cr_rnum >= 0) {
+			writel(cr_setting->setting,
+			       &ddrmr->cr[cr_setting->cr_rnum]);
+			cr_setting++;
+		}
+
+	/* perform default PHY settings (may be overriden by custom settings */
+	phy_setting = default_phy_settings;
+	while (phy_setting->phy_rnum >= 0) {
+		writel(phy_setting->setting,
+		       &ddrmr->phy[phy_setting->phy_rnum]);
+		phy_setting++;
+	}
+
+	/* execute custom PHY setting sequence (may be NULL) */
+	phy_setting = board_phy_settings;
+	if (phy_setting != NULL)
+		while (phy_setting->phy_rnum >= 0) {
+			writel(phy_setting->setting,
+			       &ddrmr->phy[phy_setting->phy_rnum]);
+			phy_setting++;
+		}
 
+	/* all inits done, start the DDR controller */
 	writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
 
 	while (!(readl(&ddrmr->cr[80]) && 0x100))
diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c
new file mode 100644
index 0000000000..15dab1d904
--- /dev/null
+++ b/arch/arm/imx-common/init.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/arch/crm_regs.h>
+
+void init_aips(void)
+{
+	struct aipstz_regs *aips1, *aips2, *aips3;
+
+	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
+	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
+	aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
+
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	writel(0x77777777, &aips1->mprot0);
+	writel(0x77777777, &aips1->mprot1);
+	writel(0x77777777, &aips2->mprot0);
+	writel(0x77777777, &aips2->mprot1);
+
+	/*
+	 * Set all OPACRx to be non-bufferable, not require
+	 * supervisor privilege level for access,allow for
+	 * write access and untrusted master access.
+	 */
+	writel(0x00000000, &aips1->opacr0);
+	writel(0x00000000, &aips1->opacr1);
+	writel(0x00000000, &aips1->opacr2);
+	writel(0x00000000, &aips1->opacr3);
+	writel(0x00000000, &aips1->opacr4);
+	writel(0x00000000, &aips2->opacr0);
+	writel(0x00000000, &aips2->opacr1);
+	writel(0x00000000, &aips2->opacr2);
+	writel(0x00000000, &aips2->opacr3);
+	writel(0x00000000, &aips2->opacr4);
+
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) {
+		/*
+		 * Set all MPROTx to be non-bufferable, trusted for R/W,
+		 * not forced to user-mode.
+		 */
+		writel(0x77777777, &aips3->mprot0);
+		writel(0x77777777, &aips3->mprot1);
+
+		/*
+		 * Set all OPACRx to be non-bufferable, not require
+		 * supervisor privilege level for access,allow for
+		 * write access and untrusted master access.
+		 */
+		writel(0x00000000, &aips3->opacr0);
+		writel(0x00000000, &aips3->opacr1);
+		writel(0x00000000, &aips3->opacr2);
+		writel(0x00000000, &aips3->opacr3);
+		writel(0x00000000, &aips3->opacr4);
+	}
+}
+
+void imx_set_wdog_powerdown(bool enable)
+{
+	struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
+	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+	struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
+#ifdef CONFIG_MX7D
+	struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
+#endif
+
+	/* Write to the PDE (Power Down Enable) bit */
+	writew(enable, &wdog1->wmcr);
+	writew(enable, &wdog2->wmcr);
+
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+			is_soc_type(MXC_SOC_MX7))
+		writew(enable, &wdog3->wmcr);
+#ifdef CONFIG_MX7D
+	writew(enable, &wdog4->wmcr);
+#endif
+}
+
+#define SRC_SCR_WARM_RESET_ENABLE	0
+
+void init_src(void)
+{
+	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+	u32 val;
+
+	/*
+	 * force warm reset sources to generate cold reset
+	 * for a more reliable restart
+	 */
+	val = readl(&src_regs->scr);
+	val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
+	writel(val, &src_regs->scr);
+}
+
+#ifdef CONFIG_CMD_BMODE
+void boot_mode_apply(unsigned cfg_val)
+{
+	unsigned reg;
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	writel(cfg_val, &psrc->gpr9);
+	reg = readl(&psrc->gpr10);
+	if (cfg_val)
+		reg |= 1 << 28;
+	else
+		reg &= ~(1 << 28);
+	writel(reg, &psrc->gpr10);
+}
+#endif
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index b4f481fa53..228d5f8f1c 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -11,10 +11,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#if !defined(CONFIG_MX25) && !defined(CONFIG_VF610)
-#include <asm/arch/sys_proto.h>
-#endif
 #include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/sys_proto.h>
 
 static void *base = (void *)IOMUXC_BASE_ADDR;
 
@@ -53,7 +51,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 	}
 #endif
 
-	if (mux_ctrl_ofs)
+	if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs)
 		__raw_writel(mux_mode, base + mux_ctrl_ofs);
 
 	if (sel_input_ofs)
diff --git a/arch/arm/imx-common/syscounter.c b/arch/arm/imx-common/syscounter.c
new file mode 100644
index 0000000000..e00fef2665
--- /dev/null
+++ b/arch/arm/imx-common/syscounter.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * The file use ls102xa/timer.c as a reference.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/syscounter.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long usec)
+{
+	ulong ticks;
+
+	if (usec < 1000)
+		ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+	else
+		ticks = ((usec / 10) * (get_tbclk() / 100000));
+
+	return ticks;
+}
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	unsigned long freq;
+
+	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, freq);
+
+	return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+	unsigned long freq;
+
+	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+	usec = usec * freq  + 999999;
+	do_div(usec, 1000000);
+
+	return usec;
+}
+
+int timer_init(void)
+{
+	struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
+	unsigned long val, freq;
+
+	freq = CONFIG_SC_TIMER_CLK;
+	asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+	writel(freq, &sctr->cntfid0);
+
+	/* Enable system counter */
+	val = readl(&sctr->cntcr);
+	val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
+	val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
+	writel(val, &sctr->cntcr);
+
+	gd->arch.tbl = 0;
+	gd->arch.tbu = 0;
+
+	return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+	unsigned long long now;
+
+	asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
+
+	gd->arch.tbl = (unsigned long)(now & 0xffffffff);
+	gd->arch.tbu = (unsigned long)(now >> 32);
+
+	return now;
+}
+
+ulong get_timer_masked(void)
+{
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	unsigned long freq;
+
+	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+	return freq;
+}