diff options
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi | 16 | ||||
| -rw-r--r-- | arch/arm/dts/imx6sx-sabreauto.dts | 40 |
2 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi b/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi new file mode 100644 index 00000000000..f5c68d707c3 --- /dev/null +++ b/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +&qspi1 { + num-cs = <2>; + + flash0: n25q256a@0 { + compatible = "spi-flash"; + }; + + flash1: n25q256a@1 { + compatible = "spi-flash"; + }; +}; diff --git a/arch/arm/dts/imx6sx-sabreauto.dts b/arch/arm/dts/imx6sx-sabreauto.dts index a4c2627f974..9643d1fe064 100644 --- a/arch/arm/dts/imx6sx-sabreauto.dts +++ b/arch/arm/dts/imx6sx-sabreauto.dts @@ -96,6 +96,29 @@ }; }; +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + &iomuxc { imx6x-sabreauto { pinctrl_i2c2_1: i2c2grp-1 { @@ -112,6 +135,23 @@ >; }; + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1 + MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1 + MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1 + MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1 + MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1 + MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1 + MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1 + MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1 + MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1 + MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1 + MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1 + MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 |