diff options
Diffstat (limited to 'arch/arm/dts/k3-am625-verdin-r5.dts')
| -rw-r--r-- | arch/arm/dts/k3-am625-verdin-r5.dts | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts new file mode 100644 index 0000000000..05fdd00b85 --- /dev/null +++ b/arch/arm/dts/k3-am625-verdin-r5.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Toradex Verdin AM62 dts file for R5 SPL + * Copyright 2023 Toradex - https://www.toradex.com/ + */ + +#include "k3-am625-verdin-wifi-dev.dts" +#include "k3-am625-verdin-lpddr4-1600MTs.dtsi" +#include "k3-am62-ddr.dtsi" + +#include "k3-am625-verdin-wifi-dev-binman.dtsi" +#include "k3-am625-verdin-wifi-dev-u-boot.dtsi" + +/ { + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + /* + * FIXME: Currently only the SPL running on the R5 has a clock + * driver. As a workaround therefore move the assigned-clock + * stuff required for our ETH_25MHz_CLK from the cpsw3g_mdio + * node of the regular device tree to here (last one each in + * below three lines, adding a <0> as spacing for parents). + */ + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 20>; + assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 22>; + assigned-clock-rates = <200000000>, <800000000>, <25000000>; + clocks = <&k3_clks 61 0>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + ti,sci = <&dmsc>; + ti,sci-host-id = <10>; + ti,sci-proc-id = <32>; + bootph-pre-ram; + }; + + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 22>, + <&secure_proxy_main 23>; + ti,host-id = <36>; + ti,secure-host; + bootph-pre-ram; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + bootph-pre-ram; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; +}; + +&cbass_main { + sa3_secproxy: secproxy@44880000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "rt", "scfg", "target_data"; + reg = <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>, + <0x00 0x43600000 0x00 0x10000>; + bootph-pre-ram; + }; + + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-pre-ram; + }; + + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x420000 0x0 0x1000>; + ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; + bootph-pre-ram; + }; +}; + +&cbass_mcu { + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x4100000 0x0 0x1000>; + ti,esm-pins = <0>, <1>, <2>, <85>; + bootph-pre-ram; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; |