diff options
Diffstat (limited to 'arch/arm/dts/imx6qdl-aristainetos2.dtsi')
| -rw-r--r-- | arch/arm/dts/imx6qdl-aristainetos2.dtsi | 244 |
1 files changed, 0 insertions, 244 deletions
diff --git a/arch/arm/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/dts/imx6qdl-aristainetos2.dtsi deleted file mode 100644 index 788e13edad..0000000000 --- a/arch/arm/dts/imx6qdl-aristainetos2.dtsi +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2019 Heiko Schocher <hs@denx.de> - * Copyright (C) 2015 Heiko Schocher <hs@denx.de> - * - */ -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/clock/imx6qdl-clock.h> - -#include "imx6qdl-aristainetos2-common.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio>; - - LED_blue { - label = "led_blue"; - gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; - }; - - LED_green { - label = "led_green"; - gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; - }; - - LED_red { - label = "led_red"; - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - }; - - LED_yellow { - label = "led_yellow"; - gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; - }; - - LED_ena { - label = "led_ena"; - gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH - &gpio4 10 GPIO_ACTIVE_HIGH - &gpio4 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; -}; - -&ecspi4 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "okay"; - pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - - flash: m25p80@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <1>; - }; -}; - -&gpio7 { - sd2_driver_ena { - gpio-hog; - output-high; - gpios = <8 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */ - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 /* WP pin */ - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - /* led enable */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 - /* LCD power enable */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 - /* led yellow */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 - /* led red */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 - /* led green */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 - /* led blue */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 - /* Profibus IRQ */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - /* FPGA IRQ currently unused*/ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 - /* Display reset because of clock failure */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 - /* spi bus #2 SS driver enable */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 - /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 - /* USB_OTG_ID = GPIO1_24*/ - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x4001b0b0 - /* Touchscreen IRQ */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - /* PCIe reset */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 - >; - }; - - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - /* SD1 card detect input */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 - /* SD1 write protect input */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 - /* SD2 level shifter output enable */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 - /* SD2 card detect input */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - /* SD2 write protect input */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - >; - }; -}; |