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-rw-r--r--arch/arm/cpu/armv7/am33xx/clock.c1
-rw-r--r--arch/arm/cpu/armv7/omap-common/boot-common.c2
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c2
-rw-r--r--arch/arm/cpu/armv8/start.S2
4 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 595c951ed24..9b9b78edddc 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -237,4 +237,5 @@ void prcm_init()
enable_basic_clocks();
scale_vcores();
setup_dplls();
+ timer_init();
}
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index ed9ba7b5d3e..0456263d6ec 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -111,6 +111,8 @@ void save_omap_boot_params(void)
(boot_device <= MMC_BOOT_DEVICES_END)) {
switch (boot_device) {
case BOOT_DEVICE_MMC1:
+ boot_mode = MMCSD_MODE_FS;
+ break;
case BOOT_DEVICE_MMC2:
boot_mode = MMCSD_MODE_RAW;
break;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index d580a43b412..a9b12a43add 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -180,7 +180,7 @@ ulong get_ddr_freq(ulong ctrl_num)
/*
* DDR controller 0 & 1 are on memory complex 0
- * DDR controler 2 is on memory complext 1
+ * DDR controller 2 is on memory complext 1
*/
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num >= 2)
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index deb44a895fd..c3cc8199caf 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -214,7 +214,9 @@ WEAK(lowlevel_init)
ldr x1, =GICC_BASE
bl gic_init_secure_percpu
#endif
+#endif
+#ifndef CONFIG_ARMV8_MULTIENTRY
branch_if_master x0, x1, 2f
/*