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-rw-r--r--arch/arm/cpu/armv7/cache_v7.c21
-rw-r--r--arch/arm/cpu/armv7/ls102xa/fdt.c16
-rw-r--r--arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c10
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fdt.c3
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c5
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/soc.c9
-rw-r--r--arch/arm/cpu/armv8/start.S19
-rw-r--r--arch/arm/cpu/armv8/zynqmp/Kconfig4
-rw-r--r--arch/arm/cpu/armv8/zynqmp/clk.c20
-rw-r--r--arch/arm/cpu/armv8/zynqmp/cpu.c18
-rw-r--r--arch/arm/cpu/u-boot.lds27
11 files changed, 113 insertions, 39 deletions
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index a5aa4fa643..94ff48859e 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -16,6 +16,23 @@
#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
#ifndef CONFIG_SYS_DCACHE_OFF
+static int check_cache_range(unsigned long start, unsigned long stop)
+{
+ int ok = 1;
+
+ if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+ ok = 0;
+
+ if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+ ok = 0;
+
+ if (!ok)
+ debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+ start, stop);
+
+ return ok;
+}
+
/*
* Write the level and type you want to Cache Size Selection Register(CSSELR)
* to get size details from Current Cache Size ID Register(CCSIDR)
@@ -257,6 +274,8 @@ void flush_dcache_all(void)
*/
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
+ check_cache_range(start, stop);
+
v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
v7_outer_cache_inval_range(start, stop);
@@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop)
*/
void flush_dcache_range(unsigned long start, unsigned long stop)
{
+ check_cache_range(start, stop);
+
v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
v7_outer_cache_flush_range(start, stop);
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index 856abed941..ae5e794230 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -30,17 +30,13 @@ void ft_fixup_enet_phy_connect_type(void *fdt)
int phy_node;
int i = 0;
uint32_t ph;
+ char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
- while ((dev = eth_get_dev_by_index(i++)) != NULL) {
- if (strstr(dev->name, "eTSEC1")) {
- strcpy(enet, "ethernet0");
- strcpy(phy, "enet0_rgmii_phy");
- } else if (strstr(dev->name, "eTSEC2")) {
- strcpy(enet, "ethernet1");
- strcpy(phy, "enet1_rgmii_phy");
- } else if (strstr(dev->name, "eTSEC3")) {
- strcpy(enet, "ethernet2");
- strcpy(phy, "enet2_rgmii_phy");
+ for (; i < ARRAY_SIZE(name); i++) {
+ dev = eth_get_dev_by_name(name[i]);
+ if (dev) {
+ sprintf(enet, "ethernet%d", i);
+ sprintf(phy, "enet%d_rgmii_phy", i);
} else {
continue;
}
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
index deeb674c69..144f2c368d 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
@@ -11,11 +11,11 @@
/* port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
-#define AHCI_PORT_PHY_2_CFG 0x28183411
-#define AHCI_PORT_PHY_3_CFG 0x0e081004
-#define AHCI_PORT_PHY_4_CFG 0x00480811
-#define AHCI_PORT_PHY_5_CFG 0x192c96a4
-#define AHCI_PORT_TRANS_CFG 0x08000025
+#define AHCI_PORT_PHY_2_CFG 0x28183414
+#define AHCI_PORT_PHY_3_CFG 0x0e080e06
+#define AHCI_PORT_PHY_4_CFG 0x064a080b
+#define AHCI_PORT_PHY_5_CFG 0x2aa86470
+#define AHCI_PORT_TRANS_CFG 0x08000029
#define SATA_ECC_REG_ADDR 0x20220520
#define SATA_ECC_DISABLE 0x00020000
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index eafdd71a84..4e4861d107 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -190,6 +190,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
#endif
+ do_fixup_by_compat_u32(blob, "fixed-clock",
+ "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
index 8ef4f1c38f..ea3114cca4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
@@ -28,12 +28,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
SGMII1 } },
{0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
{0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
-#ifdef CONFIG_LS2080A
- {0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } },
-#endif
-#ifdef CONFIG_LS2085A
{0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
-#endif
{0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
{0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
{0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A,
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 23d6b73e3d..7ff01481be 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -12,6 +12,9 @@
#include <asm/io.h>
#include <asm/global_data.h>
#include <asm/arch-fsl-layerscape/config.h>
+#ifdef CONFIG_CHAIN_OF_TRUST
+#include <fsl_validate.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -219,6 +222,9 @@ void fsl_lsch2_early_init_f(void)
init_early_memctl_regs(); /* tighten IFC timing */
#endif
+#ifdef CONFIG_FSL_QSPI
+ out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
/* Make SEC reads and writes snoopable */
setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
SCFG_SNPCNFGCR_SECWRSNP);
@@ -241,6 +247,9 @@ int board_late_init(void)
#ifdef CONFIG_SCSI_AHCI_PLAT
sata_init();
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
return 0;
}
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 2ee60d60f1..67b166c7fd 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -168,6 +168,25 @@ apply_a57_core_errata:
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
+#ifdef CONFIG_ARM_ERRATA_833471
+ mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
+ /* FPSCR write flush.
+ * Note that in some cases where a flush is unnecessary this
+ could impact performance. */
+ orr x0, x0, #1 << 38
+ msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_829520
+ mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
+ /* Disable Indirect Predictor bit will prevent this erratum
+ from occurring
+ * Note that in some cases where a flush is unnecessary this
+ could impact performance. */
+ orr x0, x0, #1 << 4
+ msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
+#endif
+
#ifdef CONFIG_ARM_ERRATA_833069
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Disable Enable Invalidates of BTB bit */
diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index e5a4fdd0fd..9a19dfa77f 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -20,10 +20,6 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP
-config SECURE_IOU
- bool "Configure ZynqMP secure IOU"
- default n
-
config ZYNQMP_USB
bool "Configure ZynqMP USB"
diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c
index 9218586e94..690c72dd66 100644
--- a/arch/arm/cpu/armv8/zynqmp/clk.c
+++ b/arch/arm/cpu/armv8/zynqmp/clk.c
@@ -21,9 +21,27 @@ unsigned long get_uart_clk(int dev_id)
return 48000;
case ZYNQMP_CSU_VERSION_EP108:
return 25000000;
+ case ZYNQMP_CSU_VERSION_QEMU:
+ return 133000000;
}
- return 133000000;
+ return 100000000;
+}
+
+unsigned long zynqmp_get_system_timer_freq(void)
+{
+ u32 ver = zynqmp_get_silicon_version();
+
+ switch (ver) {
+ case ZYNQMP_CSU_VERSION_VELOCE:
+ return 10000;
+ case ZYNQMP_CSU_VERSION_EP108:
+ return 4000000;
+ case ZYNQMP_CSU_VERSION_QEMU:
+ return 50000000;
+ }
+
+ return 100000000;
}
#ifdef CONFIG_CLOCKS
diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index f90cca36aa..c71f29152d 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -15,8 +15,22 @@
DECLARE_GLOBAL_DATA_PTR;
+static unsigned int zynqmp_get_silicon_version_secure(void)
+{
+ u32 ver;
+
+ ver = readl(&csu_base->version);
+ ver &= ZYNQMP_SILICON_VER_MASK;
+ ver >>= ZYNQMP_SILICON_VER_SHIFT;
+
+ return ver;
+}
+
unsigned int zynqmp_get_silicon_version(void)
{
+ if (current_el() == 3)
+ return zynqmp_get_silicon_version_secure();
+
gd->cpu_clk = get_tbclk();
switch (gd->cpu_clk) {
@@ -24,9 +38,11 @@ unsigned int zynqmp_get_silicon_version(void)
return ZYNQMP_CSU_VERSION_VELOCE;
case 50000000:
return ZYNQMP_CSU_VERSION_QEMU;
+ case 4000000:
+ return ZYNQMP_CSU_VERSION_EP108;
}
- return ZYNQMP_CSU_VERSION_EP108;
+ return ZYNQMP_CSU_VERSION_SILICON;
}
#ifndef CONFIG_SYS_DCACHE_OFF
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index d48a905cf3..e148ab7513 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -14,23 +14,24 @@ OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
+#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC)
/*
- * Discard the relocation entries for secure text.
- * The secure code is bundled with u-boot image, so there will
- * be relocations entries for the secure code, since we use
- * "-mword-relocations" to compile and "-pie" to link into the
- * final image. We do not need the relocation entries for secure
- * code, because secure code will not be relocated, it only needs
- * to be copied from loading address to CONFIG_ARMV7_SECURE_BASE,
- * which is the linking and running address for secure code.
- * If keep the relocation entries in .rel.dyn section,
- * "relocation offset + linking address" may locates into an
- * address that is reserved by SoC, then will trigger data abort.
+ * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not
+ * bundle with u-boot, and code offsets are fixed. Secure zone
+ * only needs to be copied from the loading address to
+ * CONFIG_ARMV7_SECURE_BASE, which is the linking and running
+ * address for secure code.
*
- * The reason that move .rel._secure at the beginning, is to
- * avoid hole in the final image.
+ * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will
+ * be included in u-boot address space, and some absolute address
+ * were used in secure code. The absolute addresses of the secure
+ * code also needs to be relocated along with the accompanying u-boot
+ * code.
+ *
+ * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE.
*/
/DISCARD/ : { *(.rel._secure*) }
+#endif
. = 0x00000000;
. = ALIGN(4);
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-03 09:56:53 +0000