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-rw-r--r--arch/arm/cpu/armv8/Kconfig3
-rw-r--r--arch/arm/cpu/armv8/cache.S19
-rw-r--r--arch/arm/cpu/armv8/fel_utils.S20
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/Kconfig25
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c2
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch336
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc8
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c4
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c6
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S4
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c2
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/soc.c2
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/spintable.S2
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/spl.c4
-rw-r--r--arch/arm/cpu/armv8/hisilicon/pinmux.c2
-rw-r--r--arch/arm/cpu/armv8/transition.S2
-rw-r--r--arch/arm/cpu/armv8/xen/hypercall.S1
17 files changed, 77 insertions, 65 deletions
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index b7a10a8e34e..0a3fdfa4716 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -3,7 +3,6 @@ if ARM64
config ARMV8_SPL_EXCEPTION_VECTORS
bool "Install crash dump exception vectors"
depends on SPL
- default n
help
The default exception vector table is only used for the crash
dump, but still takes quite a lot of space in the image size.
@@ -128,7 +127,6 @@ config PSCI_RESET
config ARMV8_PSCI
bool "Enable PSCI support" if EXPERT
- default n
help
PSCI is Power State Coordination Interface defined by ARM.
The PSCI in U-boot provides a general framework and each platform
@@ -156,7 +154,6 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER
config ARMV8_EA_EL3_FIRST
bool "External aborts and SError interrupt exception are taken in EL3"
- default n
help
Exception handling at all exception levels for External Abort and
SError interrupt exception are taken in EL3.
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index e04907dd8c0..d1cee23437d 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -27,13 +27,11 @@ ENTRY(__asm_dcache_level)
msr csselr_el1, x12 /* select cache level */
isb /* sync change of cssidr_el1 */
mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
- and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
+ ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */
+ ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */
+ ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */
add x2, x2, #4 /* x2 <- log2(cache line size) */
- mov x3, #0x3ff
- and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
clz w5, w3 /* bit position of #ways */
- mov x4, #0x7fff
- and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
/* x12 <- cache level << 1 */
/* x2 <- line length offset */
/* x3 <- number of cache ways - 1 */
@@ -72,8 +70,7 @@ ENTRY(__asm_dcache_all)
mov x1, x0
dsb sy
mrs x10, clidr_el1 /* read clidr_el1 */
- lsr x11, x10, #24
- and x11, x11, #0x7 /* x11 <- loc */
+ ubfx x11, x10, #24, #3 /* x11 <- loc */
cbz x11, finished /* if loc is 0, exit */
mov x15, lr
mov x0, #0 /* start flush at cache level 0 */
@@ -83,8 +80,7 @@ ENTRY(__asm_dcache_all)
/* x15 <- return address */
loop_level:
- lsl x12, x0, #1
- add x12, x12, x0 /* x0 <- tripled cache level */
+ add x12, x0, x0, lsl #1 /* x12 <- tripled cache level */
lsr x12, x10, x12
and x12, x12, #7 /* x12 <- cache type */
cmp x12, #2
@@ -131,8 +127,7 @@ ENDPROC(__asm_invalidate_dcache_all)
.pushsection .text.__asm_flush_dcache_range, "ax"
ENTRY(__asm_flush_dcache_range)
mrs x3, ctr_el0
- lsr x3, x3, #16
- and x3, x3, #0xf
+ ubfx x3, x3, #16, #4
mov x2, #4
lsl x2, x2, x3 /* cache line size */
@@ -158,7 +153,7 @@ ENDPROC(__asm_flush_dcache_range)
.pushsection .text.__asm_invalidate_dcache_range, "ax"
ENTRY(__asm_invalidate_dcache_range)
mrs x3, ctr_el0
- ubfm x3, x3, #16, #19
+ ubfx x3, x3, #16, #4
mov x2, #4
lsl x2, x2, x3 /* cache line size */
diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S
index 7def44ad1d3..5266515f145 100644
--- a/arch/arm/cpu/armv8/fel_utils.S
+++ b/arch/arm/cpu/armv8/fel_utils.S
@@ -64,18 +64,18 @@ ENTRY(return_to_fel)
/* AArch32 code to restore the state from fel_stash and return back to FEL. */
back_in_32:
- .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address
- .word 0xe5901008 // ldr r1, [r0, #8]
- .word 0xe129f001 // msr CPSR_fc, r1
+ .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address
+ .word 0xe5901008 // ldr r1, [r0, #8]
+ .word 0xe129f001 // msr CPSR_fc, r1
.word 0xf57ff06f // isb
- .word 0xe590d000 // ldr sp, [r0]
- .word 0xe590e004 // ldr lr, [r0, #4]
- .word 0xe5901010 // ldr r1, [r0, #16]
- .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR
- .word 0xe590100c // ldr r1, [r0, #12]
- .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
+ .word 0xe590d000 // ldr sp, [r0]
+ .word 0xe590e004 // ldr lr, [r0, #4]
+ .word 0xe5901010 // ldr r1, [r0, #16]
+ .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR
+ .word 0xe590100c // ldr r1, [r0, #12]
+ .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
.word 0xf57ff06f // isb
- .word 0xe12fff1e // bx lr ; return to FEL
+ .word 0xe12fff1e // bx lr ; return to FEL
fel_stash_addr:
.word 0x00000000 // receives fel_stash addr, by AA64 code above
ENDPROC(return_to_fel)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 9cef363fbaa..1e166c73e40 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -4,6 +4,8 @@ config ARCH_LS1012A
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH2
+ select GICV2
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE
@@ -25,6 +27,7 @@ config ARCH_LS1028A
select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select GICV3
select NXP_LSCH3_2
select SYS_FSL_HAS_CCI400
select SYS_FSL_SRDS_1
@@ -58,7 +61,9 @@ config ARCH_LS1043A
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH2
+ select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@@ -84,13 +89,16 @@ config ARCH_LS1043A
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
imply CMD_PCI
+ imply ID_EEPROM
config ARCH_LS1046A
bool
select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE
select FSL_LSCH2
+ select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@@ -117,8 +125,10 @@ config ARCH_LS1046A
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
+ imply ID_EEPROM
imply SCSI
imply SCSI_AHCI
+ imply SPL_SYS_I2C_LEGACY
config ARCH_LS1088A
bool
@@ -126,6 +136,8 @@ config ARCH_LS1088A
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select GICV3
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@@ -158,7 +170,9 @@ config ARCH_LS1088A
select SYS_I2C_MXC_I2C3 if !TFABOOT
select SYS_I2C_MXC_I2C4 if !TFABOOT
select RESV_RAM if GIC_V3_ITS
+ imply ID_EEPROM
imply SCSI
+ imply SPL_SYS_I2C_LEGACY
imply PANIC_HANG
config ARCH_LS2080A
@@ -170,6 +184,8 @@ config ARCH_LS2080A
select ARM_ERRATA_833471
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select GICV3
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@@ -210,12 +226,15 @@ config ARCH_LS2080A
select SYS_I2C_MXC_I2C4 if !TFABOOT
select RESV_RAM if GIC_V3_ITS
imply DISTRO_DEFAULTS
+ imply ID_EEPROM
imply PANIC_HANG
+ imply SPL_SYS_I2C_LEGACY
config ARCH_LX2162A
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
+ select GICV3
select NXP_LSCH3_2
select SYS_HAS_SERDES
select SYS_FSL_SRDS_1
@@ -242,11 +261,13 @@ config ARCH_LX2162A
imply PANIC_HANG
imply SCSI
imply SCSI_AHCI
+ imply SPL_SYS_I2C_LEGACY
config ARCH_LX2160A
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
+ select GICV3
select HAS_FSL_XHCI_USB if USB_HOST
select NXP_LSCH3_2
select SYS_HAS_SERDES
@@ -272,12 +293,15 @@ config ARCH_LX2160A
select SYS_I2C_MXC
select RESV_RAM if GIC_V3_ITS
imply DISTRO_DEFAULTS
+ imply ID_EEPROM
imply PANIC_HANG
imply SCSI
imply SCSI_AHCI
+ imply SPL_SYS_I2C_LEGACY
config FSL_LSCH2
bool
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
@@ -429,7 +453,6 @@ config QSPI_AHB_INIT
config FSPI_AHB_EN_4BYTE
bool "Enable 4-byte Fast Read command for AHB mode"
- default n
help
The default setting for FlexSPI AHB bus just supports 3-byte addressing.
But some FlexSPI flash sizes are up to 64MBytes.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d0103fc8811..1a359d060e8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1147,7 +1147,7 @@ int arch_early_init_r(void)
#endif
#ifdef CONFIG_SYS_FSL_HAS_RGMII
/* some dpmacs in armv8a based freescale layerscape SOCs can be
- * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
+ * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
* EC*_PMUX(rgmii) bits in RCW.
* e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
* serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
index 6c98d99d0cc..9119d60ffb3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
@@ -42,22 +42,22 @@ Flash Layout
pre-silicon platforms (simulator and emulator):
-------------------------
- | FIT Image |
+ | FIT Image |
| (linux + DTB + RFS) |
------------------------- ----> 0x0120_0000
- | Debug Server FW |
+ | Debug Server FW |
------------------------- ----> 0x00C0_0000
- | AIOP FW |
+ | AIOP FW |
------------------------- ----> 0x0070_0000
- | MC FW |
+ | MC FW |
------------------------- ----> 0x006C_0000
- | MC DPL Blob |
+ | MC DPL Blob |
------------------------- ----> 0x0020_0000
- | BootLoader + Env|
+ | BootLoader + Env|
------------------------- ----> 0x0000_1000
- | PBI |
+ | PBI |
------------------------- ----> 0x0000_0080
- | RCW |
+ | RCW |
------------------------- ----> 0x0000_0000
32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
@@ -70,45 +70,45 @@ Flash Layout
----------------------------------------- ----> 0x5_8790_0000 |
| FIT Image (linux + DTB + RFS) (40M) | |
----------------------------------------- ----> 0x5_8510_0000 |
- | PHY firmware (2M) | |
+ | PHY firmware (2M) | |
----------------------------------------- ----> 0x5_84F0_0000 | 64K
| Debug Server FW (2M) | | Alt
----------------------------------------- ----> 0x5_84D0_0000 | Bank
| AIOP FW (4M) | |
----------------------------------------- ----> 0x5_8490_0000 (vbank4)
- | MC DPC Blob (1M) | |
+ | MC DPC Blob (1M) | |
----------------------------------------- ----> 0x5_8480_0000 |
| MC DPL Blob (1M) | |
----------------------------------------- ----> 0x5_8470_0000 |
- | MC FW (4M) | |
+ | MC FW (4M) | |
----------------------------------------- ----> 0x5_8430_0000 |
- | BootLoader Environment (1M) | |
+ | BootLoader Environment (1M) | |
----------------------------------------- ----> 0x5_8420_0000 |
| BootLoader (1M) | |
----------------------------------------- ----> 0x5_8410_0000 |
- | RCW and PBI (1M) | |
+ | RCW and PBI (1M) | |
----------------------------------------- ----> 0x5_8400_0000 ---
| .. Unused .. (7M) | |
----------------------------------------- ----> 0x5_8390_0000 |
| FIT Image (linux + DTB + RFS) (40M) | |
----------------------------------------- ----> 0x5_8110_0000 |
- | PHY firmware (2M) | |
+ | PHY firmware (2M) | |
----------------------------------------- ----> 0x5_80F0_0000 | 64K
| Debug Server FW (2M) | | Bank
----------------------------------------- ----> 0x5_80D0_0000 |
| AIOP FW (4M) | |
----------------------------------------- ----> 0x5_8090_0000 (vbank0)
- | MC DPC Blob (1M) | |
+ | MC DPC Blob (1M) | |
----------------------------------------- ----> 0x5_8080_0000 |
| MC DPL Blob (1M) | |
----------------------------------------- ----> 0x5_8070_0000 |
- | MC FW (4M) | |
+ | MC FW (4M) | |
----------------------------------------- ----> 0x5_8030_0000 |
- | BootLoader Environment (1M) | |
+ | BootLoader Environment (1M) | |
----------------------------------------- ----> 0x5_8020_0000 |
| BootLoader (1M) | |
----------------------------------------- ----> 0x5_8010_0000 |
- | RCW and PBI (1M) | |
+ | RCW and PBI (1M) | |
----------------------------------------- ----> 0x5_8000_0000 ---
128-MB NOR flash layout for QDS and RDB boards
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index f33d05d0539..f2efd4cc1d7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -31,7 +31,7 @@ The LS1043A SoC includes the following function and features:
- Hardware buffer management for buffer allocation and de-allocation (BMan)
- Cryptography acceleration (SEC)
- Ethernet interfaces by FMan
- - Up to 1 x XFI supporting 10G interface
+ - Up to 1 x 10GBase-R supporting 10G interface
- Up to 1 x QSGMII
- Up to 4 x SGMII supporting 1000Mbps
- Up to 2 x SGMII supporting 2500Mbps
@@ -190,7 +190,7 @@ The LS1046A SoC includes the following function and features:
- Two PLLs per four-lane SerDes
- Support for 10G operation
- Ethernet interfaces by FMan
- - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
+ - Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10)
- Up to 1 x QSGMII (MAC 5, 6, 10, 1)
- Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
- Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
@@ -295,7 +295,7 @@ The LX2160A SoC includes the following function and features:
Single WRIOP tile supporting 130Gbps using 18 MACs
Support for 10G-SXGMII (aka USXGMII).
Support for SGMII (and 1000Base-KX)
- Support for XFI (and 10GBase-KR)
+ Support for 10GBase-R (and 10GBase-KR)
Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G).
Support for XLAUI (and 40GBase-KR4) for 40G.
Support for two RGMII parallel interfaces.
@@ -400,7 +400,7 @@ The LX2162A SoC includes the following function and features:
Ethernet interfaces
Support for 10G-SXGMII (aka USXGMII).
Support for SGMII (and 1000Base-KX)
- Support for XFI (and 10GBase-KR)
+ Support for 10GBase-R (and 10GBase-KR)
Support for CAUI2 (50G) and 25G-AUI(25G).
Support for XLAUI (and 40GBase-KR4) for 40G.
Support for two RGMII parallel interfaces.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 63d34e1ec03..3f97c8aee4a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -61,8 +61,8 @@ void get_sys_info(struct sys_info *sys_info)
#endif
cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
-#ifdef CONFIG_DDR_CLK_FREQ
- sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
+ sys_info->freq_ddrbus = get_board_ddr_clk();
#else
sys_info->freq_ddrbus = sysclk;
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index 25a1c36d2ac..6f50cbad2ba 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -78,10 +78,10 @@ void get_sys_info(struct sys_info *sys_info)
void *offset;
sys_info->freq_systembus = sysclk;
-#ifdef CONFIG_DDR_CLK_FREQ
- sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
+ sys_info->freq_ddrbus = get_board_ddr_clk();
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
+ sys_info->freq_ddrbus2 = get_board_ddr_clk();
#endif
#else
sys_info->freq_ddrbus = sysclk;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index d8803738f10..3aa1a9c3e5c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -250,7 +250,7 @@ ENTRY(lowlevel_init)
* b. We use only Region0 whose NSAID write/read is EN
*
* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
- * placeholders.
+ * placeholders.
*/
.macro tzasc_prog, xreg
@@ -259,7 +259,7 @@ ENTRY(lowlevel_init)
mov x16, #0x10000
mul x14, \xreg, x16
add x14, x14,x12
- mov x1, #0x8
+ mov x1, #0x8
add x1, x1, x14
ldr w0, [x1] /* Filter 0 Gate Keeper Register */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
index 280afbbf98f..26f8a498269 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
@@ -100,7 +100,7 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
/*
- * LS1044A/1048A support only one XFI port
+ * LS1044A/1048A support only one 10GBase-R port
* Disable MAC1 for LS1044A/1048A
*/
if (serdes == FSL_SRDS_1 && lane == 2) {
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 42a09685462..41f3e95019b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -329,7 +329,7 @@ static void erratum_rcw_src(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
static void erratum_a009203(void)
{
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
u8 __iomem *ptr;
#ifdef I2C1_BASE_ADDR
ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S
index 363ded03e60..d6bd1884599 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S
@@ -93,7 +93,7 @@ __secondary_boot_func:
4:
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
switch_el x7, _dead_loop, 0f, _dead_loop
-0: armv8_switch_to_el1_m x4, x6, x7
+0: armv8_switch_to_el1_m x4, x6, x7, x9
#else
switch_el x7, 0f, _dead_loop, _dead_loop
0: armv8_switch_to_el2_m x4, x6, x7
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 1d5e3444529..68111b6eff8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
u32 spl_boot_device(void)
{
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
return BOOT_DEVICE_MMC1;
#endif
#ifdef CONFIG_SPL_NAND_SUPPORT
@@ -88,7 +88,7 @@ void board_init_f(ulong dummy)
preloader_console_init();
spl_set_bd();
-#ifdef CONFIG_SYS_I2C_LEGACY
+#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
#ifdef CONFIG_SPL_I2C
i2c_init_all();
#endif
diff --git a/arch/arm/cpu/armv8/hisilicon/pinmux.c b/arch/arm/cpu/armv8/hisilicon/pinmux.c
index 5183e00a44c..e14057c0a47 100644
--- a/arch/arm/cpu/armv8/hisilicon/pinmux.c
+++ b/arch/arm/cpu/armv8/hisilicon/pinmux.c
@@ -181,5 +181,3 @@ int hi6220_pinmux_config(int peripheral)
return 0;
}
-
-
diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
index a31af4ffc89..9dbdff3a4fc 100644
--- a/arch/arm/cpu/armv8/transition.S
+++ b/arch/arm/cpu/armv8/transition.S
@@ -40,7 +40,7 @@ ENTRY(armv8_switch_to_el1)
* now, jump to the address saved in x4.
*/
br x4
-1: armv8_switch_to_el1_m x4, x5, x6
+1: armv8_switch_to_el1_m x4, x5, x6, x7
ENDPROC(armv8_switch_to_el1)
.popsection
diff --git a/arch/arm/cpu/armv8/xen/hypercall.S b/arch/arm/cpu/armv8/xen/hypercall.S
index 731256b34e2..e69ed408dc6 100644
--- a/arch/arm/cpu/armv8/xen/hypercall.S
+++ b/arch/arm/cpu/armv8/xen/hypercall.S
@@ -76,4 +76,3 @@ HYPERCALL2(sched_op);
HYPERCALL2(event_channel_op);
HYPERCALL2(hvm_op);
HYPERCALL2(memory_op);
-
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-18 07:18:00 +0000