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-rw-r--r--arch/arm/cpu/armv7/socfpga/misc.c14
-rw-r--r--arch/arm/cpu/armv7/socfpga/reset_manager.c12
2 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index ecae393410..b633615208 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -8,6 +8,7 @@
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
+#include <asm/arch/reset_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -36,6 +37,19 @@ int overwrite_console(void)
}
#endif
+int arch_cpu_init(void)
+{
+ /*
+ * If the HW watchdog is NOT enabled, make sure it is not running,
+ * for example because it was enabled in the preloader. This might
+ * trigger a watchdog-triggered reboot of Linux kernel later.
+ */
+#ifndef CONFIG_HW_WATCHDOG
+ socfpga_watchdog_reset();
+#endif
+ return 0;
+}
+
int misc_init_r(void)
{
return 0;
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index e320c011ae..5d7aba467f 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -14,6 +14,18 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
+/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
+void socfpga_watchdog_reset(void)
+{
+ /* assert reset for watchdog */
+ setbits_le32(&reset_manager_base->per_mod_reset,
+ 1 << RSTMGR_PERMODRST_L4WD0_LSB);
+
+ /* deassert watchdog from reset (watchdog in not running state) */
+ clrbits_le32(&reset_manager_base->per_mod_reset,
+ 1 << RSTMGR_PERMODRST_L4WD0_LSB);
+}
+
/*
* Write the reset manager register to cause reset
*/