diff options
Diffstat (limited to 'arch/arm/cpu/armv7/mx6/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 58 |
1 files changed, 3 insertions, 55 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 2283702bdd..7ad27574ed 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -24,15 +24,11 @@ #include <asm/arch/crm_regs.h> #include <dm.h> #include <imx_thermal.h> -#ifdef CONFIG_FASTBOOT +#ifdef CONFIG_FSL_FASTBOOT #ifdef CONFIG_ANDROID_RECOVERY #include <recovery.h> #endif #endif -#ifdef CONFIG_IMX_UDC -#include <asm/arch/mx6_usbphy.h> -#include <usb/imx_udc.h> -#endif enum ldo_reg { LDO_ARM, @@ -1020,7 +1016,7 @@ void v7_outer_cache_disable(void) #endif #endif /* !CONFIG_SYS_L2CACHE_OFF */ -#ifdef CONFIG_FASTBOOT +#ifdef CONFIG_FSL_FASTBOOT #ifdef CONFIG_ANDROID_RECOVERY #define ANDROID_RECOVERY_BOOT (1 << 7) @@ -1064,52 +1060,4 @@ int fastboot_check_and_clean_flag(void) return flag_set; } -#endif /*CONFIG_FASTBOOT*/ - -#ifdef CONFIG_IMX_UDC -void set_usboh3_clk(void) -{ - udc_pins_setting(); -} - -void set_usb_phy1_clk(void) -{ - /* make sure pll3 is enable here */ - struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel((BM_ANADIG_USB1_CHRG_DETECT_EN_B | - BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B), - &ccm_regs->usb1_chrg_detect_set); - - writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS, - &ccm_regs->analog_usb1_pll_480_ctrl_set); -} -void enable_usb_phy1_clk(unsigned char enable) -{ - if (enable) - writel(BM_USBPHY_CTRL_CLKGATE, - USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL_CLR); - else - writel(BM_USBPHY_CTRL_CLKGATE, - USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL_SET); -} - -void reset_usb_phy1(void) -{ - /* Reset USBPHY module */ - u32 temp; - temp = readl(USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL); - temp |= BM_USBPHY_CTRL_SFTRST; - writel(temp, USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL); - udelay(10); - - /* Remove CLKGATE and SFTRST */ - temp = readl(USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL); - temp &= ~(BM_USBPHY_CTRL_CLKGATE | BM_USBPHY_CTRL_SFTRST); - writel(temp, USB_PHY0_BASE_ADDR + HW_USBPHY_CTRL); - udelay(10); - - /* Power up the PHY */ - writel(0, USB_PHY0_BASE_ADDR + HW_USBPHY_PWD); -} -#endif +#endif /*CONFIG_FSL_FASTBOOT*/ |