diff options
Diffstat (limited to 'arch/arm/cpu/armv7/cache_v7.c')
| -rw-r--r-- | arch/arm/cpu/armv7/cache_v7.c | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 3e1e1bf877..1b4e808a79 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -81,8 +81,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, : : "r" (setway)); } } - /* DMB to make sure the operation is complete */ - CP15DMB; + /* DSB to make sure the operation is complete */ + CP15DSB; } static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, @@ -108,8 +108,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, : : "r" (setway)); } } - /* DMB to make sure the operation is complete */ - CP15DMB; + /* DSB to make sure the operation is complete */ + CP15DSB; } static void v7_maint_dcache_level_setway(u32 level, u32 operation) @@ -181,21 +181,23 @@ static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len) u32 mva; /* - * If start address is not aligned to cache-line flush the first - * line to prevent affecting somebody else's buffer + * If start address is not aligned to cache-line do not + * invalidate the first cache-line */ if (start & (line_len - 1)) { - v7_dcache_clean_inval_range(start, start + 1, line_len); + printf("ERROR: %s - start address is not aligned - 0x%08x\n", + __func__, start); /* move to next cache line */ start = (start + line_len - 1) & ~(line_len - 1); } /* - * If stop address is not aligned to cache-line flush the last - * line to prevent affecting somebody else's buffer + * If stop address is not aligned to cache-line do not + * invalidate the last cache-line */ if (stop & (line_len - 1)) { - v7_dcache_clean_inval_range(stop, stop + 1, line_len); + printf("ERROR: %s - stop address is not aligned - 0x%08x\n", + __func__, stop); /* align to the beginning of this cache line */ stop &= ~(line_len - 1); } @@ -227,8 +229,8 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) break; } - /* DMB to make sure the operation is complete */ - CP15DMB; + /* DSB to make sure the operation is complete */ + CP15DSB; } /* Invalidate TLB */ |