diff options
Diffstat (limited to 'arch/arm/cpu/arm926ejs')
23 files changed, 109 insertions, 118 deletions
diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c index c21938e31f..14121a08f8 100644 --- a/arch/arm/cpu/arm926ejs/armada100/cpu.c +++ b/arch/arm/cpu/arm926ejs/armada100/cpu.c @@ -24,8 +24,8 @@ */ #include <common.h> +#include <asm/arch/cpu.h> #include <asm/arch/armada100.h> -#include <asm/io.h> #define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1)) #define SET_MRVL_ID (1<<8) diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c index eacec2386d..8609004565 100644 --- a/arch/arm/cpu/arm926ejs/armada100/dram.c +++ b/arch/arm/cpu/arm926ejs/armada100/dram.c @@ -24,6 +24,7 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/armada100.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c index 82a6d7b72d..fbade4b459 100644 --- a/arch/arm/cpu/arm926ejs/armada100/timer.c +++ b/arch/arm/cpu/arm926ejs/armada100/timer.c @@ -24,6 +24,7 @@ */ #include <common.h> +#include <asm/arch/cpu.h> #include <asm/arch/armada100.h> /* diff --git a/arch/arm/cpu/arm926ejs/davinci/config.mk b/arch/arm/cpu/arm926ejs/davinci/config.mk deleted file mode 100644 index 565adda11d..0000000000 --- a/arch/arm/cpu/arm926ejs/davinci/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <gj@denx.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - -PLATFORM_CPPFLAGS += -march=armv5te -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/arch/arm/cpu/arm926ejs/davinci/et1011c.c b/arch/arm/cpu/arm926ejs/davinci/et1011c.c index da073457a3..df35e44d13 100644 --- a/arch/arm/cpu/arm926ejs/davinci/et1011c.c +++ b/arch/arm/cpu/arm926ejs/davinci/et1011c.c @@ -39,11 +39,9 @@ int et1011c_get_link_speed(int phy_addr) u_int16_t data; if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) { - davinci_eth_phy_read(EMAC_MDIO_PHY_NUM, - MII_PHY_CONFIG_REG, &data); + davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data); /* Enable 125MHz clock sourced from PHY */ - davinci_eth_phy_write(EMAC_MDIO_PHY_NUM, - MII_PHY_CONFIG_REG, + davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG, data | PHY_SYS_CLK_EN); return (1); } diff --git a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S index 0a4b2cf674..7a169b1076 100644 --- a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S @@ -45,6 +45,8 @@ #include <config.h> +#define MDSTAT_STATE 0x3f + .globl lowlevel_init lowlevel_init: @@ -268,7 +270,7 @@ checkStatClkStop: checkDDRStatClkStop: ldr r6, MDSTAT_DDR2 ldr r7, [r6] - and r7, r7, $0x1f + and r7, r7, $MDSTAT_STATE cmp r7, $0x03 bne checkDDRStatClkStop @@ -343,7 +345,7 @@ checkStatClkStop2: checkDDRStatClkStop2: ldr r6, MDSTAT_DDR2 ldr r7, [r6] - and r7, r7, $0x1f + and r7, r7, $MDSTAT_STATE cmp r7, $0x01 bne checkDDRStatClkStop2 @@ -374,7 +376,7 @@ checkStatClkEn2: checkDDRStatClkEn2: ldr r6, MDSTAT_DDR2 ldr r7, [r6] - and r7, r7, $0x1f + and r7, r7, $MDSTAT_STATE cmp r7, $0x03 bne checkDDRStatClkEn2 diff --git a/arch/arm/cpu/arm926ejs/davinci/psc.c b/arch/arm/cpu/arm926ejs/davinci/psc.c index 8273a7fae4..707fa47e31 100644 --- a/arch/arm/cpu/arm926ejs/davinci/psc.c +++ b/arch/arm/cpu/arm926ejs/davinci/psc.c @@ -83,7 +83,7 @@ void lpsc_on(unsigned int id) while (readl(ptstat) & 0x01) continue; - if ((readl(mdstat) & 0x1f) == 0x03) + if ((readl(mdstat) & PSC_MDSTAT_STATE) == 0x03) return; /* Already on and enabled */ writel(readl(mdctl) | 0x03, mdctl); @@ -114,7 +114,7 @@ void lpsc_on(unsigned int id) while (readl(ptstat) & 0x01) continue; - while ((readl(mdstat) & 0x1f) != 0x03) + while ((readl(mdstat) & PSC_MDSTAT_STATE) != 0x03) continue; } diff --git a/arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.s b/arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.s new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.s diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index b4a4c0428f..8f04ddbb86 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -26,6 +26,8 @@ #include <netdev.h> #include <asm/cache.h> #include <u-boot/md5.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> #include <asm/arch/kirkwood.h> #include <hush.h> diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c index 2441554ae3..181b3e7bd3 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/dram.c @@ -24,6 +24,8 @@ #include <config.h> #include <common.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> #include <asm/arch/kirkwood.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c index b2f0ad55e3..3da6c98d11 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c @@ -10,6 +10,8 @@ */ #include <common.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> #include <asm/arch/kirkwood.h> #include <asm/arch/mpp.h> diff --git a/arch/arm/cpu/arm926ejs/kirkwood/timer.c b/arch/arm/cpu/arm926ejs/kirkwood/timer.c index b4f6cf87e0..a98f54c05b 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/timer.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/timer.c @@ -22,6 +22,7 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/kirkwood.h> #define UBOOT_CNTR 0 /* counter to use for uboot timer */ diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index 8e60a262eb..c045a0bc58 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -39,7 +39,7 @@ * f = 2 * f_ref * -------------------- * pd + 1 */ -static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref) +static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) { unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT) & CCM_PLL_MFI_MASK; @@ -52,57 +52,57 @@ static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref) mfi = mfi <= 5 ? 5 : mfi; - return lldiv (2 * (u64) f_ref * (mfi * (mfd + 1) + mfn), + return lldiv(2 * (u64) f_ref * (mfi * (mfd + 1) + mfn), (mfd + 1) * (pd + 1)); } -static ulong imx_get_mpllclk (void) +static ulong imx_get_mpllclk(void) { struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; ulong fref = 24000000; - return imx_decode_pll (readl (&ccm->mpctl), fref); + return imx_decode_pll(readl(&ccm->mpctl), fref); } -ulong imx_get_armclk (void) +ulong imx_get_armclk(void) { struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - ulong cctl = readl (&ccm->cctl); - ulong fref = imx_get_mpllclk (); + ulong cctl = readl(&ccm->cctl); + ulong fref = imx_get_mpllclk(); ulong div; if (cctl & CCM_CCTL_ARM_SRC) - fref = lldiv ((fref * 3), 4); + fref = lldiv((fref * 3), 4); div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT) & CCM_CCTL_ARM_DIV_MASK) + 1; - return lldiv (fref, div); + return lldiv(fref, div); } -ulong imx_get_ahbclk (void) +ulong imx_get_ahbclk(void) { struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - ulong cctl = readl (&ccm->cctl); - ulong fref = imx_get_armclk (); + ulong cctl = readl(&ccm->cctl); + ulong fref = imx_get_armclk(); ulong div; div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT) & CCM_CCTL_AHB_DIV_MASK) + 1; - return lldiv (fref, div); + return lldiv(fref, div); } -ulong imx_get_perclk (int clk) +ulong imx_get_perclk(int clk) { struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - ulong fref = imx_get_ahbclk (); + ulong fref = imx_get_ahbclk(); ulong div; - div = readl (&ccm->pcdr[CCM_PERCLK_REG (clk)]); - div = ((div >> CCM_PERCLK_SHIFT (clk)) & CCM_PERCLK_MASK) + 1; + div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]); + div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1; - return lldiv (fref, div); + return lldiv(fref, div); } u32 get_cpu_rev(void) @@ -153,7 +153,7 @@ static char *get_reset_cause(void) } -int print_cpuinfo (void) +int print_cpuinfo(void) { char buf[32]; u32 cpurev = get_cpu_rev(); @@ -161,22 +161,22 @@ int print_cpuinfo (void) printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n", (cpurev & 0xF0) >> 4, (cpurev & 0x0F), ((cpurev & 0x8000) ? " unknown" : ""), - strmhz (buf, imx_get_armclk ())); + strmhz(buf, imx_get_armclk())); printf("Reset cause: %s\n\n", get_reset_cause()); return 0; } #endif -int cpu_eth_init (bd_t * bis) +int cpu_eth_init(bd_t *bis) { #if defined(CONFIG_FEC_MXC) struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; ulong val; - val = readl (&ccm->cgr0); + val = readl(&ccm->cgr0); val |= (1 << 23); - writel (val, &ccm->cgr0); - return fecmxc_initialize (bis); + writel(val, &ccm->cgr0); + return fecmxc_initialize(bis); #else return 0; #endif @@ -186,10 +186,10 @@ int cpu_eth_init (bd_t * bis) * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() */ -int cpu_mmc_init (bd_t * bis) +int cpu_mmc_init(bd_t *bis) { #ifdef CONFIG_MXC_MMC - return mxc_mmc_init (bis); + return mxc_mmc_init(bis); #else return 0; #endif @@ -206,7 +206,7 @@ void mx25_uart1_init_pins(void) muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; - muxmode0 = MX25_PIN_MUX_MODE (0); + muxmode0 = MX25_PIN_MUX_MODE(0); /* * set up input pins with hysteresis and 100K pull-ups */ @@ -227,25 +227,25 @@ void mx25_uart1_init_pins(void) /* UART1 */ /* rxd */ - writel (muxmode0, &muxctl->pad_uart1_rxd); - writel (inpadctl, &padctl->pad_uart1_rxd); + writel(muxmode0, &muxctl->pad_uart1_rxd); + writel(inpadctl, &padctl->pad_uart1_rxd); /* txd */ - writel (muxmode0, &muxctl->pad_uart1_txd); - writel (outpadctl, &padctl->pad_uart1_txd); + writel(muxmode0, &muxctl->pad_uart1_txd); + writel(outpadctl, &padctl->pad_uart1_txd); /* rts */ - writel (muxmode0, &muxctl->pad_uart1_rts); - writel (outpadctl, &padctl->pad_uart1_rts); + writel(muxmode0, &muxctl->pad_uart1_rts); + writel(outpadctl, &padctl->pad_uart1_rts); /* cts */ - writel (muxmode0, &muxctl->pad_uart1_cts); - writel (inpadctl, &padctl->pad_uart1_cts); + writel(muxmode0, &muxctl->pad_uart1_cts); + writel(inpadctl, &padctl->pad_uart1_cts); } #endif /* CONFIG_MXC_UART */ #ifdef CONFIG_FEC_MXC -void mx25_fec_init_pins (void) +void mx25_fec_init_pins(void) { struct iomuxc_mux_ctl *muxctl; struct iomuxc_pad_ctl *padctl; @@ -256,7 +256,7 @@ void mx25_fec_init_pins (void) muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; - muxmode0 = MX25_PIN_MUX_MODE (0); + muxmode0 = MX25_PIN_MUX_MODE(0); inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS | MX25_PIN_PAD_CTL_PKE | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; @@ -275,40 +275,40 @@ void mx25_fec_init_pins (void) outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; /* FEC_TX_CLK */ - writel (muxmode0, &muxctl->pad_fec_tx_clk); - writel (inpadctl_100kpd, &padctl->pad_fec_tx_clk); + writel(muxmode0, &muxctl->pad_fec_tx_clk); + writel(inpadctl_100kpd, &padctl->pad_fec_tx_clk); /* FEC_RX_DV */ - writel (muxmode0, &muxctl->pad_fec_rx_dv); - writel (inpadctl_100kpd, &padctl->pad_fec_rx_dv); + writel(muxmode0, &muxctl->pad_fec_rx_dv); + writel(inpadctl_100kpd, &padctl->pad_fec_rx_dv); /* FEC_RDATA0 */ - writel (muxmode0, &muxctl->pad_fec_rdata0); - writel (inpadctl_100kpd, &padctl->pad_fec_rdata0); + writel(muxmode0, &muxctl->pad_fec_rdata0); + writel(inpadctl_100kpd, &padctl->pad_fec_rdata0); /* FEC_TDATA0 */ - writel (muxmode0, &muxctl->pad_fec_tdata0); - writel (outpadctl, &padctl->pad_fec_tdata0); + writel(muxmode0, &muxctl->pad_fec_tdata0); + writel(outpadctl, &padctl->pad_fec_tdata0); /* FEC_TX_EN */ - writel (muxmode0, &muxctl->pad_fec_tx_en); - writel (outpadctl, &padctl->pad_fec_tx_en); + writel(muxmode0, &muxctl->pad_fec_tx_en); + writel(outpadctl, &padctl->pad_fec_tx_en); /* FEC_MDC */ - writel (muxmode0, &muxctl->pad_fec_mdc); - writel (outpadctl, &padctl->pad_fec_mdc); + writel(muxmode0, &muxctl->pad_fec_mdc); + writel(outpadctl, &padctl->pad_fec_mdc); /* FEC_MDIO */ - writel (muxmode0, &muxctl->pad_fec_mdio); - writel (inpadctl_22kpu, &padctl->pad_fec_mdio); + writel(muxmode0, &muxctl->pad_fec_mdio); + writel(inpadctl_22kpu, &padctl->pad_fec_mdio); /* FEC_RDATA1 */ - writel (muxmode0, &muxctl->pad_fec_rdata1); - writel (inpadctl_100kpd, &padctl->pad_fec_rdata1); + writel(muxmode0, &muxctl->pad_fec_rdata1); + writel(inpadctl_100kpd, &padctl->pad_fec_rdata1); /* FEC_TDATA1 */ - writel (muxmode0, &muxctl->pad_fec_tdata1); - writel (outpadctl, &padctl->pad_fec_tdata1); + writel(muxmode0, &muxctl->pad_fec_tdata1); + writel(outpadctl, &padctl->pad_fec_tdata1); } diff --git a/arch/arm/cpu/arm926ejs/mx25/reset.c b/arch/arm/cpu/arm926ejs/mx25/reset.c index 1a43683081..e6f1056670 100644 --- a/arch/arm/cpu/arm926ejs/mx25/reset.c +++ b/arch/arm/cpu/arm926ejs/mx25/reset.c @@ -39,7 +39,7 @@ /* * Reset the cpu by setting up the watchdog timer and let it time out */ -void reset_cpu (ulong ignored) +void reset_cpu(ulong ignored) { struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; /* Disable watchdog and set Time-Out field to 0 */ diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c index 5eb2747122..1cfd02b230 100644 --- a/arch/arm/cpu/arm926ejs/mx25/timer.c +++ b/arch/arm/cpu/arm926ejs/mx25/timer.c @@ -15,7 +15,7 @@ * * (C) Copyright 2009 DENX Software Engineering * Author: John Rigby <jrigby@gmail.com> - * Add support for MX25 + * Add support for MX25 * * See file CREDITS for list of people who contributed to this * project. @@ -43,8 +43,8 @@ DECLARE_GLOBAL_DATA_PTR; -#define timestamp gd->tbl -#define lastinc gd->lastinc +#define timestamp (gd->tbl) +#define lastinc (gd->lastinc) /* * "time" is measured in 1 / CONFIG_SYS_HZ seconds, @@ -121,7 +121,7 @@ int timer_init(void) return 0; } -unsigned long long get_ticks (void) +unsigned long long get_ticks(void) { struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE; ulong now = readl(&gpt->counter); /* current tick value */ @@ -140,7 +140,7 @@ unsigned long long get_ticks (void) return timestamp; } -ulong get_timer_masked (void) +ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in @@ -151,13 +151,13 @@ ulong get_timer_masked (void) return tick_to_time(get_ticks()); } -ulong get_timer (ulong base) +ulong get_timer(ulong base) { - return get_timer_masked () - base; + return get_timer_masked() - base; } /* delay x useconds AND preserve advance timstamp value */ -void __udelay (unsigned long usec) +void __udelay(unsigned long usec) { unsigned long long tmp; ulong tmo; diff --git a/arch/arm/cpu/arm926ejs/mx27/reset.c b/arch/arm/cpu/arm926ejs/mx27/reset.c index 6c54eafd37..cc0a33ed55 100644 --- a/arch/arm/cpu/arm926ejs/mx27/reset.c +++ b/arch/arm/cpu/arm926ejs/mx27/reset.c @@ -39,7 +39,7 @@ /* * Reset the cpu by setting up the watchdog timer and let it time out */ -void reset_cpu (ulong ignored) +void reset_cpu(ulong ignored) { struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; /* Disable watchdog and set Time-Out field to 0 */ diff --git a/arch/arm/cpu/arm926ejs/mx27/timer.c b/arch/arm/cpu/arm926ejs/mx27/timer.c index df76d16810..5af935976e 100644 --- a/arch/arm/cpu/arm926ejs/mx27/timer.c +++ b/arch/arm/cpu/arm926ejs/mx27/timer.c @@ -45,8 +45,8 @@ DECLARE_GLOBAL_DATA_PTR; -#define timestamp gd->tbl -#define lastinc gd->lastinc +#define timestamp (gd->tbl) +#define lastinc (gd->lastinc) /* * "time" is measured in 1 / CONFIG_SYS_HZ seconds, @@ -124,7 +124,7 @@ int timer_init(void) return 0; } -unsigned long long get_ticks (void) +unsigned long long get_ticks(void) { struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE; ulong now = readl(®s->gpt_tcn); /* current tick value */ @@ -143,7 +143,7 @@ unsigned long long get_ticks (void) return timestamp; } -ulong get_timer_masked (void) +ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in @@ -154,13 +154,13 @@ ulong get_timer_masked (void) return tick_to_time(get_ticks()); } -ulong get_timer (ulong base) +ulong get_timer(ulong base) { - return get_timer_masked () - base; + return get_timer_masked() - base; } /* delay x useconds AND preserve advance timstamp value */ -void __udelay (unsigned long usec) +void __udelay(unsigned long usec) { unsigned long long tmp; ulong tmo; diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index 05bd45c3f6..792b11dfc5 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -28,8 +28,9 @@ #include <common.h> #include <netdev.h> #include <asm/cache.h> +#include <asm/io.h> #include <u-boot/md5.h> -#include <asm/arch/orion5x.h> +#include <asm/arch/cpu.h> #include <hush.h> #define BUFLEN 16 diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c index 5cc31a99f1..c0f7ef157f 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/dram.c +++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c @@ -27,7 +27,7 @@ #include <common.h> #include <config.h> -#include <asm/arch/orion5x.h> +#include <asm/arch/cpu.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/cpu/arm926ejs/orion5x/timer.c index 17df68f86a..e39ecc245b 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/timer.c +++ b/arch/arm/cpu/arm926ejs/orion5x/timer.c @@ -25,7 +25,7 @@ */ #include <common.h> -#include <asm/arch/orion5x.h> +#include <asm/io.h> #define UBOOT_CNTR 0 /* counter to use for uboot timer */ diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c index 8b2eafa40b..db9b348ad3 100644 --- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c +++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c @@ -23,8 +23,8 @@ */ #include <common.h> +#include <asm/arch/cpu.h> #include <asm/arch/pantheon.h> -#include <asm/io.h> #define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1)) #define SET_MRVL_ID (1<<8) @@ -42,6 +42,9 @@ int arch_cpu_init(void) struct panthmpmu_registers *mpmu = (struct panthmpmu_registers*) PANTHEON_MPMU_BASE; + struct panthapmu_registers *apmu = + (struct panthapmu_registers *) PANTHEON_APMU_BASE; + /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */ val = readl(&cpuregs->cpu_conf); val = val | SET_MRVL_ID; @@ -65,6 +68,14 @@ int arch_cpu_init(void) writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi); #endif +#ifdef CONFIG_MV_SDHCI + /* Enable mmc clock */ + writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST, + &apmu->sd1); + writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST, + &apmu->sd3); +#endif + icache_enable(); return 0; diff --git a/arch/arm/cpu/arm926ejs/pantheon/dram.c b/arch/arm/cpu/arm926ejs/pantheon/dram.c index bbca7eef16..a3d719e5cf 100644 --- a/arch/arm/cpu/arm926ejs/pantheon/dram.c +++ b/arch/arm/cpu/arm926ejs/pantheon/dram.c @@ -23,6 +23,7 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/pantheon.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c index c71162a8be..17045b1c2f 100644 --- a/arch/arm/cpu/arm926ejs/pantheon/timer.c +++ b/arch/arm/cpu/arm926ejs/pantheon/timer.c @@ -23,6 +23,7 @@ */ #include <common.h> +#include <asm/arch/cpu.h> #include <asm/arch/pantheon.h> /* |