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-rw-r--r--arch/arm/cpu/arm926ejs/davinci/Makefile2
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/cpu.c14
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/et1011c.c55
-rw-r--r--arch/arm/cpu/arm926ejs/kirkwood/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/mb86r0x/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/mx25/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/mx27/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/omap/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/orion5x/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/spear/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/start.S2
-rw-r--r--arch/arm/cpu/arm926ejs/versatile/timer.c6
12 files changed, 100 insertions, 21 deletions
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
index 4eb1d876eaf..3183e6a6567 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -32,7 +32,7 @@ COBJS-$(CONFIG_SOC_DM355) += dm355.o
COBJS-$(CONFIG_SOC_DM365) += dm365.o
COBJS-$(CONFIG_SOC_DM644X) += dm644x.o
COBJS-$(CONFIG_SOC_DM646X) += dm646x.o
-COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o
+COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o
SOBJS = reset.o
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index fc3551c3023..8b57205ea8d 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -54,9 +54,9 @@
#define DDR_PLLDIV PLLC_PLLDIV2
#endif
-#ifdef CONFIG_SOC_DM6447
-#define ARM_PLLDIV PLLC_PLLDIV2
+#ifdef CONFIG_SOC_DM646X
#define DSP_PLLDIV PLLC_PLLDIV1
+#define ARM_PLLDIV PLLC_PLLDIV2
#define DDR_PLLDIV PLLC_PLLDIV1
#endif
@@ -145,7 +145,11 @@ static inline unsigned pll_postdiv(volatile void *pllbase)
static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
{
volatile void *pllbase = (volatile void *) pll_addr;
+#ifdef CONFIG_SOC_DM646X
+ unsigned base = CFG_REFCLK_FREQ / 1000;
+#else
unsigned base = CONFIG_SYS_HZ_CLOCK / 1000;
+#endif
/* the PLL might be bypassed */
if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
@@ -176,6 +180,12 @@ int print_cpuinfo(void)
return 0;
}
+#ifdef DAVINCI_DM6467EVM
+unsigned int davinci_arm_clk_get()
+{
+ return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
+}
+#endif
#endif
/*
diff --git a/arch/arm/cpu/arm926ejs/davinci/et1011c.c b/arch/arm/cpu/arm926ejs/davinci/et1011c.c
new file mode 100644
index 00000000000..da073457a30
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/davinci/et1011c.c
@@ -0,0 +1,55 @@
+/*
+ * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <miiphy.h>
+#include <asm/arch/emac_defs.h>
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+#ifdef CONFIG_CMD_NET
+
+/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
+
+#define MII_PHY_CONFIG_REG 22
+
+/* PHY Config bits */
+#define PHY_SYS_CLK_EN (1 << 4)
+
+int et1011c_get_link_speed(int phy_addr)
+{
+ u_int16_t data;
+
+ if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
+ davinci_eth_phy_read(EMAC_MDIO_PHY_NUM,
+ MII_PHY_CONFIG_REG, &data);
+ /* Enable 125MHz clock sourced from PHY */
+ davinci_eth_phy_write(EMAC_MDIO_PHY_NUM,
+ MII_PHY_CONFIG_REG,
+ data | PHY_SYS_CLK_EN);
+ return (1);
+ }
+ return (0);
+}
+
+#endif /* CONFIG_CMD_NET */
+
+#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/timer.c b/arch/arm/cpu/arm926ejs/kirkwood/timer.c
index 2ec6a93807e..3e803296084 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/timer.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/timer.c
@@ -83,8 +83,10 @@ struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
#define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \
(CONFIG_SYS_TCLK / 1000))
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
void reset_timer_masked(void)
{
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
index 9175b71d16a..6966b0d190d 100644
--- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
+++ b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
@@ -33,8 +33,10 @@
#define TIMER_LOAD_VAL 0xffffffff
#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256)
-static unsigned long long timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
static inline unsigned long long tick_to_time(unsigned long long tick)
{
diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c
index 11d41a8bf9f..14f0c2dc73b 100644
--- a/arch/arm/cpu/arm926ejs/mx25/timer.c
+++ b/arch/arm/cpu/arm926ejs/mx25/timer.c
@@ -41,8 +41,10 @@
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-static ulong timestamp;
-static ulong lastinc;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastinc gd->lastinc
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
diff --git a/arch/arm/cpu/arm926ejs/mx27/timer.c b/arch/arm/cpu/arm926ejs/mx27/timer.c
index 8f1d47bba77..5c1cf014f05 100644
--- a/arch/arm/cpu/arm926ejs/mx27/timer.c
+++ b/arch/arm/cpu/arm926ejs/mx27/timer.c
@@ -43,8 +43,10 @@
#define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
-static ulong timestamp;
-static ulong lastinc;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastinc gd->lastinc
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
diff --git a/arch/arm/cpu/arm926ejs/omap/timer.c b/arch/arm/cpu/arm926ejs/omap/timer.c
index 7d4b6e602e4..88a0ee677ea 100644
--- a/arch/arm/cpu/arm926ejs/omap/timer.c
+++ b/arch/arm/cpu/arm926ejs/omap/timer.c
@@ -42,8 +42,10 @@
/* macro to read the 32 bit timer */
#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8))
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
int timer_init (void)
{
diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/cpu/arm926ejs/orion5x/timer.c
index 089ef47b371..bbab2269dda 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/timer.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/timer.c
@@ -90,8 +90,10 @@ static inline ulong read_timer(void)
/ (CONFIG_SYS_TCLK / 1000);
}
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
void reset_timer_masked(void)
{
diff --git a/arch/arm/cpu/arm926ejs/spear/timer.c b/arch/arm/cpu/arm926ejs/spear/timer.c
index 06858b4a13b..66cf4de8171 100644
--- a/arch/arm/cpu/arm926ejs/spear/timer.c
+++ b/arch/arm/cpu/arm926ejs/spear/timer.c
@@ -36,8 +36,10 @@ static struct gpt_regs *const gpt_regs_p =
static struct misc_regs *const misc_regs_p =
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
int timer_init(void)
{
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 55192521b7f..eb93ac9db7d 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -201,7 +201,6 @@ stack_setup:
cmp r0, r6
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy loop */
- ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
@@ -256,7 +255,6 @@ clear_bss:
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
diff --git a/arch/arm/cpu/arm926ejs/versatile/timer.c b/arch/arm/cpu/arm926ejs/versatile/timer.c
index 81d67490db8..2e243b196eb 100644
--- a/arch/arm/cpu/arm926ejs/versatile/timer.c
+++ b/arch/arm/cpu/arm926ejs/versatile/timer.c
@@ -42,8 +42,10 @@
/* macro to read the 32 bit timer */
#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->tbl
+#define lastdec gd->lastinc
#define TIMER_ENABLE (1 << 7)
#define TIMER_MODE_MSK (1 << 6)
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-26 22:44:05 +0000