diff options
| -rw-r--r-- | arch/arm/Kconfig | 6 | ||||
| -rw-r--r-- | board/compulab/cm_t43/Kconfig | 15 | ||||
| -rw-r--r-- | board/compulab/cm_t43/MAINTAINERS | 6 | ||||
| -rw-r--r-- | board/compulab/cm_t43/Makefile | 9 | ||||
| -rw-r--r-- | board/compulab/cm_t43/board.c | 272 | ||||
| -rw-r--r-- | board/compulab/cm_t43/board.h | 12 | ||||
| -rw-r--r-- | board/compulab/cm_t43/mux.c | 143 | ||||
| -rw-r--r-- | configs/cm_t43_defconfig | 10 | ||||
| -rw-r--r-- | include/configs/cm_t43.h | 182 |
9 files changed, 655 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e9a30b6b27..bd18e0aa42 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -643,6 +643,11 @@ config ARCH_SOCFPGA select DM_SPI_FLASH select DM_SPI +config TARGET_CM_T43 + bool "Support cm_t43" + select CPU_V7 + select SUPPORT_SPL + config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs" select CMD_USB @@ -902,6 +907,7 @@ source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" source "board/cirrus/edb93xx/Kconfig" source "board/compulab/cm_t335/Kconfig" +source "board/compulab/cm_t43/Kconfig" source "board/compulab/cm_fx6/Kconfig" source "board/congatec/cgtqmx6eval/Kconfig" source "board/creative/xfi3/Kconfig" diff --git a/board/compulab/cm_t43/Kconfig b/board/compulab/cm_t43/Kconfig new file mode 100644 index 0000000000..a19188975e --- /dev/null +++ b/board/compulab/cm_t43/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CM_T43 + +config SYS_BOARD + default "cm_t43" + +config SYS_VENDOR + default "compulab" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "cm_t43" + +endif diff --git a/board/compulab/cm_t43/MAINTAINERS b/board/compulab/cm_t43/MAINTAINERS new file mode 100644 index 0000000000..951c370dd7 --- /dev/null +++ b/board/compulab/cm_t43/MAINTAINERS @@ -0,0 +1,6 @@ +CM_T43 BOARD +M: Nikita Kiryanov <nikita@compulab.co.il> +S: Maintained +F: board/compulab/cm_t43/ +F: include/configs/cm_t43.h +F: configs/cm_t43_defconfig diff --git a/board/compulab/cm_t43/Makefile b/board/compulab/cm_t43/Makefile new file mode 100644 index 0000000000..399368920d --- /dev/null +++ b/board/compulab/cm_t43/Makefile @@ -0,0 +1,9 @@ +# +# Makefile +# +# Copyright (C) 2015 Compulab, Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += board.o mux.o diff --git a/board/compulab/cm_t43/board.c b/board/compulab/cm_t43/board.c new file mode 100644 index 0000000000..4272c45feb --- /dev/null +++ b/board/compulab/cm_t43/board.c @@ -0,0 +1,272 @@ +/* + * Copyright (C) 2015 Compulab, Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mux.h> +#include <asm/arch/ddr_defs.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/emif.h> +#include <power/pmic.h> +#include <power/tps65218.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + +const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 }; +const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 }; +const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 }; +const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 }; + +const struct ctrl_ioregs ioregs_ddr3 = { + .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0x0143, +}; + +/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ +struct emif_regs ddr3_emif_regs = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000066, + .emif_ddr_ext_phy_ctrl_3 = 0x00000091, + .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, + .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +const u32 ext_phy_ctrl_const_base_ddr3[] = { + 0x00000000, + 0x00000044, + 0x00000044, + 0x00000046, + 0x00000046, + 0x00000000, + 0x00000059, + 0x00000077, + 0x00000093, + 0x000000A8, + 0x00000000, + 0x00000019, + 0x00000037, + 0x00000053, + 0x00000068, + 0x00000000, + 0x0, + 0x0, + 0x40000000, + 0x08102040 +}; + +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ + *regs = ext_phy_ctrl_const_base_ddr3; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +const struct dpll_params *get_dpll_mpu_params(void) +{ + return &dpll_mpu; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + return &dpll_core; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + return &dpll_per; +} + +static void enable_vtt_regulator(void) +{ + u32 temp; + + writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); + writel(GPIO_SETDATAOUT(7), AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); + temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); + temp = temp & ~(GPIO_OE_ENABLE(7)); + writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); +} + +void sdram_init(void) +{ + unsigned long ram_size; + + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); + ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + if (ram_size == 0x80000000 || + ram_size == 0x40000000 || + ram_size == 0x20000000) + return; + + ddr3_emif_regs.sdram_config = 0x638453B2; + config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); + ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + if (ram_size == 0x08000000) + return; + + hang(); +} +#endif + +/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + + power_tps65218_init(I2C_PMIC); + p = pmic_get("TPS65218_PMIC"); + if (p && !pmic_probe(p)) + puts("PMIC: TPS65218\n"); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + set_i2c_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + i2c_probe(TPS65218_CHIP_PM); + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW + +static void cpsw_control(int enabled) +{ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_RGMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + .phy_if = PHY_INTERFACE_MODE_RGMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 2, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#define GPIO_PHY1_RST 170 +#define GPIO_PHY2_RST 168 + +int board_phy_config(struct phy_device *phydev) +{ + unsigned short val; + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + if (phydev->drv->config) + return phydev->drv->config(phydev); + + return 0; +} + +static void board_phy_init(void) +{ + set_mdio_pin_mux(); + writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */ + writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */ + writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */ + + /* For revision A */ + writel(0x2000009, 0x44df2e6c); + writel(0x38a, 0x44df2e70); + + mdelay(10); + + gpio_request(GPIO_PHY1_RST, "phy1_rst"); + gpio_request(GPIO_PHY2_RST, "phy2_rst"); + gpio_direction_output(GPIO_PHY1_RST, 0); + gpio_direction_output(GPIO_PHY2_RST, 0); + mdelay(2); + + gpio_set_value(GPIO_PHY1_RST, 1); + gpio_set_value(GPIO_PHY2_RST, 1); + mdelay(2); +} + +int board_eth_init(bd_t *bis) +{ + int rv; + + set_rgmii_pin_mux(); + writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); + board_phy_init(); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + + return rv; +} +#endif diff --git a/board/compulab/cm_t43/board.h b/board/compulab/cm_t43/board.h new file mode 100644 index 0000000000..b585db03ba --- /dev/null +++ b/board/compulab/cm_t43/board.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2015 Compulab, Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +void set_i2c_pin_mux(void); +void set_mdio_pin_mux(void); +void set_rgmii_pin_mux(void); +#endif diff --git a/board/compulab/cm_t43/mux.c b/board/compulab/cm_t43/mux.c new file mode 100644 index 0000000000..d4bf4b25c7 --- /dev/null +++ b/board/compulab/cm_t43/mux.c @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2015 Compulab, Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mux.h> +#include "board.h" + +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, + {OFFSET(mii1_txd3), MODE(2)}, + {OFFSET(mii1_txd2), MODE(2)}, + {OFFSET(mii1_txd1), MODE(2)}, + {OFFSET(mii1_txd0), MODE(2)}, + {OFFSET(mii1_txclk), MODE(2)}, + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE | PULLDOWN_EN}, + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE | PULLDOWN_EN}, + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE | PULLDOWN_EN}, + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE | PULLDOWN_EN}, + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE | PULLDOWN_EN}, + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE | PULLDOWN_EN}, + {-1}, +}; + +static struct module_pin_mux rgmii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(2)}, /* txen */ + {OFFSET(gpmc_a2), MODE(2)}, /* txd3 */ + {OFFSET(gpmc_a3), MODE(2)}, /* txd2 */ + {OFFSET(gpmc_a4), MODE(2)}, /* txd1 */ + {OFFSET(gpmc_a5), MODE(2)}, /* txd0 */ + {OFFSET(gpmc_a6), MODE(2)}, /* txclk */ + {OFFSET(gpmc_a1), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxvd */ + {OFFSET(gpmc_a7), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxclk */ + {OFFSET(gpmc_a8), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd3 */ + {OFFSET(gpmc_a9), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd2 */ + {OFFSET(gpmc_a10), MODE(2) | RXACTIVE | PULLDOWN_EN}, /* rxd1 */ + {OFFSET(gpmc_a11), MODE(2) | RXACTIVE | PULLUP_EN}, /* rxd0 */ + {-1}, +}; + +static struct module_pin_mux mdio_pin_mux[] = { + {OFFSET(mdio_data), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux i2c_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(spi2_sclk), (MODE(1) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(spi2_cs0), (MODE(1) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(gpmc_wpn), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, + {-1}, +}; + +static struct module_pin_mux emmc_pin_mux[] = { + {OFFSET(gpmc_csn1), (MODE(2) | PULLUDDIS | RXACTIVE)}, /* EMMC_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_CMD */ + {OFFSET(gpmc_ad8), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT0 */ + {OFFSET(gpmc_ad9), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT1 */ + {OFFSET(gpmc_ad10), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT2 */ + {OFFSET(gpmc_ad11), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT3 */ + {OFFSET(gpmc_ad12), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT4 */ + {OFFSET(gpmc_ad13), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT5 */ + {OFFSET(gpmc_ad14), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT6 */ + {OFFSET(gpmc_ad15), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* EMMC_DAT7 */ + {-1}, +}; + +static struct module_pin_mux spi_flash_pin_mux[] = { + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN)}, + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN)}, + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, + {-1}, +}; + +void set_uart_mux_conf(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void set_mdio_pin_mux(void) +{ + configure_module_pin_mux(mdio_pin_mux); +} + +void set_rgmii_pin_mux(void) +{ + configure_module_pin_mux(rgmii1_pin_mux); + configure_module_pin_mux(rgmii2_pin_mux); +} + +void set_mux_conf_regs(void) +{ + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(emmc_pin_mux); + configure_module_pin_mux(i2c_pin_mux); + configure_module_pin_mux(spi_flash_pin_mux); + configure_module_pin_mux(nand_pin_mux); +} + +void set_i2c_pin_mux(void) +{ + configure_module_pin_mux(i2c_pin_mux); +} diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig new file mode 100644 index 0000000000..19ac18a7f2 --- /dev/null +++ b/configs/cm_t43_defconfig @@ -0,0 +1,10 @@ +CONFIG_ARM=y +CONFIG_TARGET_CM_T43=y +CONFIG_SPL=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_NFS is not set +CONFIG_DM=y +CONFIG_DM_GPIO=y diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h new file mode 100644 index 0000000000..c4d3b94ee5 --- /dev/null +++ b/include/configs/cm_t43.h @@ -0,0 +1,182 @@ +/* + * cm_t43.h + * + * Copyright (C) 2015 Compulab, Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_CM_T43_H +#define __CONFIG_CM_T43_H + +#define CONFIG_AM43XX +#define CONFIG_CM_T43 +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ + +#include <asm/arch/omap.h> + +/* Serial support */ +#define CONFIG_OMAP_SERIAL +#define CONFIG_DM_SERIAL +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK 48000000 +#define CONFIG_SYS_NS16550_COM1 0x44e09000 + +/* NAND support */ +#define CONFIG_NAND +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +/* CPSW Ethernet support */ +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_NET_MULTI +#define CONFIG_PHY_GIGE +#define CONFIG_PHY_ATHEROS +#define CONFIG_PHYLIB +#define CONFIG_SYS_RX_ETH_BUFFER 64 + +/* USB support */ +#define CONFIG_USB_HOST +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_OMAP +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_OMAP_USB_PHY +#define CONFIG_AM437X_USB2PHY2_HOST + +/* SPI Flash support */ +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SPI_FLASH_EON +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_TI_SPI_MMAP +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_SPEED 48000000 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 + +/* Power */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_TPS65218 + +/* Enabling L2 Cache */ +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_HSMMC2_8BIT + +#include <configs/ti_armv7_omap.h> +#undef CONFIG_SPL_OS_BOOT +#undef CONFIG_SPL_GPIO_SUPPORT +#undef CONFIG_SPL_NAND_SUPPORT +#undef CONFIG_SPL_BOARD_INIT +#undef CONFIG_BOOTDELAY +#include <config_distro_defaults.h> +#define CONFIG_ZERO_BOOTDELAY_CHECK +#undef CONFIG_CMD_IMLS + +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SPI_MAX_HZ 48000000 + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x81200000\0" \ + "bootm_size=0x8000000\0" \ + "autoload=no\0" \ + "console=ttyO0,115200n8\0" \ + "fdtfile=am437x-sb-som-t43.dtb\0" \ + "kernel=zImage-cm-t43\0" \ + "bootscr=bootscr.img\0" \ + "emmcroot=/dev/mmcblk0p2 rw\0" \ + "emmcrootfstype=ext4 rootwait\0" \ + "emmcargs=setenv bootargs console=${console} " \ + "root=${emmcroot} " \ + "rootfstype=${emmcrootfstype}\0" \ + "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "emmcboot=echo Booting from emmc ... && " \ + "run emmcargs && " \ + "load mmc 1 ${loadaddr} ${kernel} && " \ + "load mmc 1 ${fdtaddr} ${fdtfile} && " \ + "bootz ${loadaddr} - ${fdtaddr}\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev 0; " \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "fi; " \ + "fi; " \ + "mmc dev 1; " \ + "if mmc rescan; then " \ + "run emmcboot; " \ + "fi;" + + +#define CONFIG_CONS_INDEX 1 + +/* SPL defines. */ +#define CONFIG_SPL_TEXT_BASE 0x40300350 +#define CONFIG_SPL_MAX_SIZE (64 * 1024) +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024) +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD + +#endif /* __CONFIG_CM_T43_H */ |