diff options
| -rw-r--r-- | MAINTAINERS | 2 | ||||
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/Makefile | 1 | ||||
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/cpu.c | 16 | ||||
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/iop480_uart.c | 254 | ||||
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/speed.c | 17 | ||||
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/start.S | 108 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/cache.h | 2 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/ppc405.h | 4 | ||||
| -rw-r--r-- | boards.cfg | 2 | ||||
| -rw-r--r-- | include/common.h | 2 | ||||
| -rw-r--r-- | include/configs/ADCIOP.h | 203 | ||||
| -rw-r--r-- | include/configs/DASA_SIM.h | 194 | ||||
| -rw-r--r-- | include/vxworks.h | 2 |
13 files changed, 3 insertions, 804 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index e76f71cf50b..9f3e4bacce7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -179,7 +179,6 @@ Thomas Frieden <ThomasF@hyperion-entertainment.com> Matthias Fuchs <matthias.fuchs@esd-electronics.com> - ADCIOP IOP480 (PPC401) APC405 PPC405GP AR405 PPC405GP ASH405 PPC405EP @@ -190,7 +189,6 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com> CPCI405AB PPC405GP CPCI405DT PPC405GP CPCIISER4 PPC405GP - DASA_SIM IOP480 (PPC401) DP405 PPC405EP DU405 PPC405GP DU440 PPC440EPx diff --git a/arch/powerpc/cpu/ppc4xx/Makefile b/arch/powerpc/cpu/ppc4xx/Makefile index 3d622550390..8da2f86e593 100644 --- a/arch/powerpc/cpu/ppc4xx/Makefile +++ b/arch/powerpc/cpu/ppc4xx/Makefile @@ -53,7 +53,6 @@ COBJS += ecc.o COBJS-$(CONFIG_CMD_ECCTEST) += cmd_ecctest.o COBJS += fdt.o COBJS += interrupts.o -COBJS += iop480_uart.o COBJS-$(CONFIG_CMD_REGINFO) += reginfo.o COBJS += sdram.o COBJS += speed.o diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c index 67f1fff7efe..60aba8cefe4 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu.c +++ b/arch/powerpc/cpu/ppc4xx/cpu.c @@ -79,7 +79,7 @@ static int pci_async_enabled(void) #endif #endif /* CONFIG_PCI */ -#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \ +#if defined(CONFIG_PCI) && \ !defined(CONFIG_405) && !defined(CONFIG_405EX) int pci_arbiter_enabled(void) { @@ -303,7 +303,6 @@ int checkcpu (void) u32 reg; #endif -#if !defined(CONFIG_IOP480) char addstr[64] = ""; sys_info_t sys_info; int cpu_num; @@ -671,14 +670,6 @@ int checkcpu (void) printf (" 16 kB I-Cache %d kB D-Cache", ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); #endif -#endif /* !defined(CONFIG_IOP480) */ - -#if defined(CONFIG_IOP480) - printf ("PLX IOP480 (PVR=%08x)", pvr); - printf (" at %s MHz:", strmhz(buf, clock)); - printf (" %u kB I-Cache", 4); - printf (" %u kB D-Cache", 2); -#endif #endif /* !defined(CONFIG_405) */ @@ -723,15 +714,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) */ unsigned long get_tbclk (void) { -#if !defined(CONFIG_IOP480) sys_info_t sys_info; get_sys_info(&sys_info); return (sys_info.freqProcessor); -#else - return (66000000); -#endif - } diff --git a/arch/powerpc/cpu/ppc4xx/iop480_uart.c b/arch/powerpc/cpu/ppc4xx/iop480_uart.c deleted file mode 100644 index 94739848904..00000000000 --- a/arch/powerpc/cpu/ppc4xx/iop480_uart.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <commproc.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <watchdog.h> -#include <serial.h> -#include <linux/compiler.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_IOP480 - -#define SPU_BASE 0x40000000 - -#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */ -#define spu_LineStat_w 0x04 /* Line Status Register (Set) */ -#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */ -#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */ -#define spu_BRateDivh 0x10 /* Baud rate divisor high */ -#define spu_BRateDivl 0x14 /* Baud rate divisor low */ -#define spu_CtlReg 0x18 /* Control Register */ -#define spu_RxCmd 0x1c /* Rx Command Register */ -#define spu_TxCmd 0x20 /* Tx Command Register */ -#define spu_RxBuff 0x24 /* Rx data buffer */ -#define spu_TxBuff 0x24 /* Tx data buffer */ - -/*-----------------------------------------------------------------------------+ - | Line Status Register. - +-----------------------------------------------------------------------------*/ -#define asyncLSRport1 0x40000000 -#define asyncLSRport1set 0x40000004 -#define asyncLSRDataReady 0x80 -#define asyncLSRFramingError 0x40 -#define asyncLSROverrunError 0x20 -#define asyncLSRParityError 0x10 -#define asyncLSRBreakInterrupt 0x08 -#define asyncLSRTxHoldEmpty 0x04 -#define asyncLSRTxShiftEmpty 0x02 - -/*-----------------------------------------------------------------------------+ - | Handshake Status Register. - +-----------------------------------------------------------------------------*/ -#define asyncHSRport1 0x40000008 -#define asyncHSRport1set 0x4000000c -#define asyncHSRDsr 0x80 -#define asyncLSRCts 0x40 - -/*-----------------------------------------------------------------------------+ - | Control Register. - +-----------------------------------------------------------------------------*/ -#define asyncCRport1 0x40000018 -#define asyncCRNormal 0x00 -#define asyncCRLoopback 0x40 -#define asyncCRAutoEcho 0x80 -#define asyncCRDtr 0x20 -#define asyncCRRts 0x10 -#define asyncCRWordLength7 0x00 -#define asyncCRWordLength8 0x08 -#define asyncCRParityDisable 0x00 -#define asyncCRParityEnable 0x04 -#define asyncCREvenParity 0x00 -#define asyncCROddParity 0x02 -#define asyncCRStopBitsOne 0x00 -#define asyncCRStopBitsTwo 0x01 -#define asyncCRDisableDtrRts 0x00 - -/*-----------------------------------------------------------------------------+ - | Receiver Command Register. - +-----------------------------------------------------------------------------*/ -#define asyncRCRport1 0x4000001c -#define asyncRCRDisable 0x00 -#define asyncRCREnable 0x80 -#define asyncRCRIntDisable 0x00 -#define asyncRCRIntEnabled 0x20 -#define asyncRCRDMACh2 0x40 -#define asyncRCRDMACh3 0x60 -#define asyncRCRErrorInt 0x10 -#define asyncRCRPauseEnable 0x08 - -/*-----------------------------------------------------------------------------+ - | Transmitter Command Register. - +-----------------------------------------------------------------------------*/ -#define asyncTCRport1 0x40000020 -#define asyncTCRDisable 0x00 -#define asyncTCREnable 0x80 -#define asyncTCRIntDisable 0x00 -#define asyncTCRIntEnabled 0x20 -#define asyncTCRDMACh2 0x40 -#define asyncTCRDMACh3 0x60 -#define asyncTCRTxEmpty 0x10 -#define asyncTCRErrorInt 0x08 -#define asyncTCRStopPause 0x04 -#define asyncTCRBreakGen 0x02 - -/*-----------------------------------------------------------------------------+ - | Miscellanies defines. - +-----------------------------------------------------------------------------*/ -#define asyncTxBufferport1 0x40000024 -#define asyncRxBufferport1 0x40000024 -#define asyncDLABLsbport1 0x40000014 -#define asyncDLABMsbport1 0x40000010 -#define asyncXOFFchar 0x13 -#define asyncXONchar 0x11 - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -static int iop480_serial_init(void) -{ - unsigned short br_reg; - - br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); - - /* - * Init onboard UART - */ - out_8((u8 *)SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */ - out_8((u8 *)SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */ - out_8((u8 *)SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ - out_8((u8 *)SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */ - out_8((u8 *)SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */ - out_8((u8 *)SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */ - out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ - in_8((u8 *)SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */ - - return (0); -} - -static void iop480_serial_setbrg(void) -{ - unsigned short br_reg; - - br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); - - out_8((u8 *)SPU_BASE + spu_BRateDivl, - (br_reg & 0x00ff)); /* Set baud rate divisor... */ - out_8((u8 *)SPU_BASE + spu_BRateDivh, - ((br_reg & 0xff00) >> 8)); /* ... */ -} - -static void iop480_serial_putc(const char c) -{ - if (c == '\n') - serial_putc ('\r'); - - /* load status from handshake register */ - if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00) - out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ - - out_8((u8 *)SPU_BASE + spu_TxBuff, c); /* Put char */ - - while ((in_8((u8 *)SPU_BASE + spu_LineStat_rc) & 04) != 04) { - if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00) - out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ - } -} - -static void iop480_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -static int iop480_serial_getc(void) -{ - unsigned char status = 0; - - while (1) { - status = in_8((u8 *)asyncLSRport1); - if ((status & asyncLSRDataReady) != 0x0) { - break; - } - if ((status & ( asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt )) != 0) { - (void) out_8((u8 *)asyncLSRport1, - asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt ); - } - } - return (0x000000ff & (int) in_8((u8 *)asyncRxBufferport1)); -} - -static int iop480_serial_tstc(void) -{ - unsigned char status; - - status = in_8((u8 *)asyncLSRport1); - if ((status & asyncLSRDataReady) != 0x0) { - return (1); - } - if ((status & ( asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt )) != 0) { - (void) out_8((u8 *)asyncLSRport1, - asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt); - } - return 0; -} - -static struct serial_device iop480_serial_drv = { - .name = "iop480_serial", - .start = iop480_serial_init, - .stop = NULL, - .setbrg = iop480_serial_setbrg, - .putc = iop480_serial_putc, - .puts = iop480_serial_puts, - .getc = iop480_serial_getc, - .tstc = iop480_serial_tstc, -}; - -void iop480_serial_initialize(void) -{ - serial_register(&iop480_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &iop480_serial_drv; -} -#endif /* CONFIG_IOP480 */ diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 09d6671d0d8..6156ac952fb 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -1190,22 +1190,12 @@ void get_sys_info (sys_info_t * sysInfo) int get_clocks (void) { -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_405EX) || defined(CONFIG_405) || \ - defined(CONFIG_440) sys_info_t sys_info; get_sys_info (&sys_info); gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqPLB; -#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */ - -#ifdef CONFIG_IOP480 - gd->cpu_clk = 66000000; - gd->bus_clk = 66000000; -#endif return (0); } @@ -1226,11 +1216,6 @@ ulong get_bus_freq (ulong dummy) get_sys_info (&sys_info); val = sys_info.freqPLB; - -#elif defined(CONFIG_IOP480) - - val = 66; - #else # error get_bus_freq() not implemented #endif @@ -1238,7 +1223,6 @@ ulong get_bus_freq (ulong dummy) return val; } -#if !defined(CONFIG_IOP480) ulong get_OPB_freq (void) { PPC4xx_SYS_INFO sys_info; @@ -1247,4 +1231,3 @@ ulong get_OPB_freq (void) return sys_info.freqOPB; } -#endif diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 3b0e3644a4c..7aef43b210d 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -806,114 +806,6 @@ _start: #endif /* CONFIG_440 */ /*****************************************************************************/ -#ifdef CONFIG_IOP480 - /*----------------------------------------------------------------------- */ - /* Set up some machine state registers. */ - /*----------------------------------------------------------------------- */ - addi r0,r0,0x0000 /* initialize r0 to zero */ - mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */ - mttcr r0 /* timer control register */ - mtexier r0 /* disable all interrupts */ - addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */ - ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */ - mtdbsr r4 /* clear/reset the dbsr */ - mtexisr r4 /* clear all pending interrupts */ - addis r4,r0,0x8000 - mtexier r4 /* enable critical exceptions */ - addis r4,r0,0x0000 /* assume 403GCX - enable core clk */ - ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */ - mtiocr r4 /* since bit not used) & DRC to latch */ - /* data bus on rising edge of CAS */ - /*----------------------------------------------------------------------- */ - /* Clear XER. */ - /*----------------------------------------------------------------------- */ - mtxer r0 - /*----------------------------------------------------------------------- */ - /* Invalidate i-cache and d-cache TAG arrays. */ - /*----------------------------------------------------------------------- */ - addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */ - addi r4,0,1024 /* 1/4 of I-cache */ -..cloop: - iccci 0,r3 - iccci r4,r3 - dccci 0,r3 - addic. r3,r3,-16 /* move back one cache line */ - bne ..cloop /* loop back to do rest until r3 = 0 */ - - /* */ - /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */ - /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */ - /* */ - - /* first copy IOP480 register base address into r3 */ - addis r3,0,0x5000 /* IOP480 register base address hi */ -/* ori r3,r3,0x0000 / IOP480 register base address lo */ - -#ifdef CONFIG_ADCIOP - /* use r4 as the working variable */ - /* turn on CS3 (LOCCTL.7) */ - lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ - andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */ - stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ -#endif - -#ifdef CONFIG_DASA_SIM - /* use r4 as the working variable */ - /* turn on MA17 (LOCCTL.7) */ - lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ - ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */ - stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ -#endif - - /* turn on MA16..13 (LCS0BRD.12 = 0) */ - lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ - andi. r4,r4,0xefff /* make bit 12 = 0 */ - stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ - - /* make sure above stores all comlete before going on */ - sync - - /* last thing, set local init status done bit (DEVINIT.31) */ - lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */ - oris r4,r4,0x8000 /* make bit 31 = 1 */ - stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */ - - /* clear all pending interrupts and disable all interrupts */ - li r4,-1 /* set p1 to 0xffffffff */ - stw r4,0x1b0(r3) /* clear all pending interrupts */ - stw r4,0x1b8(r3) /* clear all pending interrupts */ - li r4,0 /* set r4 to 0 */ - stw r4,0x1b4(r3) /* disable all interrupts */ - stw r4,0x1bc(r3) /* disable all interrupts */ - - /* make sure above stores all comlete before going on */ - sync - - /* Set-up icache cacheability. */ - lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h - ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l - mticcr r1 - isync - - /* Set-up dcache cacheability. */ - lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h - ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l - mtdccr r1 - - addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h - ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */ - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - GET_GOT /* initialize GOT access */ - - bl board_init_f /* run first part of init code (from Flash) */ - /* NOTREACHED - board_init_f() does not return */ - -#endif /* CONFIG_IOP480 */ - -/*****************************************************************************/ #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || defined(CONFIG_405) diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index e6b8f69b765..5f9c640aa2a 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -8,7 +8,7 @@ #include <asm/processor.h> /* bytes per L1 cache line */ -#if defined(CONFIG_8xx) || defined(CONFIG_IOP480) +#if defined(CONFIG_8xx) #define L1_CACHE_SHIFT 4 #elif defined(CONFIG_PPC64BRIDGE) #define L1_CACHE_SHIFT 7 diff --git a/arch/powerpc/include/asm/ppc405.h b/arch/powerpc/include/asm/ppc405.h index 14a7a379fd1..892848aacf1 100644 --- a/arch/powerpc/include/asm/ppc405.h +++ b/arch/powerpc/include/asm/ppc405.h @@ -28,11 +28,7 @@ #define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) #define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) -#ifndef CONFIG_IOP480 #define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ -#else -#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480(403)*/ -#endif /* DCR registers */ #define PLB0_ACR 0x0087 diff --git a/boards.cfg b/boards.cfg index 70d63a2df5f..6abf6860b69 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1015,7 +1015,6 @@ PPChameleonEVB_HI_25 powerpc ppc4xx PPChameleonEVB dave PPChameleonEVB_HI_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33 PPChameleonEVB_ME_25 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 PPChameleonEVB_ME_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 -ADCIOP powerpc ppc4xx adciop esd APC405 powerpc ppc4xx apc405 esd AR405 powerpc ppc4xx ar405 esd ASH405 powerpc ppc4xx ash405 esd @@ -1027,7 +1026,6 @@ CPCI4052 powerpc ppc4xx cpci405 esd CPCI405AB powerpc ppc4xx cpci405 esd CPCI405DT powerpc ppc4xx cpci405 esd CPCIISER4 powerpc ppc4xx cpciiser4 esd -DASA_SIM powerpc ppc4xx dasa_sim esd DP405 powerpc ppc4xx dp405 esd DU405 powerpc ppc4xx du405 esd DU440 powerpc ppc4xx du440 esd diff --git a/include/common.h b/include/common.h index 7205677b8db..fb337791a26 100644 --- a/include/common.h +++ b/include/common.h @@ -659,7 +659,7 @@ static inline ulong get_ddr_freq(ulong dummy) } #endif -#if defined(CONFIG_4xx) || defined(CONFIG_IOP480) +#if defined(CONFIG_4xx) # if defined(CONFIG_440) # if defined(CONFIG_440SPE) unsigned long determine_sysper(void); diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h deleted file mode 100644 index 5cd8eef3100..00000000000 --- a/include/configs/ADCIOP.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_IOP480 1 /* This is a IOP480 CPU */ -#define CONFIG_ADCIOP 1 /* ...on a ADCIOP board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFD0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_CPUCLOCK 66 -#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK) - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ -#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ - -#undef CONFIG_BOOTARGS - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_PHY_ADDR 0 /* PHY address */ - -#define CONFIG_IPADDR 10.0.18.222 -#define CONFIG_SERVERIP 10.0.18.190 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_ASKENV - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0002 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0000 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0004 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 1 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0x10000000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_ENV_SIZE 0x0400 /* Size of Environment vars */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ -#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x7800) /* VxWorks eth-addr*/ - -#else /* Use FLASH for environment variables */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ - -#define CONFIG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */ - -#endif - -/*----------------------------------------------------------------------- - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_TULIP - -#define CONFIG_SYS_ETH_DEV_FN 0x0000 -#define CONFIG_SYS_ETH_IOBASE 0x0fff0000 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFE00000 /* FLASH bank #1 */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h deleted file mode 100644 index 6fe7fd33c0e..00000000000 --- a/include/configs/DASA_SIM.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_IOP480 1 /* This is a IOP480 CPU */ -#define CONFIG_DASA_SIM 1 /* ...on a DASA_SIM board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 -#define CONFIG_SYS_LDSCRIPT "board/esd/dasa_sim/u-boot.lds" - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_CPUCLOCK 66 -#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK) - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm ffe00000" /* autoboot command */ - -#undef CONFIG_BOOTARGS - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_IPADDR 10.0.18.222 -#define CONFIG_SERVERIP 10.0.18.190 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_BSP - - -#if 0 /* Does not appear to be used?! If it is used, needs to be fixed */ -#define CONFIG_SOFT_I2C /* Software I2C support enabled */ -#endif -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0002 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0000 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0004 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ - -#if 0 -#define CONFIG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */ -#else -#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ -#endif - -/*----------------------------------------------------------------------- - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP - - -#define CONFIG_TULIP - -#define CONFIG_SYS_ETH_DEV_FN 0x0000 -#define CONFIG_SYS_ETH_IOBASE 0x0fff0000 -#define CONFIG_SYS_PCI9054_DEV_FN 0x0800 -#define CONFIG_SYS_PCI9054_IOBASE 0x0eff0000 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ - -#endif /* __CONFIG_H */ diff --git a/include/vxworks.h b/include/vxworks.h index 917a9ff8567..736e3b5f900 100644 --- a/include/vxworks.h +++ b/include/vxworks.h @@ -39,8 +39,6 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); #ifndef CONFIG_SYS_VXWORKS_BOOT_DEVICE #if defined(CONFIG_4xx) #define CONFIG_SYS_VXWORKS_BOOT_DEVICE "emac(0,0)" -#elif defined(CONFIG_IOP480) -#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "dc(0,0)" #else #define CONFIG_SYS_VXWORKS_BOOT_DEVICE "eth(0,0)" #endif |