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-rw-r--r--README3
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c20
-rw-r--r--arch/arm/include/asm/global_data.h14
-rw-r--r--board/freescale/ls1043aqds/ddr.c15
-rw-r--r--board/freescale/ls1043ardb/ddr.c15
-rw-r--r--board/freescale/ls2080a/ddr.c15
-rw-r--r--board/freescale/ls2080aqds/ddr.c15
-rw-r--r--board/freescale/ls2080ardb/ddr.c15
-rw-r--r--cmd/bdinfo.c4
-rw-r--r--common/board_f.c2
-rw-r--r--include/asm-generic/global_data.h14
11 files changed, 69 insertions, 63 deletions
diff --git a/README b/README
index 26d5ad273ef..af37d4125f2 100644
--- a/README
+++ b/README
@@ -3766,10 +3766,11 @@ Configuration Settings:
You only need to set this if address zero isn't writeable
- CONFIG_SYS_MEM_RESERVE_SECURE
+ Only implemented for ARMv8 for now.
If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
is substracted from total RAM and won't be reported to OS.
This memory can be used as secure memory. A variable
- gd->secure_ram is used to track the location. In systems
+ gd->arch.secure_ram is used to track the location. In systems
the RAM base is not zero, or RAM is divided into banks,
this variable needs to be recalcuated to get the address.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 8062106e3e9..a397f5d7472 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -289,8 +289,8 @@ static inline int final_secure_ddr(u64 *level0_table,
* These tables are in DRAM. Sub tables are added to enable cache for
* QBMan and OCRAM.
*
- * Put the MMU table in secure memory if gd->secure_ram is valid.
- * OCRAM will be not used for this purpose so gd->secure_ram can't be 0.
+ * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
+ * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
*
* Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB.
* Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB.
@@ -321,13 +321,13 @@ static inline void final_mmu_setup(void)
if (el == 3) {
/*
- * Only use gd->secure_ram if the address is recalculated
+ * Only use gd->arch.secure_ram if the address is recalculated
* Align to 4KB for MMU table
*/
- if (gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED)
- level0_table = (u64 *)(gd->secure_ram & ~0xfff);
+ if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED)
+ level0_table = (u64 *)(gd->arch.secure_ram & ~0xfff);
else
- printf("MMU warning: gd->secure_ram is not maintained, disabled.\n");
+ printf("MMU warning: gd->arch.secure_ram is not maintained, disabled.\n");
}
#endif
level1_table0 = level0_table + 512;
@@ -374,7 +374,7 @@ static inline void final_mmu_setup(void)
}
/* Set the secure memory to secure in MMU */
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- if (el == 3 && gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
+ if (el == 3 && gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
#ifdef CONFIG_FSL_LSCH3
level2_table_secure = level2_table1 + 512;
#elif defined(CONFIG_FSL_LSCH2)
@@ -382,10 +382,10 @@ static inline void final_mmu_setup(void)
#endif
if (!final_secure_ddr(level0_table,
level2_table_secure,
- gd->secure_ram & ~0x3)) {
- gd->secure_ram |= MEM_RESERVE_SECURE_SECURED;
+ gd->arch.secure_ram & ~0x3)) {
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
debug("Now MMU table is in secured memory at 0x%llx\n",
- gd->secure_ram & ~0x3);
+ gd->arch.secure_ram & ~0x3);
} else {
printf("MMU warning: Failed to secure DDR\n");
}
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 77d2653e27a..2d76cd477d4 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -44,6 +44,20 @@ struct arch_global_data {
unsigned long tlb_emerg;
#endif
#endif
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#define MEM_RESERVE_SECURE_SECURED 0x1
+#define MEM_RESERVE_SECURE_MAINTAINED 0x2
+#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3)
+ /*
+ * Secure memory addr
+ * This variable needs maintenance if the RAM base is not zero,
+ * or if RAM splits into non-consecutive banks. It also has a
+ * flag indicating the secure memory is marked as secure by MMU.
+ * Flags used: 0x1 secured
+ * 0x2 maintained
+ */
+ phys_addr_t secure_ram;
+#endif
#ifdef CONFIG_OMAP_COMMON
u32 omap_boot_device;
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index 0fd835d74fb..d4540d0a9a0 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -128,7 +128,7 @@ phys_size_t initdram(int board_type)
void dram_init_banksize(void)
{
/*
- * gd->secure_ram tracks the location of secure memory.
+ * gd->arch.secure_ram tracks the location of secure memory.
* It was set as if the memory starts from 0.
* The address needs to add the offset of its bank.
*/
@@ -139,16 +139,17 @@ void dram_init_banksize(void)
gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->secure_ram = gd->bd->bi_dram[1].start +
- gd->secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+ gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+ gd->arch.secure_ram -
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif
} else {
gd->bd->bi_dram[0].size = gd->ram_size;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
- gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+ gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+ gd->arch.secure_ram;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif
}
}
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index 1e2fd2ed0c1..61b1cc4f30e 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -189,7 +189,7 @@ phys_size_t initdram(int board_type)
void dram_init_banksize(void)
{
/*
- * gd->secure_ram tracks the location of secure memory.
+ * gd->arch.secure_ram tracks the location of secure memory.
* It was set as if the memory starts from 0.
* The address needs to add the offset of its bank.
*/
@@ -200,16 +200,17 @@ void dram_init_banksize(void)
gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->secure_ram = gd->bd->bi_dram[1].start +
- gd->secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+ gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+ gd->arch.secure_ram -
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif
} else {
gd->bd->bi_dram[0].size = gd->ram_size;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
- gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+ gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+ gd->arch.secure_ram;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif
}
}
diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c
index 1827ddca695..e6130ec7093 100644
--- a/board/freescale/ls2080a/ddr.c
+++ b/board/freescale/ls2080a/ddr.c
@@ -177,7 +177,7 @@ void dram_init_banksize(void)
#endif
/*
- * gd->secure_ram tracks the location of secure memory.
+ * gd->arch.secure_ram tracks the location of secure memory.
* It was set as if the memory starts from 0.
* The address needs to add the offset of its bank.
*/
@@ -188,16 +188,17 @@ void dram_init_banksize(void)
gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->secure_ram = gd->bd->bi_dram[1].start +
- gd->secure_ram -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+ gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+ gd->arch.secure_ram -
+ CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif
} else {
gd->bd->bi_dram[0].size = gd->ram_size;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
- gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+ gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+ gd->arch.secure_ram;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif
}
diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c
index fcb03665bf9..9c6f477c7f4 100644
--- a/board/freescale/ls2080aqds/ddr.c
+++ b/board/freescale/ls2080aqds/ddr.c
@@ -177,7 +177,7 @@ void dram_init_banksize(void)
#endif
/*
- * gd->secure_ram tracks the location of secure memory.
+ * gd->arch.secure_ram tracks the location of secure memory.
* It was set as if the memory starts from 0.
* The address needs to add the offset of its bank.
*/
@@ -188,16 +188,17 @@ void dram_init_banksize(void)
gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->secure_ram = gd->bd->bi_dram[1].start +
- gd->secure_ram -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+ gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+ gd->arch.secure_ram -
+ CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif
} else {
gd->bd->bi_dram[0].size = gd->ram_size;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
- gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+ gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+ gd->arch.secure_ram;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif
}
diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c
index a04d21be130..ecd1e71ad8f 100644
--- a/board/freescale/ls2080ardb/ddr.c
+++ b/board/freescale/ls2080ardb/ddr.c
@@ -177,7 +177,7 @@ void dram_init_banksize(void)
#endif
/*
- * gd->secure_ram tracks the location of secure memory.
+ * gd->arch.secure_ram tracks the location of secure memory.
* It was set as if the memory starts from 0.
* The address needs to add the offset of its bank.
*/
@@ -188,16 +188,17 @@ void dram_init_banksize(void)
gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->secure_ram = gd->bd->bi_dram[1].start +
- gd->secure_ram -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+ gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+ gd->arch.secure_ram -
+ CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif
} else {
gd->bd->bi_dram[0].size = gd->ram_size;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
- gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+ gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+ gd->arch.secure_ram;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif
}
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 1c4bed96b5b..f2435ab7e52 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -385,9 +385,9 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
}
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- if (gd->secure_ram & MEM_RESERVE_SECURE_SECURED) {
+ if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) {
print_num("Secure ram",
- gd->secure_ram & MEM_RESERVE_SECURE_ADDR_MASK);
+ gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK);
}
#endif
#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
diff --git a/common/board_f.c b/common/board_f.c
index d405b5b407e..0fc96bd4c6c 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -339,7 +339,7 @@ static int setup_dest_addr(void)
* Record secure memory location. Need recalcuate if memory splits
* into banks, or the ram base is not zero.
*/
- gd->secure_ram = gd->ram_size;
+ gd->arch.secure_ram = gd->ram_size;
#endif
/*
* Subtract specified amount of memory to hide so that it won't
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 0abcbe4c0b3..a6d1d2ab3f4 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -55,20 +55,6 @@ typedef struct global_data {
unsigned long relocaddr; /* Start address of U-Boot in RAM */
phys_size_t ram_size; /* RAM size */
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-#define MEM_RESERVE_SECURE_SECURED 0x1
-#define MEM_RESERVE_SECURE_MAINTAINED 0x2
-#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3)
- /*
- * Secure memory addr
- * This variable needs maintenance if the RAM base is not zero,
- * or if RAM splits into non-consecutive banks. It also has a
- * flag indicating the secure memory is marked as secure by MMU.
- * Flags used: 0x1 secured
- * 0x2 maintained
- */
- phys_addr_t secure_ram;
-#endif
unsigned long mon_len; /* monitor len */
unsigned long irq_sp; /* irq stack pointer */
unsigned long start_addr_sp; /* start_addr_stackpointer */
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-05 18:41:07 +0000