diff options
| -rw-r--r-- | arch/riscv/cpu/cpu.c | 2 | ||||
| -rw-r--r-- | arch/riscv/lib/sifive_clint.c | 16 | ||||
| -rw-r--r-- | common/spl/spl_opensbi.c | 5 |
3 files changed, 13 insertions, 10 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index bbd6c15352..bfa2d4a426 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -107,7 +107,7 @@ int arch_cpu_init_dm(void) #endif } -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) ret = riscv_init_ipi(); if (ret) return ret; diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c index 78fc6c868d..b9a2c649cc 100644 --- a/arch/riscv/lib/sifive_clint.c +++ b/arch/riscv/lib/sifive_clint.c @@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR; int riscv_get_time(u64 *time) { + /* ensure timer register base has a sane value */ + riscv_init_ipi(); + *time = readq((void __iomem *)MTIME_REG(gd->arch.clint)); return 0; @@ -33,6 +36,9 @@ int riscv_get_time(u64 *time) int riscv_set_timecmp(int hart, u64 cmp) { + /* ensure timer register base has a sane value */ + riscv_init_ipi(); + writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); return 0; @@ -40,11 +46,13 @@ int riscv_set_timecmp(int hart, u64 cmp) int riscv_init_ipi(void) { - long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT); + if (!gd->arch.clint) { + long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT); - if (IS_ERR(ret)) - return PTR_ERR(ret); - gd->arch.clint = ret; + if (IS_ERR(ret)) + return PTR_ERR(ret); + gd->arch.clint = ret; + } return 0; } diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index 3440bc0294..14f335f75f 100644 --- a/common/spl/spl_opensbi.c +++ b/common/spl/spl_opensbi.c @@ -79,11 +79,6 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) invalidate_icache_all(); #ifdef CONFIG_SPL_SMP - /* Initialize the IPI before we use it */ - ret = riscv_init_ipi(); - if (ret) - hang(); - /* * Start OpenSBI on all secondary harts and wait for acknowledgment. * |