diff options
215 files changed, 1078 insertions, 3317 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 01276dbee7..5e8693f877 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -490,7 +490,7 @@ F: arch/arm/mach-tegra/ F: arch/arm/include/asm/arch-tegra*/ ARM TI -M: Lokesh Vutla <lokeshvutla@ti.com> +M: Tom Rini <trini@konsulko.com> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-ti.git F: arch/arm/mach-davinci/ @@ -3,7 +3,7 @@ VERSION = 2021 PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = -rc4 NAME = # *DOCUMENTATION* @@ -2631,9 +2631,6 @@ Low Level (hardware related) configuration options: CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM: Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM) -- CONFIG_PCI_INDIRECT_BRIDGE: - Enable support for indirect PCI bridges. - - CONFIG_SYS_SRIO: Chip has SRIO or not diff --git a/arch/Kconfig b/arch/Kconfig index abb7488e64..3e2cc84ab2 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -206,7 +206,6 @@ config X86 select SUPPORT_TPL select CREATE_ARCH_SYMLINK select DM - select DM_PCI select HAVE_ARCH_IOMAP select HAVE_PRIVATE_LIBGCC select OF_CONTROL diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 21f17c202f..f0fd57f8d6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1696,7 +1696,7 @@ config TARGET_SL28 select DM_SPI_FLASH select DM_ETH select DM_MDIO - select DM_PCI + select PCI select DM_RNG select DM_RTC select DM_SCSI diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi index ce07cec846..b5093020ee 100644 --- a/arch/arm/dts/am33xx.dtsi +++ b/arch/arm/dts/am33xx.dtsi @@ -380,28 +380,24 @@ #address-cells = <1>; #size-cells = <1>; ti,hwmods = "usb_otg_hs"; - status = "disabled"; usb_ctrl_mod: control@44e10620 { compatible = "ti,am335x-usb-ctrl-module"; reg = <0x44e10620 0x10 0x44e10648 0x4>; reg-names = "phy_ctrl", "wakeup"; - status = "disabled"; }; usb0_phy: usb-phy@47401300 { compatible = "ti,am335x-usb-phy"; reg = <0x47401300 0x100>; reg-names = "phy"; - status = "disabled"; ti,ctrl_mod = <&usb_ctrl_mod>; #phy-cells = <0>; }; usb0: usb@47401000 { compatible = "ti,musb-am33xx"; - status = "disabled"; reg = <0x47401400 0x400 0x47401000 0x200>; reg-names = "mc", "control"; @@ -443,14 +439,12 @@ compatible = "ti,am335x-usb-phy"; reg = <0x47401b00 0x100>; reg-names = "phy"; - status = "disabled"; ti,ctrl_mod = <&usb_ctrl_mod>; #phy-cells = <0>; }; usb1: usb@47401800 { compatible = "ti,musb-am33xx"; - status = "disabled"; reg = <0x47401c00 0x400 0x47401800 0x200>; reg-names = "mc", "control"; diff --git a/arch/arm/dts/am3517-evm-ui.dtsi b/arch/arm/dts/am3517-evm-ui.dtsi index e841918c1c..54aa2522aa 100644 --- a/arch/arm/dts/am3517-evm-ui.dtsi +++ b/arch/arm/dts/am3517-evm-ui.dtsi @@ -186,14 +186,14 @@ }; &mcbsp1 { - status = "ok"; + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp1_pins>; }; &mcbsp2 { - status = "ok"; + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp2_pins>; diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts index 3527c0f2df..935c471c97 100644 --- a/arch/arm/dts/am3517-evm.dts +++ b/arch/arm/dts/am3517-evm.dts @@ -193,7 +193,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; diff --git a/arch/arm/dts/am437x-gp-evm.dts b/arch/arm/dts/am437x-gp-evm.dts index 3c500d52db..21f7691f49 100644 --- a/arch/arm/dts/am437x-gp-evm.dts +++ b/arch/arm/dts/am437x-gp-evm.dts @@ -742,7 +742,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_pins>; diff --git a/arch/arm/dts/am43x-epos-evm.dts b/arch/arm/dts/am43x-epos-evm.dts index 65f157ed59..b940bc6ccf 100644 --- a/arch/arm/dts/am43x-epos-evm.dts +++ b/arch/arm/dts/am43x-epos-evm.dts @@ -752,7 +752,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_pins>; diff --git a/arch/arm/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/dts/am57xx-beagle-x15-common.dtsi index d6b94d528f..1912ea9a15 100644 --- a/arch/arm/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/dts/am57xx-beagle-x15-common.dtsi @@ -528,13 +528,13 @@ }; &dss { - status = "ok"; + status = "okay"; vdda_video-supply = <&ldoln_reg>; }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&ldo4_reg>; port { @@ -545,7 +545,7 @@ }; &pcie1_rc { - status = "ok"; + status = "okay"; gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index b158f92349..9104042359 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -175,6 +175,7 @@ }; &cp0_mdio { + status = "okay"; phy0: ethernet-phy@0 { reg = <0>; }; diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts index 6a586dbbba..79ee871c5a 100644 --- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts @@ -295,6 +295,7 @@ }; &cp1_mdio { + status = "okay"; phy0: ethernet-phy@0 { reg = <0>; }; diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index 51c2f23f4d..2686e00242 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -270,6 +270,7 @@ }; &cp0_mdio { + status = "okay"; phy1: ethernet-phy@1 { reg = <1>; }; diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index 2184648318..b0bed77ae6 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -155,6 +155,7 @@ }; &cp0_mdio { + status = "okay"; ge_phy: ethernet-phy@0 { reg = <0>; }; diff --git a/arch/arm/dts/beacon-renesom-som.dtsi b/arch/arm/dts/beacon-renesom-som.dtsi index 9565495b49..d30bab3c8b 100644 --- a/arch/arm/dts/beacon-renesom-som.dtsi +++ b/arch/arm/dts/beacon-renesom-som.dtsi @@ -7,6 +7,10 @@ #include <dt-bindings/clk/versaclock.h> / { + aliases { + spi0 = &rpc; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ @@ -275,6 +279,25 @@ }; }; +&rpc { + compatible = "renesas,rcar-gen3-rpc"; + num-cs = <1>; + spi-max-frequency = <40000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <40000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + &scif_clk { clock-frequency = <14745600>; }; diff --git a/arch/arm/dts/da850-evm.dts b/arch/arm/dts/da850-evm.dts index f04bc3e153..b331cefd18 100644 --- a/arch/arm/dts/da850-evm.dts +++ b/arch/arm/dts/da850-evm.dts @@ -405,7 +405,7 @@ &aemif { pinctrl-names = "default"; pinctrl-0 = <&nand_pins>; - status = "ok"; + status = "okay"; cs3 { #address-cells = <2>; #size-cells = <1>; diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index 43de9638e3..8e9a1a80a8 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -501,7 +501,7 @@ }; &dcan1 { - status = "ok"; + status = "okay"; pinctrl-names = "default", "sleep", "active"; pinctrl-0 = <&dcan1_pins_sleep>; pinctrl-1 = <&dcan1_pins_sleep>; diff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi index 2e485a13df..964e5e9b90 100644 --- a/arch/arm/dts/dra72-evm-common.dtsi +++ b/arch/arm/dts/dra72-evm-common.dtsi @@ -430,7 +430,7 @@ }; &dcan1 { - status = "ok"; + status = "okay"; pinctrl-names = "default", "sleep", "active"; pinctrl-0 = <&dcan1_pins_sleep>; pinctrl-1 = <&dcan1_pins_sleep>; @@ -499,11 +499,11 @@ }; &dss { - status = "ok"; + status = "okay"; }; &hdmi { - status = "ok"; + status = "okay"; port { hdmi_out: endpoint { diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi index ed38b7269e..03688a51a3 100644 --- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi @@ -59,6 +59,10 @@ u-boot,dm-spl; }; +&main_mmc1_pins_default { + u-boot,dm-spl; +}; + &main_usb0_pins_default { u-boot,dm-spl; }; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index a12607dc2f..4b2362a5dd 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -280,7 +280,7 @@ /delete-property/ assigned-clocks; /delete-property/ assigned-clock-parents; clocks = <&clk_19_2mhz>; - clock-names = "usb2_refclk"; + clock-names = "ref"; pinctrl-names = "default"; pinctrl-0 = <&main_usbss0_pins_default>; ti,vbus-divider; diff --git a/arch/arm/dts/keystone-k2e-evm.dts b/arch/arm/dts/keystone-k2e-evm.dts index 9288df21ce..bb197e133e 100644 --- a/arch/arm/dts/keystone-k2e-evm.dts +++ b/arch/arm/dts/keystone-k2e-evm.dts @@ -142,7 +142,7 @@ }; &mdio { - status = "ok"; + status = "okay"; ethphy0: ethernet-phy@0 { compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; reg = <0>; diff --git a/arch/arm/dts/keystone-k2hk-evm.dts b/arch/arm/dts/keystone-k2hk-evm.dts index 84c58d75ad..acfcaff0a8 100644 --- a/arch/arm/dts/keystone-k2hk-evm.dts +++ b/arch/arm/dts/keystone-k2hk-evm.dts @@ -170,7 +170,7 @@ }; &mdio { - status = "ok"; + status = "okay"; ethphy0: ethernet-phy@0 { compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; reg = <0>; diff --git a/arch/arm/dts/keystone-k2l-evm.dts b/arch/arm/dts/keystone-k2l-evm.dts index 91cefdf2aa..ca049ba81b 100644 --- a/arch/arm/dts/keystone-k2l-evm.dts +++ b/arch/arm/dts/keystone-k2l-evm.dts @@ -119,7 +119,7 @@ }; &mdio { - status = "ok"; + status = "okay"; ethphy0: ethernet-phy@0 { compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; reg = <0>; diff --git a/arch/arm/dts/omap3-beagle-xm.dts b/arch/arm/dts/omap3-beagle-xm.dts index 0349fcc9dc..8461159baf 100644 --- a/arch/arm/dts/omap3-beagle-xm.dts +++ b/arch/arm/dts/omap3-beagle-xm.dts @@ -379,7 +379,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = < @@ -396,7 +396,7 @@ }; &venc { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; diff --git a/arch/arm/dts/omap3-beagle.dts b/arch/arm/dts/omap3-beagle.dts index 3ca8991a6c..4ceee2ba19 100644 --- a/arch/arm/dts/omap3-beagle.dts +++ b/arch/arm/dts/omap3-beagle.dts @@ -353,7 +353,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; @@ -367,7 +367,7 @@ }; &venc { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; @@ -380,7 +380,7 @@ }; &gpmc { - status = "ok"; + status = "okay"; ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */ /* Chip select 0 */ diff --git a/arch/arm/dts/omap3-igep0020-common.dtsi b/arch/arm/dts/omap3-igep0020-common.dtsi index ecbec23af4..d62481dacd 100644 --- a/arch/arm/dts/omap3-igep0020-common.dtsi +++ b/arch/arm/dts/omap3-igep0020-common.dtsi @@ -248,7 +248,7 @@ }; &dss { - status = "ok"; + status = "okay"; port { dpi_out: endpoint { diff --git a/arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi b/arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi index b8b9fcc41e..2dbb687d4d 100644 --- a/arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi +++ b/arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi @@ -46,7 +46,7 @@ }; &dss { - status = "ok"; + status = "okay"; port { dpi_out: endpoint { remote-endpoint = <&lcd_in>; diff --git a/arch/arm/dts/omap34xx.dtsi b/arch/arm/dts/omap34xx.dtsi index ac4f8795b7..a703d09736 100644 --- a/arch/arm/dts/omap34xx.dtsi +++ b/arch/arm/dts/omap34xx.dtsi @@ -69,7 +69,7 @@ }; &ssi { - status = "ok"; + status = "okay"; clocks = <&ssi_ssr_fck>, <&ssi_sst_fck>, diff --git a/arch/arm/dts/omap36xx.dtsi b/arch/arm/dts/omap36xx.dtsi index 6fb23ada1f..52e1b8ce0f 100644 --- a/arch/arm/dts/omap36xx.dtsi +++ b/arch/arm/dts/omap36xx.dtsi @@ -153,7 +153,7 @@ }; &ssi { - status = "ok"; + status = "okay"; clocks = <&ssi_ssr_fck>, <&ssi_sst_fck>, diff --git a/arch/arm/dts/omap4-panda-common.dtsi b/arch/arm/dts/omap4-panda-common.dtsi index 55ea8b6189..c124b20d46 100644 --- a/arch/arm/dts/omap4-panda-common.dtsi +++ b/arch/arm/dts/omap4-panda-common.dtsi @@ -546,7 +546,7 @@ }; &dss { - status = "ok"; + status = "okay"; port { dpi_out: endpoint { @@ -557,12 +557,12 @@ }; &dsi2 { - status = "ok"; + status = "okay"; vdd-supply = <&vcxio>; }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; port { diff --git a/arch/arm/dts/omap4-sdp.dts b/arch/arm/dts/omap4-sdp.dts index 91480ac1f3..28b989cfdb 100644 --- a/arch/arm/dts/omap4-sdp.dts +++ b/arch/arm/dts/omap4-sdp.dts @@ -648,11 +648,11 @@ }; &dss { - status = "ok"; + status = "okay"; }; &dsi1 { - status = "ok"; + status = "okay"; vdd-supply = <&vcxio>; port { @@ -677,7 +677,7 @@ }; &dsi2 { - status = "ok"; + status = "okay"; vdd-supply = <&vcxio>; port { @@ -702,7 +702,7 @@ }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; port { diff --git a/arch/arm/dts/omap5-board-common.dtsi b/arch/arm/dts/omap5-board-common.dtsi index 68ac04641b..1eedd8d706 100644 --- a/arch/arm/dts/omap5-board-common.dtsi +++ b/arch/arm/dts/omap5-board-common.dtsi @@ -743,11 +743,11 @@ }; &dss { - status = "ok"; + status = "okay"; }; &hdmi { - status = "ok"; + status = "okay"; /* vdda-supply populated in board specific dts file */ diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 157217ee7f..ee73006ae8 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -236,7 +236,7 @@ config TARGET_KOSAGI_NOVENA select DM_ETH select DM_GPIO select DM_MMC - select DM_PCI + select PCI select DM_SCSI select DM_VIDEO select OF_CONTROL diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 0b935c46fb..0272dd7352 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -14,6 +14,7 @@ #include <asm/pl310.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> +#include <asm/spl.h> #include <sdhci.h> #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) @@ -80,6 +81,65 @@ int mvebu_soc_family(void) return MVEBU_SOC_UNKNOWN; } +u32 get_boot_device(void) +{ + u32 val; + u32 boot_device; + + /* + * First check, if UART boot-mode is active. This can only + * be done, via the bootrom error register. Here the + * MSB marks if the UART mode is active. + */ + val = readl(CONFIG_BOOTROM_ERR_REG); + boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS; + debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device); + if (boot_device == BOOTROM_ERR_MODE_UART) + return BOOT_DEVICE_UART; + +#ifdef CONFIG_ARMADA_38X + /* + * If the bootrom error code contains any other than zeros it's an + * error condition and the bootROM has fallen back to UART boot + */ + boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS; + if (boot_device) + return BOOT_DEVICE_UART; +#endif + + /* + * Now check the SAR register for the strapped boot-device + */ + val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; + debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device); + switch (boot_device) { +#ifdef BOOT_FROM_NAND + case BOOT_FROM_NAND: + return BOOT_DEVICE_NAND; +#endif +#ifdef BOOT_FROM_MMC + case BOOT_FROM_MMC: + case BOOT_FROM_MMC_ALT: + return BOOT_DEVICE_MMC1; +#endif + case BOOT_FROM_UART: +#ifdef BOOT_FROM_UART_ALT + case BOOT_FROM_UART_ALT: +#endif + return BOOT_DEVICE_UART; +#ifdef BOOT_FROM_SATA + case BOOT_FROM_SATA: + case BOOT_FROM_SATA_ALT: + return BOOT_DEVICE_SATA; +#endif + case BOOT_FROM_SPI: + return BOOT_DEVICE_SPI; + default: + return BOOT_DEVICE_BOOTROM; + }; +} + #if defined(CONFIG_DISPLAY_CPUINFO) #if defined(CONFIG_ARMADA_375) diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 79858858c2..a7a62c7e7d 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -148,6 +148,8 @@ void __noreturn return_to_bootrom(void); int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); #endif +u32 get_boot_device(void); + void get_sar_freq(struct sar_freq_modes *sar_freq); /* diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 8e8a405855..aab61f7c15 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -189,7 +189,7 @@ #define BOOT_FROM_SPI 0x3 #define CONFIG_SYS_TCLK 200000000 /* 200MHz */ -#else +#elif defined(CONFIG_ARMADA_XP) /* SAR values for Armada XP */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) #define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 77ee46cdd8..b798c797cc 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -172,74 +172,6 @@ int spl_parse_board_header(struct spl_image_info *spl_image, return 0; } -static u32 get_boot_device(void) -{ - u32 val; - u32 boot_device; - - /* - * First check, if UART boot-mode is active. This can only - * be done, via the bootrom error register. Here the - * MSB marks if the UART mode is active. - */ - val = readl(CONFIG_BOOTROM_ERR_REG); - boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS; - debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device); - if (boot_device == BOOTROM_ERR_MODE_UART) - return BOOT_DEVICE_UART; - -#ifdef CONFIG_ARMADA_38X - /* - * If the bootrom error code contains any other than zeros it's an - * error condition and the bootROM has fallen back to UART boot - */ - boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS; - if (boot_device) - return BOOT_DEVICE_UART; -#endif - - /* - * Now check the SAR register for the strapped boot-device - */ - val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ - boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; - debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device); - switch (boot_device) { -#ifdef BOOT_FROM_NAND - case BOOT_FROM_NAND: - return BOOT_DEVICE_NAND; -#endif -#ifdef BOOT_FROM_MMC - case BOOT_FROM_MMC: - case BOOT_FROM_MMC_ALT: - return BOOT_DEVICE_MMC1; -#endif - case BOOT_FROM_UART: -#ifdef BOOT_FROM_UART_ALT - case BOOT_FROM_UART_ALT: -#endif - return BOOT_DEVICE_UART; -#ifdef BOOT_FROM_SATA - case BOOT_FROM_SATA: - case BOOT_FROM_SATA_ALT: - return BOOT_DEVICE_SATA; -#endif - case BOOT_FROM_SPI: - return BOOT_DEVICE_SPI; - default: - return BOOT_DEVICE_BOOTROM; - }; -} - -#else - -static u32 get_boot_device(void) -{ - return BOOT_DEVICE_BOOTROM; -} - -#endif - u32 spl_boot_device(void) { u32 boot_device = get_boot_device(); @@ -286,6 +218,15 @@ u32 spl_boot_device(void) } } +#else + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} + +#endif + int board_return_to_bootrom(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index f4791c1ebe..bddfd44427 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -11,7 +11,7 @@ config SOCFPGA_SECURE_VAB_AUTH depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X select FIT_IMAGE_POST_PROCESS select SHA384 - select SHA512_ALGO + select SHA512 select SPL_FIT_IMAGE_POST_PROCESS help All images loaded from FIT will be authenticated by Secure Device diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 94f25f34e0..920b99bb68 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -47,7 +47,7 @@ ulong board_get_usable_ram_top(ulong total_size) struct lmb lmb; if (!total_size) - return gd->ram_base + gd->ram_size; + return gd->ram_top; /* found enough not-reserved memory to relocated U-Boot */ lmb_init(&lmb); diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ebfa8e668c..28234aa0bb 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -17,7 +17,7 @@ config TARGET_MALTA select BOARD_EARLY_INIT_R select DM select DM_SERIAL - select DM_PCI + select PCI select DM_ETH select DYNAMIC_IO_PORT_BASE select MIPS_CM diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index cc2e4ff647..836aeddbe2 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -179,12 +179,6 @@ config TARGET_KMCENT2 bool "Support kmcent2" select VENDOR_KM -config TARGET_UCP1020 - bool "Support uCP1020" - select ARCH_P1020 - imply CMD_SATA - imply PANIC_HANG - endchoice config ARCH_B4420 @@ -1163,6 +1157,5 @@ source "board/freescale/t208xrdb/Kconfig" source "board/freescale/t4rdb/Kconfig" source "board/keymile/Kconfig" source "board/socrates/Kconfig" -source "board/Arcturus/ucp1020/Kconfig" endmenu diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 519507d570..ba29e70acf 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. +config SIFIVE_CACHE + bool + help + This enables the operations to configure SiFive cache + config ANDES_PLIC bool depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig index 05463b2625..1604b412b4 100644 --- a/arch/riscv/cpu/fu540/Kconfig +++ b/arch/riscv/cpu/fu540/Kconfig @@ -19,6 +19,8 @@ config SIFIVE_FU540 imply SMP imply CLK_SIFIVE imply CLK_SIFIVE_PRCI + imply SIFIVE_CACHE + imply SIFIVE_CCACHE imply SIFIVE_SERIAL imply MACB imply MII diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile index 088205ef57..043fb961a5 100644 --- a/arch/riscv/cpu/fu540/Makefile +++ b/arch/riscv/cpu/fu540/Makefile @@ -8,5 +8,4 @@ obj-y += spl.o else obj-y += dram.o obj-y += cpu.o -obj-y += cache.o endif diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c deleted file mode 100644 index 0fc4ef6c00..0000000000 --- a/arch/riscv/cpu/fu540/cache.c +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 SiFive, Inc - * - * Authors: - * Pragnesh Patel <pragnesh.patel@sifive.com> - */ - -#include <common.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <linux/bitops.h> - -/* Register offsets */ -#define L2_CACHE_CONFIG 0x000 -#define L2_CACHE_ENABLE 0x008 - -#define MASK_NUM_WAYS GENMASK(15, 8) -#define NUM_WAYS_SHIFT 8 - -DECLARE_GLOBAL_DATA_PTR; - -int cache_enable_ways(void) -{ - const void *blob = gd->fdt_blob; - int node; - fdt_addr_t base; - u32 config; - u32 ways; - - volatile u32 *enable; - - node = fdt_node_offset_by_compatible(blob, -1, - "sifive,fu540-c000-ccache"); - - if (node < 0) - return node; - - base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0, - NULL, false); - if (base == FDT_ADDR_T_NONE) - return FDT_ADDR_T_NONE; - - config = readl((volatile u32 *)base + L2_CACHE_CONFIG); - ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; - - enable = (volatile u32 *)(base + L2_CACHE_ENABLE); - - /* memory barrier */ - mb(); - (*enable) = ways - 1; - /* memory barrier */ - mb(); - return 0; -} diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig index 408195f149..049a0a0584 100644 --- a/arch/riscv/cpu/fu740/Kconfig +++ b/arch/riscv/cpu/fu740/Kconfig @@ -19,6 +19,8 @@ config SIFIVE_FU740 imply SMP imply CLK_SIFIVE imply CLK_SIFIVE_PRCI + imply SIFIVE_CACHE + imply SIFIVE_CCACHE imply SIFIVE_SERIAL imply MACB imply MII diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile index 5ef8ac18a7..1d1ad98ba7 100644 --- a/arch/riscv/cpu/fu740/Makefile +++ b/arch/riscv/cpu/fu740/Makefile @@ -8,5 +8,4 @@ obj-y += spl.o else obj-y += dram.o obj-y += cpu.o -obj-y += cache.o endif diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c deleted file mode 100644 index 680955c9e3..0000000000 --- a/arch/riscv/cpu/fu740/cache.c +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020-2021 SiFive, Inc - * - * Authors: - * Pragnesh Patel <pragnesh.patel@sifive.com> - */ - -#include <common.h> -#include <asm/io.h> -#include <linux/bitops.h> -#include <asm/global_data.h> - -/* Register offsets */ -#define L2_CACHE_CONFIG 0x000 -#define L2_CACHE_ENABLE 0x008 - -#define MASK_NUM_WAYS GENMASK(15, 8) -#define NUM_WAYS_SHIFT 8 - -DECLARE_GLOBAL_DATA_PTR; - -int cache_enable_ways(void) -{ - const void *blob = gd->fdt_blob; - int node; - fdt_addr_t base; - u32 config; - u32 ways; - - volatile u32 *enable; - - node = fdt_node_offset_by_compatible(blob, -1, - "sifive,fu740-c000-ccache"); - - if (node < 0) - return node; - - base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0, - NULL, false); - if (base == FDT_ADDR_T_NONE) - return FDT_ADDR_T_NONE; - - config = readl((volatile u32 *)base + L2_CACHE_CONFIG); - ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; - - enable = (volatile u32 *)(base + L2_CACHE_ENABLE); - - /* memory barrier */ - mb(); - (*enable) = ways - 1; - /* memory barrier */ - mb(); - return 0; -} diff --git a/arch/riscv/include/asm/arch-fu540/cache.h b/arch/riscv/include/asm/arch-fu540/cache.h deleted file mode 100644 index 135a17c679..0000000000 --- a/arch/riscv/include/asm/arch-fu540/cache.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2020 SiFive, Inc. - * - * Authors: - * Pragnesh Patel <pragnesh.patel@sifve.com> - */ - -#ifndef _CACHE_SIFIVE_H -#define _CACHE_SIFIVE_H - -int cache_enable_ways(void); - -#endif /* _CACHE_SIFIVE_H */ diff --git a/arch/riscv/include/asm/arch-fu740/cache.h b/arch/riscv/include/asm/arch-fu740/cache.h deleted file mode 100644 index 7d4fe9942b..0000000000 --- a/arch/riscv/include/asm/arch-fu740/cache.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2020-2021 SiFive, Inc. - * - * Authors: - * Pragnesh Patel <pragnesh.patel@sifve.com> - */ - -#ifndef _CACHE_SIFIVE_H -#define _CACHE_SIFIVE_H - -int cache_enable_ways(void); - -#endif /* _CACHE_SIFIVE_H */ diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index ec8fe201d3..874963d731 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -8,7 +8,7 @@ #define _ASM_RISCV_CACHE_H /* cache */ -void cache_flush(void); +void cache_flush(void); /* * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index c4cc41434b..06020fcc2a 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o +obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o obj-$(CONFIG_ANDES_PLIC) += andes_plic.o diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index b1d42bcc2b..686e699efb 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -70,3 +70,7 @@ __weak int dcache_status(void) { return 0; } + +__weak void enable_caches(void) +{ +} diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 7525c152b8..100be2e966 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -51,6 +51,38 @@ static void show_regs(struct pt_regs *regs) #endif } +/** + * instr_len() - get instruction length + * + * @i: low 16 bits of the instruction + * Return: number of u16 in instruction + */ +static int instr_len(u16 i) +{ + if ((i & 0x03) != 0x03) + return 1; + /* Instructions with more than 32 bits are not yet specified */ + return 2; +} + +/** + * show_code() - display code leading to exception + * + * @epc: program counter + */ +static void show_code(ulong epc) +{ + u16 *pos = (u16 *)(epc & ~1UL); + int i, len = instr_len(*pos); + + printf("\nCode: "); + for (i = -8; i; ++i) + printf("%04x ", pos[i]); + printf("("); + for (i = 0; i < len; ++i) + printf("%04x%s", pos[i], i + 1 == len ? ")\n" : " "); +} + static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) { static const char * const exception_code[] = { @@ -85,6 +117,7 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) epc - gd->reloc_off, regs->ra - gd->reloc_off); show_regs(regs); + show_code(epc); show_efi_loaded_images(epc); panic("\n"); } diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c new file mode 100644 index 0000000000..28154878fc --- /dev/null +++ b/arch/riscv/lib/sifive_cache.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 SiFive, Inc + */ + +#include <common.h> +#include <cache.h> +#include <cpu_func.h> +#include <dm.h> + +void enable_caches(void) +{ + struct udevice *dev; + int ret; + + /* Enable ways of ccache */ + ret = uclass_get_device_by_driver(UCLASS_CACHE, + DM_DRIVER_GET(sifive_ccache), + &dev); + if (ret) { + log_debug("Cannot enable cache ways"); + } else { + ret = cache_enable(dev); + if (ret) + log_debug("ccache enable failed"); + } +} diff --git a/board/Arcturus/ucp1020/Kconfig b/board/Arcturus/ucp1020/Kconfig deleted file mode 100644 index fe2c3be1b7..0000000000 --- a/board/Arcturus/ucp1020/Kconfig +++ /dev/null @@ -1,36 +0,0 @@ -if TARGET_UCP1020 - -config SYS_BOARD - string - default "ucp1020" - -config SYS_VENDOR - string - default "Arcturus" - -config SYS_CONFIG_NAME - string - default "UCP1020" - -choice - prompt "Target image select" - -config TARGET_UCP1020_NOR - bool "NOR flash u-boot image" - -config TARGET_UCP1020_SPIFLASH - bool "SPI flash u-boot image" - -endchoice - -if TARGET_UCP1020_SPIFLASH -config UCBOOT - bool - default y - -config SPIFLASH - bool - default y -endif - -endif diff --git a/board/Arcturus/ucp1020/MAINTAINERS b/board/Arcturus/ucp1020/MAINTAINERS deleted file mode 100644 index e4a4718188..0000000000 --- a/board/Arcturus/ucp1020/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -UCP1020 BOARD -M: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com> -S: Maintained -F: board/Arcturus/ucp1020/ -F: include/configs/UCP1020.h -F: configs/UCP1020_defconfig -F: configs/UCP1020_SPIFLASH_defconfig diff --git a/board/Arcturus/ucp1020/Makefile b/board/Arcturus/ucp1020/Makefile deleted file mode 100644 index 46d04fb78c..0000000000 --- a/board/Arcturus/ucp1020/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2013-2015 Arcturus Networks, Inc. -# based on board/freescale/p1_p2_rdb_pc/Makefile -# original copyright follows: -# Copyright 2010-2011 Freescale Semiconductor, Inc. - -MINIMAL= - -ifdef CONFIG_SPL_BUILD -ifdef CONFIG_SPL_INIT_MINIMAL -MINIMAL=y -endif -endif - -ifdef MINIMAL - -obj-y += spl_minimal.o tlb.o law.o - -else -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -endif - -obj-y += ucp1020.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o -obj-y += cmd_arc.o - -endif diff --git a/board/Arcturus/ucp1020/README b/board/Arcturus/ucp1020/README deleted file mode 100644 index 555c4ef79f..0000000000 --- a/board/Arcturus/ucp1020/README +++ /dev/null @@ -1,54 +0,0 @@ -The uCP1020 product family (ucp1020) is an Arcturus Networks Inc. System on Modules -product featuring a Freescale P1020 CPU, optionally populated with 1, 2 or 3 Gig-Ethernet PHYs, -DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash. - -Information on the generic product family can be found here: - http://www.arcturusnetworks.com/products/ucp1020 - -The UCP1020 several configurable options -======================================== - -- the selection of populated phy(s): - KSZ9031 (current default for eTSEC 1 and 3) - -- the selection of boot location: - SPI Flash or NOR flash - -The UCP1020 includes 2 default configurations -============================================= -NOR boot image: - configs/UCP1020_defconfig -SPI boot image: - configs/UCP1020_SPIFLASH_defconfig - -The UCP1020 adds an additional command in cmd_arc.c to access and program -SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet -HW Addresses. - - -Build example -============= - -make distclean -make UCP1020_defconfig -make - -Default Scripts -=============== -A default upgrade scripts is included in the default environment variable example: - -B$ run tftpflash - -Dual Environment -================ - -This build enables dual / failover environment environment. - -NOR Flash Partition declarations and scripts -============================================ -Several scripts are available to allow TFTP of images and programming directly -into defined NOR flash partitions. Examples: - -B$ run program0 -B$ run program1 -B$ run program2 diff --git a/board/Arcturus/ucp1020/cmd_arc.c b/board/Arcturus/ucp1020/cmd_arc.c deleted file mode 100644 index 4b30b66e20..0000000000 --- a/board/Arcturus/ucp1020/cmd_arc.c +++ /dev/null @@ -1,408 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Command for accessing Arcturus factory environment. - * - * Copyright 2013-2019 Arcturus Networks Inc. - * https://www.arcturusnetworks.com/products/ - * by Oleksandr G Zhadan et al. - * - */ - -#include <common.h> -#include <command.h> -#include <cpu_func.h> -#include <div64.h> -#include <env.h> -#include <flash.h> -#include <malloc.h> -#include <spi_flash.h> -#include <mmc.h> -#include <version.h> -#include <asm/io.h> -#include <linux/stringify.h> - -static ulong fwenv_addr[MAX_FWENV_ADDR]; -const char mystrerr[] = "ERROR: Failed to save factory info"; - -static int ishwaddr(char *hwaddr) -{ - if (strlen(hwaddr) == MAX_HWADDR_SIZE) - if (hwaddr[2] == ':' && - hwaddr[5] == ':' && - hwaddr[8] == ':' && - hwaddr[11] == ':' && - hwaddr[14] == ':') - return 0; - return -1; -} - -#if (FWENV_TYPE == FWENV_MMC) - -static char smac[29][18] __attribute__ ((aligned(0x200))); /* 1 MMC block is 512 bytes */ - -int set_mmc_arc_product(int argc, char *const argv[]) -{ - struct mmc *mmc; - u32 blk, cnt, n; - int i, err = 1; - void *addr; - const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV; - - mmc = find_mmc_device(mmc_dev_num); - if (!mmc) { - printf("No SD/MMC/eMMC card found\n"); - return 0; - } - if (mmc_init(mmc)) { - printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC", - mmc_dev_num); - return 0; - } - if (mmc_getwp(mmc) == 1) { - printf("Error: card is write protected!\n"); - return CMD_RET_FAILURE; - } - - /* Save factory defaults */ - addr = (void *)smac; - cnt = 1; /* One 512 bytes block */ - - for (i = 0; i < MAX_FWENV_ADDR; i++) - if (fwenv_addr[i] != -1) { - blk = fwenv_addr[i] / 512; - n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); - if (n != cnt) - printf("%s: %s [%d]\n", __func__, mystrerr, i); - else - err = 0; - } - if (err) - return -2; - - return err; -} - -static int read_mmc_arc_info(void) -{ - struct mmc *mmc; - u32 blk, cnt, n; - int i; - void *addr; - const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV; - - mmc = find_mmc_device(mmc_dev_num); - if (!mmc) { - printf("No SD/MMC/eMMC card found\n"); - return 0; - } - if (mmc_init(mmc)) { - printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC", - mmc_dev_num); - return 0; - } - - addr = (void *)smac; - cnt = 1; /* One 512 bytes block */ - - for (i = 0; i < MAX_FWENV_ADDR; i++) - if (fwenv_addr[i] != -1) { - blk = fwenv_addr[i] / 512; - n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); - flush_cache((ulong) addr, 512); - if (n == cnt) - return (i + 1); - } - return 0; -} -#endif - -#if (FWENV_TYPE == FWENV_SPI_FLASH) - -static struct spi_flash *flash; -static char smac[4][18]; - -int set_spi_arc_product(int argc, char *const argv[]) -{ - int i, err = 1; - - flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, - CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); - if (!flash) { - printf("Failed to initialize SPI flash at %u:%u\n", - CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS); - return -1; - } - - /* Save factory defaults */ - for (i = 0; i < MAX_FWENV_ADDR; i++) - if (fwenv_addr[i] != -1) - if (spi_flash_write - (flash, fwenv_addr[i], sizeof(smac), smac)) - printf("%s: %s [%d]\n", __func__, mystrerr, i); - else - err = 0; - if (err) - return -2; - - return err; -} - -static int read_spi_arc_info(void) -{ - int i; - - flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, - CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); - if (!flash) { - printf("Failed to initialize SPI flash at %u:%u\n", - CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS); - return 0; - } - for (i = 0; i < MAX_FWENV_ADDR; i++) - if (fwenv_addr[i] != -1) - if (!spi_flash_read - (flash, fwenv_addr[i], sizeof(smac), smac)) - return (i + 1); - return 0; -} -#endif - -#if (FWENV_TYPE == FWENV_NOR_FLASH) - -static char smac[4][18]; - -int set_nor_arc_product(int argc, char *const argv[]) -{ - int i, err = 1; - - /* Save factory defaults */ - for (i = 0; i < MAX_FWENV_ADDR; i++) - if (fwenv_addr[i] != -1) { - ulong fwenv_end = fwenv_addr[i] + 4; - - flash_sect_roundb(&fwenv_end); - flash_sect_protect(0, fwenv_addr[i], fwenv_end); - if (flash_write - ((char *)smac, fwenv_addr[i], sizeof(smac))) - printf("%s: %s [%d]\n", __func__, mystrerr, i); - else - err = 0; - flash_sect_protect(1, fwenv_addr[i], fwenv_end); - } - if (err) - return -2; - - return err; -} - -static int read_nor_arc_info(void) -{ - int i; - - for (i = 0; i < MAX_FWENV_ADDR; i++) - if (fwenv_addr[i] != -1) { - memcpy(smac, (void *)fwenv_addr[i], sizeof(smac)); - return (i + 1); - } - - return 0; -} -#endif - -int set_arc_product(int argc, char *const argv[]) -{ - if (argc != 5) - return -1; - - /* Check serial number */ - if (strlen(argv[1]) != MAX_SERIAL_SIZE) - return -1; - - /* Check HWaddrs */ - if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4])) - return -1; - - strcpy(smac[0], argv[1]); - strcpy(smac[1], argv[2]); - strcpy(smac[2], argv[3]); - strcpy(smac[3], argv[4]); - -#if (FWENV_TYPE == FWENV_NOR_FLASH) - return set_nor_arc_product(argc, argv); -#endif -#if (FWENV_TYPE == FWENV_SPI_FLASH) - return set_spi_arc_product(argc, argv); -#endif -#if (FWENV_TYPE == FWENV_MMC) - return set_mmc_arc_product(argc, argv); -#endif - return -2; -} - -static int read_arc_info(void) -{ -#if (FWENV_TYPE == FWENV_NOR_FLASH) - return read_nor_arc_info(); -#endif -#if (FWENV_TYPE == FWENV_SPI_FLASH) - return read_spi_arc_info(); -#endif -#if (FWENV_TYPE == FWENV_MMC) - return read_mmc_arc_info(); -#endif - return 0; -} - -static int do_get_arc_info(void) -{ - int l = read_arc_info(); - char *oldserial = env_get("SERIAL"); - char *oldversion = env_get("VERSION"); - - if (oldversion != NULL) - if (strcmp(oldversion, U_BOOT_VERSION) != 0) - oldversion = NULL; - - if (l == 0) { - printf("%s: failed to read factory info\n", __func__); - return -2; - } - - printf("\rSERIAL: "); - if (smac[0][0] == EMPY_CHAR) { - printf("<not found>\n"); - } else { - printf("%s\n", smac[0]); - env_set("SERIAL", smac[0]); - } - - if (strcmp(smac[1], "00:00:00:00:00:00") == 0) { - env_set("ethaddr", NULL); - env_set("eth1addr", NULL); - env_set("eth2addr", NULL); - goto done; - } - - printf("HWADDR0: "); - if (smac[1][0] == EMPY_CHAR) { - printf("<not found>\n"); - } else { - char *ret = env_get("ethaddr"); - - if (ret == NULL) { - env_set("ethaddr", smac[1]); - printf("%s\n", smac[1]); - } else if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) { - env_set("ethaddr", smac[1]); - printf("%s (factory)\n", smac[1]); - } else { - printf("%s\n", ret); - } - } - - if (strcmp(smac[2], "00:00:00:00:00:00") == 0) { - env_set("eth1addr", NULL); - env_set("eth2addr", NULL); - goto done; - } - - printf("HWADDR1: "); - if (smac[2][0] == EMPY_CHAR) { - printf("<not found>\n"); - } else { - char *ret = env_get("eth1addr"); - - if (ret == NULL) { - env_set("ethaddr", smac[2]); - printf("%s\n", smac[2]); - } else if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) { - env_set("eth1addr", smac[2]); - printf("%s (factory)\n", smac[2]); - } else { - printf("%s\n", ret); - } - } - - if (strcmp(smac[3], "00:00:00:00:00:00") == 0) { - env_set("eth2addr", NULL); - goto done; - } - - printf("HWADDR2: "); - if (smac[3][0] == EMPY_CHAR) { - printf("<not found>\n"); - } else { - char *ret = env_get("eth2addr"); - - if (ret == NULL) { - env_set("ethaddr", smac[3]); - printf("%s\n", smac[3]); - } else if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) { - env_set("eth2addr", smac[3]); - printf("%s (factory)\n", smac[3]); - } else { - printf("%s\n", ret); - } - } -done: - if (oldserial == NULL || oldversion == NULL) { - if (oldversion == NULL) - env_set("VERSION", U_BOOT_VERSION); - env_save(); - } - - return 0; -} - -static int init_fwenv(void) -{ - int i, ret = -1; - - fwenv_addr[0] = FWENV_ADDR1; - fwenv_addr[1] = FWENV_ADDR2; - fwenv_addr[2] = FWENV_ADDR3; - fwenv_addr[3] = FWENV_ADDR4; - - for (i = 0; i < MAX_FWENV_ADDR; i++) - if (fwenv_addr[i] != -1) - ret = 0; - if (ret) - printf("%s: No firmfare info storage address is defined\n", - __func__); - return ret; -} - -void get_arc_info(void) -{ - if (!init_fwenv()) - do_get_arc_info(); -} - -static int do_arc_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - const char *cmd; - int ret = -1; - - cmd = argv[1]; - --argc; - ++argv; - - if (init_fwenv()) - return ret; - - if (strcmp(cmd, "product") == 0) - ret = set_arc_product(argc, argv); - else if (strcmp(cmd, "info") == 0) - ret = do_get_arc_info(); - - if (ret == -1) - return CMD_RET_USAGE; - - return ret; -} - -U_BOOT_CMD(arc, 6, 1, do_arc_cmd, - "Arcturus product command sub-system", - "product serial hwaddr0 hwaddr1 hwaddr2 - save Arcturus factory env\n" - "info - show Arcturus factory env\n\n"); diff --git a/board/Arcturus/ucp1020/ddr.c b/board/Arcturus/ucp1020/ddr.c deleted file mode 100644 index a3285ebe5c..0000000000 --- a/board/Arcturus/ucp1020/ddr.c +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ - * based on board/freescale/p1_p2_rdb_pc/spl.c - * original copyright follows: - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <vsprintf.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <asm/processor.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include <asm/io.h> -#include <asm/fsl_law.h> - -#ifdef CONFIG_SYS_DDR_RAW_TIMING -#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1) -/* - * Micron MT41J128M16HA-15E - * */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 536870912u, - .capacity = 536870912u, - .primary_sdram_width = 32, - .ec_sdram_width = 8, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 14, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 2, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1650, - .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */ - .taa_ps = 14050, - .twr_ps = 15000, - .trcd_ps = 13500, - .trrd_ps = 75000, - .trp_ps = 13500, - .tras_ps = 40000, - .trc_ps = 49500, - .trfc_ps = 160000, - .twtr_ps = 75000, - .trtp_ps = 75000, - .refresh_rate_ps = 7800000, - .tfaw_ps = 30000, -}; - -#else -#error Missing raw timing data for this board -#endif - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR on board"; - - if ((controller_number == 0) && (dimm_number == 0)) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} -#endif /* CONFIG_SYS_DDR_RAW_TIMING */ - -#ifdef CONFIG_SYS_DDR_CS0_BNDS -/* Fixed sdram init -- doesn't use serial presence detect. */ -phys_size_t fixed_sdram(void) -{ - sys_info_t sysinfo; - char buf[32]; - size_t ddr_size; - fsl_ddr_cfg_regs_t ddr_cfg_regs = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, -#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, -#endif - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, - .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 - }; - - get_sys_info(&sysinfo); - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, sysinfo.freq_ddrbus)); - - ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size, LAW_TRGT_IF_DDR_1) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - }; - - return ddr_size; -} -#endif - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - int i; - - popts->clk_adjust = 6; - popts->cpo_override = 0x1f; - popts->write_data_delay = 2; - popts->half_strength_driver_enable = 1; - /* Write leveling override */ - popts->wrlvl_en = 1; - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - popts->wrlvl_start = 0x8; - popts->trwt_override = 1; - popts->trwt = 0; - - if (pdimm->primary_sdram_width == 64) - popts->data_bus_width = 0; - else if (pdimm->primary_sdram_width == 32) - popts->data_bus_width = 1; - else - printf("Error in DDR bus width configuration!\n"); - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; - popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; - } -} diff --git a/board/Arcturus/ucp1020/law.c b/board/Arcturus/ucp1020/law.c deleted file mode 100644 index cb53692a32..0000000000 --- a/board/Arcturus/ucp1020/law.c +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ - * based on board/freescale/p1_p2_rdb_pc/spl.c - * original copyright follows: - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { -#ifdef CONFIG_VSC7385_ENET - SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#endif - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c deleted file mode 100644 index 4a70a21e28..0000000000 --- a/board/Arcturus/ucp1020/spl.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ - * based on board/freescale/p1_p2_rdb_pc/spl.c - * original copyright follows: - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <clock_legacy.h> -#include <console.h> -#include <env.h> -#include <env_internal.h> -#include <init.h> -#include <ns16550.h> -#include <malloc.h> -#include <mmc.h> -#include <nand.h> -#include <i2c.h> -#include <fsl_esdhc.h> -#include <spi_flash.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; - -static const u32 sysclk_tbl[] = { - 66666000, 7499900, 83332500, 8999900, - 99999000, 11111000, 12499800, 13333200 -}; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L2_SIZE; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio, bus_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - console_init_f(); - - /* Set pmuxcr to allow both i2c1 and i2c2 */ - setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); - setbits_be32(&gur->pmuxcr, - in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); - - /* Read back the register to synchronize the write. */ - in_be32(&gur->pmuxcr); - -#ifdef CONFIG_SPL_SPI_BOOT - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); -#endif - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - gd->bus_clk = bus_clk; - - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); -#ifdef CONFIG_SPL_MMC_BOOT - puts("\nSD boot...\n"); -#elif defined(CONFIG_SPL_SPI_BOOT) - puts("\nSPI Flash boot...\n"); -#endif - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *)CONFIG_SPL_GD_ADDR; - struct bd_info *bd; - - memset(gd, 0, sizeof(gd_t)); - bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); - memset(bd, 0, sizeof(struct bd_info)); - gd->bd = bd; - - arch_cpu_init(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - -#ifndef CONFIG_SPL_NAND_BOOT - env_init(); -#endif -#ifdef CONFIG_SPL_MMC_BOOT - mmc_initialize(bd); -#endif - /* relocate environment function pointers etc. */ -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_ENV_ADDR); - gd->env_addr = (ulong)(CONFIG_ENV_ADDR); - gd->env_valid = ENV_VALID; -#else - env_relocate(); -#endif - -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) - i2c_init_all(); -#else - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - - dram_init(); -#ifdef CONFIG_SPL_NAND_BOOT - puts("Tertiary program loader running in sram..."); -#else - puts("Second program loader running in sram...\n"); -#endif - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_boot(); -#elif defined(CONFIG_SPL_NAND_BOOT) - nand_boot(); -#endif -} diff --git a/board/Arcturus/ucp1020/spl_minimal.c b/board/Arcturus/ucp1020/spl_minimal.c deleted file mode 100644 index 90abec9cce..0000000000 --- a/board/Arcturus/ucp1020/spl_minimal.c +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ - * based on board/freescale/p1_p2_rdb_pc/spl_minimal.c - * original copyright follows: - * Copyright 2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <ns16550.h> -#include <asm/io.h> -#include <nand.h> -#include <linux/compiler.h> -#include <asm/fsl_law.h> -#include <fsl_ddr_sdram.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - -#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); -#endif - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - puts("\nSecond program loader running in sram..."); - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r'); - - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/board/Arcturus/ucp1020/tlb.c b/board/Arcturus/ucp1020/tlb.c deleted file mode 100644 index 2c07df63e5..0000000000 --- a/board/Arcturus/ucp1020/tlb.c +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013-2015 Arcturus Networks, Inc - * http://www.arcturusnetworks.com/products/ucp1020/ - * based on board/freescale/p1_p2_rdb_pc/tlb.c - * original copyright follows: - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - -#ifndef CONFIG_SPL_BUILD - /* W**G* - Flash/promjet, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX | MAS3_SR, MAS2_W | MAS2_G, - 0, 2, BOOKE_PAGESZ_64M, 1), - -#ifdef CONFIG_PCI - /* *I*G* - PCI memory 1.5G */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI I/O effective: 192K */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 4, BOOKE_PAGESZ_256K, 1), -#endif - -#ifdef CONFIG_VSC7385_ENET - /* *I*G - VSC7385 Switch */ - SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 5, BOOKE_PAGESZ_1M, 1), -#endif -#endif /* not SPL */ - -#ifdef CONFIG_SYS_NAND_BASE - /* *I*G - NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 7, BOOKE_PAGESZ_1M, 1), -#endif - -#if defined(CONFIG_SYS_RAMBOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) - /* *I*G - eSDHC/eSPI/NAND boot */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, - 0, 8, BOOKE_PAGESZ_1G, 1), - -#endif /* RAMBOOT/SPL */ - -#ifdef CONFIG_SYS_INIT_L2_ADDR - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G, - 0, 11, BOOKE_PAGESZ_256K, 1), -#if CONFIG_SYS_L2_SIZE >= (256 << 10) - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 12, BOOKE_PAGESZ_256K, 1) -#endif -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/Arcturus/ucp1020/ucp1020.c b/board/Arcturus/ucp1020/ucp1020.c deleted file mode 100644 index ee8a9e0a5e..0000000000 --- a/board/Arcturus/ucp1020/ucp1020.c +++ /dev/null @@ -1,372 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013-2019 Arcturus Networks, Inc. - * https://www.arcturusnetworks.com/products/ucp1020/ - * by Oleksandr G Zhadan et al. - * based on board/freescale/p1_p2_rdb_pc/spl.c - * original copyright follows: - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <hwconfig.h> -#include <image.h> -#include <init.h> -#include <net.h> -#include <pci.h> -#include <i2c.h> -#include <miiphy.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <fsl_mdio.h> -#include <tsec.h> -#include <ioports.h> -#include <netdev.h> -#include <micrel.h> -#include <spi_flash.h> -#include <mmc.h> -#include <linux/ctype.h> -#include <asm/fsl_serdes.h> -#include <asm/gpio.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/io.h> -#include <asm/fsl_law.h> -#include <asm/fsl_lbc.h> -#include <asm/mp.h> -#include "ucp1020.h" - -void spi_set_speed(struct spi_slave *slave, uint hz) -{ - /* TO DO: It's actially have to be in spi/ */ -} - -/* - * To be compatible with cmd_gpio - */ -int name_to_gpio(const char *name) -{ - int gpio = 31 - dectoul(name, NULL); - - if (gpio < 16) - gpio = -1; - - return gpio; -} - -void board_gpio_init(void) -{ - int i; - char envname[8], *val; - - for (i = 0; i < GPIO_MAX_NUM; i++) { - sprintf(envname, "GPIO%d", i); - val = env_get(envname); - if (val) { - char direction = toupper(val[0]); - char level = toupper(val[1]); - - if (direction == 'I') { - gpio_direction_input(i); - } else { - if (direction == 'O') { - if (level == '1') - gpio_direction_output(i, 1); - else - gpio_direction_output(i, 0); - } - } - } - } - - val = env_get("PCIE_OFF"); - if (val) { - gpio_direction_input(GPIO_PCIE1_EN); - gpio_direction_input(GPIO_PCIE2_EN); - } else { - gpio_direction_output(GPIO_PCIE1_EN, 1); - gpio_direction_output(GPIO_PCIE2_EN, 1); - } - - val = env_get("SDHC_CDWP_OFF"); - if (!val) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - setbits_be32(&gur->pmuxcr, - (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); - } -} - -int board_early_init_f(void) -{ - return 0; /* Just in case. Could be disable in config file */ -} - -int checkboard(void) -{ - printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL); - board_gpio_init(); -#ifdef CONFIG_MMC - printf("SD/MMC: 4-bit Mode\n"); -#endif - - return 0; -} - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */ - 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ -#if defined(CONFIG_PHY_MICREL_KSZ9021) - int regval; - static int cnt; - - if (cnt++ == 0) - printf("PHYs address ["); - - if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) { - regval = - ksz9021_phy_extended_read(phydev, - MII_KSZ9021_EXT_STRAP_STATUS); - /* - * min rx data delay - */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, - 0x6666); - /* - * max rx/tx clock delay, min rx/tx control - */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, - 0xf6f6); - printf("0x%x", (regval & 0x1f)); - } else { - printf("0x%x", (TSEC2_PHY_ADDR & 0x1f)); - } - if (cnt == 3) - printf("] "); - else - printf(","); -#endif - -#if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG) - regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000); - if (regval >= 0) - printf(" (ADDR 0x%x) ", regval & 0x1f); -#endif - - return 0; -} - -int last_stage_init(void) -{ - static char newkernelargs[256]; - static u8 id1[16]; - static u8 id2; -#ifdef CONFIG_MMC - struct mmc *mmc; -#endif - char *sval, *kval; - - if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) { - printf("Error reading i2c IDT6V49205B information!\n"); - } else { - printf("IDT6V49205B(0x%02x): ready\n", id1[1]); - i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2); - if (!(id1[1] & 0x02)) { - id1[1] |= 0x02; - i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2); - asm("nop; nop"); - } - } - - if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0) - printf("Error reading i2c NCT72 information!\n"); - else - printf("NCT72(0x%x): ready\n", id2); - - kval = env_get("kernelargs"); - -#ifdef CONFIG_MMC - mmc = find_mmc_device(0); - if (mmc) - if (!mmc_init(mmc)) { - printf("MMC/SD card detected\n"); - if (kval) { - int n = strlen(defkargs); - char *tmp = strstr(kval, defkargs); - - *tmp = 0; - strcpy(newkernelargs, kval); - strcat(newkernelargs, " "); - strcat(newkernelargs, mmckargs); - strcat(newkernelargs, " "); - strcat(newkernelargs, &tmp[n]); - env_set("kernelargs", newkernelargs); - } else { - env_set("kernelargs", mmckargs); - } - } -#endif - get_arc_info(); - - if (kval) { - sval = env_get("SERIAL"); - if (sval) { - strcpy(newkernelargs, "SN="); - strcat(newkernelargs, sval); - strcat(newkernelargs, " "); - strcat(newkernelargs, kval); - env_set("kernelargs", newkernelargs); - } - } else { - printf("Error reading kernelargs env variable!\n"); - } - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; -#ifdef CONFIG_TSEC2 - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#endif - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) { - puts("eTSEC2 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII; - } - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - num++; -#endif - - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - - return pci_eth_init(bis); -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - const char *soc_usb_compat = "fsl-usb2-dr"; - int err, usb1_off, usb2_off; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - - FT_FSL_PCI_SETUP; - -#if defined(CONFIG_HAS_FSL_DR_USB) - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - -#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) - /* Delete eLBC node as it is muxed with USB2 controller */ - if (hwconfig("usb2")) { - const char *soc_elbc_compat = "fsl,p1020-elbc"; - int off = fdt_node_offset_by_compatible(blob, -1, - soc_elbc_compat); - if (off < 0) { - printf - ("WARNING: could not find compatible node %s: %s\n", - soc_elbc_compat, fdt_strerror(off)); - return off; - } - err = fdt_del_node(blob, off); - if (err < 0) { - printf("WARNING: could not remove %s: %s\n", - soc_elbc_compat, fdt_strerror(err)); - } - return err; - } -#endif - -/* Delete USB2 node as it is muxed with eLBC */ - usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat); - if (usb1_off < 0) { - printf("WARNING: could not find compatible node %s: %s.\n", - soc_usb_compat, fdt_strerror(usb1_off)); - return usb1_off; - } - usb2_off = - fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat); - if (usb2_off < 0) { - printf("WARNING: could not find compatible node %s: %s.\n", - soc_usb_compat, fdt_strerror(usb2_off)); - return usb2_off; - } - err = fdt_del_node(blob, usb2_off); - if (err < 0) { - printf("WARNING: could not remove %s: %s.\n", - soc_usb_compat, fdt_strerror(err)); - } - return 0; -} -#endif diff --git a/board/Arcturus/ucp1020/ucp1020.h b/board/Arcturus/ucp1020/ucp1020.h deleted file mode 100644 index 1b527cdb1c..0000000000 --- a/board/Arcturus/ucp1020/ucp1020.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2019 Arcturus Networks, Inc. - * https://www.arcturusnetworks.com/products/ucp1020/ - * by Oleksandr G Zhadan et al. - */ - -#ifndef __UCP1020_H__ -#define __UCP1020_H__ - -#define GPIO0 31 -#define GPIO1 30 -#define GPIO2 29 -#define GPIO3 28 -#define GPIO4 27 -#define GPIO5 26 -#define GPIO6 25 -#define GPIO7 24 -#define GPIO8 23 -#define GPIO9 22 -#define GPIO10 21 -#define GPIO11 20 -#define GPIO12 19 -#define GPIO13 18 -#define GPIO14 17 -#define GPIO15 16 -#define GPIO_MAX_NUM 16 - -#define GPIO_SDHC_CD GPIO8 -#define GPIO_SDHC_WP GPIO9 -#define GPIO_USB_PCTL0 GPIO10 -#define GPIO_PCIE1_EN GPIO11 -#define GPIO_PCIE2_EN GPIO10 -#define GPIO_USB_PCTL1 GPIO11 - -#define GPIO_WD GPIO15 - -#ifdef CONFIG_MMC -static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro"; -static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw"; -#endif - -int get_arc_info(void); - -#endif diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index a7e5f56eed..bac78af04e 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -129,7 +129,6 @@ static int omnia_mcu_read(u8 cmd, void *buf, int len) return dm_i2c_read(chip, cmd, buf, len); } -#ifndef CONFIG_SPL_BUILD static int omnia_mcu_write(u8 cmd, const void *buf, int len) { struct udevice *chip; @@ -158,7 +157,6 @@ static bool disable_mcu_watchdog(void) return true; } -#endif static bool omnia_detect_sata(void) { @@ -325,7 +323,6 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) return &board_topology_map_1g; } -#ifndef CONFIG_SPL_BUILD static int set_regdomain(void) { struct omnia_eeprom oep; @@ -394,7 +391,6 @@ static void handle_reset_button(void) } } } -#endif int board_early_init_f(void) { @@ -423,24 +419,35 @@ int board_early_init_f(void) return 0; } +void spl_board_init(void) +{ + /* + * If booting from UART, disable MCU watchdog in SPL, since uploading + * U-Boot proper can take too much time and trigger it. + */ + if (get_boot_device() == BOOT_DEVICE_UART) + disable_mcu_watchdog(); +} + int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; -#ifndef CONFIG_SPL_BUILD - disable_mcu_watchdog(); -#endif - return 0; } int board_late_init(void) { -#ifndef CONFIG_SPL_BUILD + /* + * If not booting from UART, MCU watchdog was not disabled in SPL, + * disable it now. + */ + if (get_boot_device() != BOOT_DEVICE_UART) + disable_mcu_watchdog(); + set_regdomain(); handle_reset_button(); -#endif pci_init(); return 0; diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index d5b6b22ddf..7ba14021b2 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -163,7 +163,7 @@ void reset_phy(void) char *eth0_name = "ethernet-controller@72000"; char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0"; char *eth1_name = "ethernet-controller@76000"; - char *eth1_path = "/ocp@f1000000/ethernet-controller@72000/ethernet1-port@0"; + char *eth1_path = "/ocp@f1000000/ethernet-controller@76000/ethernet1-port@0"; /* configure and initialize both PHY's */ mv_phy_88e1116_init(eth0_name, eth0_path); diff --git a/board/Marvell/sheevaplug/MAINTAINERS b/board/Marvell/sheevaplug/MAINTAINERS index 2b0103d07d..282f046667 100644 --- a/board/Marvell/sheevaplug/MAINTAINERS +++ b/board/Marvell/sheevaplug/MAINTAINERS @@ -1,5 +1,5 @@ SHEEVAPLUG BOARD -M: Prafulla Wadaskar <prafulla@marvell.com> +M: Tony Dinh <mibodhi@gmail.com> S: Maintained F: board/Marvell/sheevaplug/ F: include/configs/sheevaplug.h diff --git a/board/davinci/da8xxevm/MAINTAINERS b/board/davinci/da8xxevm/MAINTAINERS index 16f1032661..993b22f2f6 100644 --- a/board/davinci/da8xxevm/MAINTAINERS +++ b/board/davinci/da8xxevm/MAINTAINERS @@ -8,7 +8,7 @@ F: configs/da850evm_nand_defconfig F: configs/da850evm_direct_nor_defconfig OMAPL138_LCDK BOARD -M: Lokesh Vutla <lokeshvutla@ti.com> +M: Tom Rini <trini@konsulko.com> S: Maintained F: include/configs/omap1l38_lcdk.h F: configs/omapl138_lcdk_defconfig diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index a7de82d3bf..1bbf1bc84a 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -51,7 +51,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply E1000 imply NVME imply PCI - imply DM_PCI imply PCIE_ECAM_GENERIC imply SCSI imply DM_SCSI diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig index 1e3bb42b7e..69620dbb74 100644 --- a/board/freescale/common/Kconfig +++ b/board/freescale/common/Kconfig @@ -4,6 +4,7 @@ config CHAIN_OF_TRUST imply CMD_HASH if ARM select FSL_CAAM select SPL_BOARD_INIT if (ARM && SPL) + select SPL_HASH if (ARM && SPL) select SHA_HW_ACCEL select SHA_PROG_HW_ACCEL select ENV_IS_NOWHERE diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c index fa65fcade0..8cd514df30 100644 --- a/board/sifive/unleashed/unleashed.c +++ b/board/sifive/unleashed/unleashed.c @@ -6,6 +6,7 @@ * Anup Patel <anup.patel@wdc.com> */ +#include <cpu_func.h> #include <dm.h> #include <env.h> #include <init.h> @@ -15,7 +16,6 @@ #include <linux/delay.h> #include <misc.h> #include <spl.h> -#include <asm/arch/cache.h> #include <asm/sections.h> /* @@ -126,14 +126,8 @@ void *board_fdt_blob_setup(void) int board_init(void) { - int ret; - /* enable all cache ways */ - ret = cache_enable_ways(); - if (ret) { - debug("%s: could not enable cache ways\n", __func__); - return ret; - } + enable_caches(); return 0; } diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c index da23a6ce24..d90b252bae 100644 --- a/board/sifive/unmatched/unmatched.c +++ b/board/sifive/unmatched/unmatched.c @@ -7,8 +7,8 @@ */ #include <common.h> +#include <cpu_func.h> #include <dm.h> -#include <asm/arch/cache.h> #include <asm/sections.h> void *board_fdt_blob_setup(void) @@ -23,13 +23,8 @@ void *board_fdt_blob_setup(void) int board_init(void) { - int ret; - /* enable all cache ways */ - ret = cache_enable_ways(); - if (ret) { - debug("%s: could not enable cache ways\n", __func__); - return ret; - } + enable_caches(); + return 0; } diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig index 706b8dc0f1..c181d26a44 100644 --- a/board/socionext/developerbox/Kconfig +++ b/board/socionext/developerbox/Kconfig @@ -7,7 +7,6 @@ choice config TARGET_DEVELOPERBOX bool "Socionext DeveloperBox" select PCI - select DM_PCI select PCIE_ECAM_SYNQUACER select SYS_DISABLE_DCACHE_OPS select OF_BOARD_SETUP diff --git a/board/ti/am43xx/MAINTAINERS b/board/ti/am43xx/MAINTAINERS index ab9da22c64..5478dd7104 100644 --- a/board/ti/am43xx/MAINTAINERS +++ b/board/ti/am43xx/MAINTAINERS @@ -1,5 +1,5 @@ AM43XX BOARD -M: Lokesh Vutla <lokeshvutla@ti.com> +M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/am43xx/ F: include/configs/am43xx_evm.h diff --git a/board/ti/am57xx/MAINTAINERS b/board/ti/am57xx/MAINTAINERS index 47b694eb4b..a6f4f168fc 100644 --- a/board/ti/am57xx/MAINTAINERS +++ b/board/ti/am57xx/MAINTAINERS @@ -1,5 +1,5 @@ AM57XX EVM -M: Lokesh Vutla <lokeshvutla@ti.com> +M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/am57xx/ F: include/configs/am57xx_evm.h diff --git a/board/ti/am64x/MAINTAINERS b/board/ti/am64x/MAINTAINERS index d384a330df..eaca2b865f 100644 --- a/board/ti/am64x/MAINTAINERS +++ b/board/ti/am64x/MAINTAINERS @@ -1,6 +1,6 @@ AM64x BOARD M: Dave Gerlach <d-gerlach@ti.com> -M: Lokesh Vutla <lokeshvutla@ti.com> +M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/am64x/ F: include/configs/am64x_evm.h diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index 21c58c76d6..1a9f69c6cf 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -10,6 +10,7 @@ #include <common.h> #include <asm/io.h> #include <spl.h> +#include <fdt_support.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <env.h> @@ -60,6 +61,37 @@ int board_fit_config_name_match(const char *name) } #endif +#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(USB_STORAGE) +static int fixup_usb_boot(const void *fdt_blob) +{ + int ret = 0; + + switch (spl_boot_device()) { + case BOOT_DEVICE_USB: + /* + * If the boot mode is host, fixup the dr_mode to host + * before cdns3 bind takes place + */ + ret = fdt_find_and_setprop((void *)fdt_blob, + "/bus@f4000/cdns-usb@f900000/usb@f400000", + "dr_mode", "host", 5, 0); + if (ret) + printf("%s: fdt_find_and_setprop() failed:%d\n", + __func__, ret); + fallthrough; + default: + break; + } + + return ret; +} + +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + fixup_usb_boot(spl_image->fdt_addr); +} +#endif + #ifdef CONFIG_TI_I2C_BOARD_DETECT int do_board_detect(void) { diff --git a/board/ti/am65x/MAINTAINERS b/board/ti/am65x/MAINTAINERS index 6da4182d9f..c52f7c9112 100644 --- a/board/ti/am65x/MAINTAINERS +++ b/board/ti/am65x/MAINTAINERS @@ -1,5 +1,5 @@ AM65x BOARD -M: Lokesh Vutla <lokeshvutla@ti.com> +M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/am65x/ F: include/configs/am65x_evm.h diff --git a/board/ti/dra7xx/MAINTAINERS b/board/ti/dra7xx/MAINTAINERS index 46b6e82b36..ba3d06dab9 100644 --- a/board/ti/dra7xx/MAINTAINERS +++ b/board/ti/dra7xx/MAINTAINERS @@ -1,5 +1,5 @@ DRA7XX BOARD -M: Lokesh Vutla <lokeshvutla@ti.com> +M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/dra7xx/ F: include/configs/dra7xx_evm.h diff --git a/board/ti/j721e/MAINTAINERS b/board/ti/j721e/MAINTAINERS index 4b13f46ddc..f5ca7d06a3 100644 --- a/board/ti/j721e/MAINTAINERS +++ b/board/ti/j721e/MAINTAINERS @@ -1,5 +1,5 @@ J721E BOARD -M: Lokesh Vutla <lokeshvutla@ti.com> +M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/j721e F: include/configs/j721e_evm.h diff --git a/board/ti/omap5_uevm/MAINTAINERS b/board/ti/omap5_uevm/MAINTAINERS index 280ea2f91f..ce544828f8 100644 --- a/board/ti/omap5_uevm/MAINTAINERS +++ b/board/ti/omap5_uevm/MAINTAINERS @@ -1,5 +1,5 @@ OMAP5_UEVM BOARD -M: Lokesh Vutla <lokeshvutla@ti.com> +M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/omap5_uevm/ F: include/configs/omap5_uevm.h diff --git a/board/ti/panda/MAINTAINERS b/board/ti/panda/MAINTAINERS index 2142368271..8b8cf7daf6 100644 --- a/board/ti/panda/MAINTAINERS +++ b/board/ti/panda/MAINTAINERS @@ -1,5 +1,5 @@ PANDA BOARD -M: Lokesh Vutla <lokeshvutla@ti.com> +M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/panda/ F: include/configs/omap4_panda.h diff --git a/board/ti/sdp4430/MAINTAINERS b/board/ti/sdp4430/MAINTAINERS index ac4d0ccc19..d8b8fe600e 100644 --- a/board/ti/sdp4430/MAINTAINERS +++ b/board/ti/sdp4430/MAINTAINERS @@ -1,5 +1,5 @@ SDP4430 BOARD -M: Lokesh Vutla <lokeshvutla@ti.com> +M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/sdp4430/ F: include/configs/omap4_sdp4430.h diff --git a/board/toradex/apalis-imx8/MAINTAINERS b/board/toradex/apalis-imx8/MAINTAINERS index 7fbd1be10f..507172c596 100644 --- a/board/toradex/apalis-imx8/MAINTAINERS +++ b/board/toradex/apalis-imx8/MAINTAINERS @@ -6,5 +6,5 @@ F: arch/arm/dts/fsl-imx8-apalis.dts F: arch/arm/dts/fsl-imx8-apalis-u-boot.dtsi F: board/toradex/apalis-imx8/ F: configs/apalis-imx8_defconfig -F: doc/board/toradex/apalix-imx8.rst +F: doc/board/toradex/apalis-imx8.rst F: include/configs/apalis-imx8.h diff --git a/cmd/Kconfig b/cmd/Kconfig index d8fc5a171b..5b30b13e43 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -2411,4 +2411,14 @@ config CMD_UBIFS help UBIFS is a file system for flash devices which works on top of UBI. +config MMC_SPEED_MODE_SET + bool "set speed mode using mmc command" + depends on CMD_MMC + default n + help + Enable setting speed mode using mmc rescan and mmc dev commands. + The speed mode is provided as the last argument in these commands + and is indicated using the index from enum bus_mode in + include/mmc.h. A speed mode can be set only if it has already + been enabled in the device tree. endmenu @@ -120,7 +120,9 @@ static void print_mmcinfo(struct mmc *mmc) } } } -static struct mmc *init_mmc_device(int dev, bool force_init) + +static struct mmc *__init_mmc_device(int dev, bool force_init, + enum bus_mode speed_mode) { struct mmc *mmc; mmc = find_mmc_device(dev); @@ -134,6 +136,10 @@ static struct mmc *init_mmc_device(int dev, bool force_init) if (force_init) mmc->has_init = 0; + + if (IS_ENABLED(CONFIG_MMC_SPEED_MODE_SET)) + mmc->user_speed_mode = speed_mode; + if (mmc_init(mmc)) return NULL; @@ -145,6 +151,11 @@ static struct mmc *init_mmc_device(int dev, bool force_init) return mmc; } +static struct mmc *init_mmc_device(int dev, bool force_init) +{ + return __init_mmc_device(dev, force_init, MMC_MODES_END); +} + static int do_mmcinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -482,8 +493,17 @@ static int do_mmc_rescan(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct mmc *mmc; + enum bus_mode speed_mode = MMC_MODES_END; + + if (argc == 1) { + mmc = init_mmc_device(curr_device, true); + } else if (argc == 2) { + speed_mode = (int)dectoul(argv[1], NULL); + mmc = __init_mmc_device(curr_device, true, speed_mode); + } else { + return CMD_RET_USAGE; + } - mmc = init_mmc_device(curr_device, true); if (!mmc) return CMD_RET_FAILURE; @@ -515,11 +535,14 @@ static int do_mmc_dev(struct cmd_tbl *cmdtp, int flag, { int dev, part = 0, ret; struct mmc *mmc; + enum bus_mode speed_mode = MMC_MODES_END; if (argc == 1) { dev = curr_device; + mmc = init_mmc_device(dev, true); } else if (argc == 2) { - dev = dectoul(argv[1], NULL); + dev = (int)dectoul(argv[1], NULL); + mmc = init_mmc_device(dev, true); } else if (argc == 3) { dev = (int)dectoul(argv[1], NULL); part = (int)dectoul(argv[2], NULL); @@ -528,11 +551,21 @@ static int do_mmc_dev(struct cmd_tbl *cmdtp, int flag, PART_ACCESS_MASK); return CMD_RET_FAILURE; } + mmc = init_mmc_device(dev, true); + } else if (argc == 4) { + dev = (int)dectoul(argv[1], NULL); + part = (int)dectoul(argv[2], NULL); + if (part > PART_ACCESS_MASK) { + printf("#part_num shouldn't be larger than %d\n", + PART_ACCESS_MASK); + return CMD_RET_FAILURE; + } + speed_mode = (int)dectoul(argv[3], NULL); + mmc = __init_mmc_device(dev, true, speed_mode); } else { return CMD_RET_USAGE; } - mmc = init_mmc_device(dev, true); if (!mmc) return CMD_RET_FAILURE; @@ -983,9 +1016,9 @@ static struct cmd_tbl cmd_mmc[] = { #if CONFIG_IS_ENABLED(CMD_MMC_SWRITE) U_BOOT_CMD_MKENT(swrite, 3, 0, do_mmc_sparse_write, "", ""), #endif - U_BOOT_CMD_MKENT(rescan, 1, 1, do_mmc_rescan, "", ""), + U_BOOT_CMD_MKENT(rescan, 2, 1, do_mmc_rescan, "", ""), U_BOOT_CMD_MKENT(part, 1, 1, do_mmc_part, "", ""), - U_BOOT_CMD_MKENT(dev, 3, 0, do_mmc_dev, "", ""), + U_BOOT_CMD_MKENT(dev, 4, 0, do_mmc_dev, "", ""), U_BOOT_CMD_MKENT(list, 1, 1, do_mmc_list, "", ""), #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) U_BOOT_CMD_MKENT(hwpartition, 28, 0, do_mmc_hwpartition, "", ""), @@ -1042,9 +1075,12 @@ U_BOOT_CMD( "mmc swrite addr blk#\n" #endif "mmc erase blk# cnt\n" - "mmc rescan\n" + "mmc rescan [mode]\n" "mmc part - lists available partition on current mmc device\n" - "mmc dev [dev] [part] - show or set current mmc device [partition]\n" + "mmc dev [dev] [part] [mode] - show or set current mmc device [partition] and set mode\n" + " - the required speed mode is passed as the index from the following list\n" + " [MMC_LEGACY, MMC_HS, SD_HS, MMC_HS_52, MMC_DDR_52, UHS_SDR12, UHS_SDR25,\n" + " UHS_SDR50, UHS_DDR50, UHS_SDR104, MMC_HS_200, MMC_HS_400, MMC_HS_400_ES]\n" "mmc list - lists available devices\n" "mmc wp - power on write protect boot partitions\n" #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) diff --git a/cmd/mvebu/Kconfig b/cmd/mvebu/Kconfig index 4afe0bf32d..ac8b0afd20 100644 --- a/cmd/mvebu/Kconfig +++ b/cmd/mvebu/Kconfig @@ -3,6 +3,7 @@ depends on ARCH_MVEBU config CMD_MVEBU_BUBT bool "bubt" + select SHA256 if ARMADA_3700 help bubt - Burn a u-boot image to flash For details about bubt command please see the documentation diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c index 676bbda950..710d923a91 100644 --- a/cmd/nvedit_efi.c +++ b/cmd/nvedit_efi.c @@ -187,8 +187,8 @@ static int efi_dump_var_all(int argc, char *const argv[], var_name16[0] = 0; for (;;) { size = buf_size; - ret = EFI_CALL(efi_get_next_variable_name(&size, var_name16, - &guid)); + ret = efi_get_next_variable_name_int(&size, var_name16, + &guid); if (ret == EFI_NOT_FOUND) break; if (ret == EFI_BUFFER_TOO_SMALL) { @@ -199,9 +199,8 @@ static int efi_dump_var_all(int argc, char *const argv[], return CMD_RET_FAILURE; } var_name16 = p; - ret = EFI_CALL(efi_get_next_variable_name(&size, - var_name16, - &guid)); + ret = efi_get_next_variable_name_int(&size, var_name16, + &guid); } if (ret != EFI_SUCCESS) { free(var_name16); diff --git a/common/Kconfig b/common/Kconfig index 5c1151bf54..0543b839d1 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -557,7 +557,6 @@ config ID_EEPROM config PCI_INIT_R bool "Enumerate PCI buses during init" depends on PCI - default y if !DM_PCI help With this option U-Boot will call pci_init() soon after relocation, which will enumerate PCI buses. This is needed, for instance, in the diff --git a/common/Kconfig.boot b/common/Kconfig.boot index e2780bdd8e..f23b998852 100644 --- a/common/Kconfig.boot +++ b/common/Kconfig.boot @@ -11,8 +11,10 @@ config ANDROID_BOOT_IMAGE config FIT bool "Support Flattened Image Tree" + select HASH select MD5 select SHA1 + imply SHA256 help This option allows you to boot the new uImage structure, Flattened Image Tree. FIT is formally a FDT, which can include @@ -35,32 +37,6 @@ config FIT_EXTERNAL_OFFSET could be put in the hole between data payload and fit image header, such as CSF data on i.MX platform. -config FIT_SHA256 - bool "Support SHA256 checksum of FIT image contents" - default y - select SHA256 - help - Enable this to support SHA256 checksum of FIT image contents. A - SHA256 checksum is a 256-bit (32-byte) hash value used to check that - the image contents have not been corrupted. - -config FIT_SHA384 - bool "Support SHA384 checksum of FIT image contents" - select SHA384 - help - Enable this to support SHA384 checksum of FIT image contents. A - SHA384 checksum is a 384-bit (48-byte) hash value used to check that - the image contents have not been corrupted. Use this for the highest - security. - -config FIT_SHA512 - bool "Support SHA512 checksum of FIT image contents" - select SHA512 - help - Enable this to support SHA512 checksum of FIT image contents. A - SHA512 checksum is a 512-bit (64-byte) hash value used to check that - the image contents have not been corrupted. - config FIT_FULL_CHECK bool "Do a full check of the FIT before using it" default y @@ -158,6 +134,7 @@ if SPL config SPL_FIT bool "Support Flattened Image Tree within SPL" depends on SPL + select SPL_HASH select SPL_OF_LIBFDT config SPL_FIT_PRINT @@ -182,7 +159,7 @@ config SPL_FIT_SIGNATURE select FIT_SIGNATURE select SPL_FIT select SPL_CRYPTO - select SPL_HASH_SUPPORT + select SPL_HASH imply SPL_RSA imply SPL_RSA_VERIFY select SPL_IMAGE_SIGN_INFO diff --git a/common/Makefile b/common/Makefile index f7852607a5..fb8173a5b8 100644 --- a/common/Makefile +++ b/common/Makefile @@ -8,7 +8,6 @@ ifndef CONFIG_SPL_BUILD obj-y += init/ obj-y += main.o obj-y += exports.o -obj-$(CONFIG_HASH) += hash.o obj-$(CONFIG_HUSH_PARSER) += cli_hush.o obj-$(CONFIG_AUTOBOOT) += autoboot.o @@ -66,8 +65,6 @@ ifdef CONFIG_SPL_BUILD ifdef CONFIG_SPL_DFU obj-$(CONFIG_DFU_OVER_USB) += dfu.o endif -obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o -obj-$(CONFIG_TPL_HASH_SUPPORT) += hash.o obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o obj-$(CONFIG_SPL_NET) += miiphyutil.o obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o @@ -105,6 +102,7 @@ endif endif obj-y += image.o +obj-$(CONFIG_$(SPL_TPL_)HASH) += hash.o obj-$(CONFIG_ANDROID_AB) += android_ab.o obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o image-android-dt.o obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o diff --git a/common/board_r.c b/common/board_r.c index 802a4c65d1..0cbe5f7f3d 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -114,7 +114,7 @@ static int initr_reloc(void) return 0; } -#ifdef CONFIG_ARM +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV) /* * Some of these functions are needed purely because the functions they * call return void. If we change them to return 0, these stubs can go away. @@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] = { initr_trace, initr_reloc, /* TODO: could x86/PPC have this also perhaps? */ -#ifdef CONFIG_ARM +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV) initr_caches, /* Note: For Freescale LS2 SoCs, new MMU table is created in DDR. * A temporary mapping of IFC high region is since removed, diff --git a/common/hash.c b/common/hash.c index dca23635ab..6277fe65b3 100644 --- a/common/hash.c +++ b/common/hash.c @@ -207,12 +207,25 @@ static int hash_finish_crc32(struct hash_algo *algo, void *ctx, void *dest_buf, return 0; } +#ifdef USE_HOSTCC +# define I_WANT_MD5 1 +#else +# define I_WANT_MD5 CONFIG_IS_ENABLED(MD5) +#endif /* * These are the hash algorithms we support. If we have hardware acceleration * is enable we will use that, otherwise a software version of the algorithm. * Note that algorithm names must be in lower case. */ static struct hash_algo hash_algo[] = { +#if I_WANT_MD5 + { + .name = "md5", + .digest_size = MD5_SUM_LEN, + .chunk_size = CHUNKSZ_MD5, + .hash_func_ws = md5_wd, + }, +#endif #ifdef CONFIG_SHA1 { .name = "sha1", diff --git a/common/image-fit.c b/common/image-fit.c index aa9c781462..5a0a0cc200 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1215,7 +1215,7 @@ int fit_set_timestamp(void *fit, int noffset, time_t timestamp) * 0, on success * -1, when algo is unsupported */ -int calculate_hash(const void *data, int data_len, const char *algo, +int calculate_hash(const void *data, int data_len, const char *name, uint8_t *value, int *value_len) { #if !defined(USE_HOSTCC) && defined(CONFIG_DM_HASH) @@ -1243,35 +1243,19 @@ int calculate_hash(const void *data, int data_len, const char *algo, *value_len = hash_algo_digest_size(hash_algo); #else - if (IMAGE_ENABLE_CRC32 && strcmp(algo, "crc32") == 0) { - *((uint32_t *)value) = crc32_wd(0, data, data_len, - CHUNKSZ_CRC32); - *((uint32_t *)value) = cpu_to_uimage(*((uint32_t *)value)); - *value_len = 4; - } else if (CONFIG_IS_ENABLED(SHA1) && strcmp(algo, "sha1") == 0) { - sha1_csum_wd((unsigned char *)data, data_len, - (unsigned char *)value, CHUNKSZ_SHA1); - *value_len = 20; - } else if (CONFIG_IS_ENABLED(SHA256) && strcmp(algo, "sha256") == 0) { - sha256_csum_wd((unsigned char *)data, data_len, - (unsigned char *)value, CHUNKSZ_SHA256); - *value_len = SHA256_SUM_LEN; - } else if (CONFIG_IS_ENABLED(SHA384) && strcmp(algo, "sha384") == 0) { - sha384_csum_wd((unsigned char *)data, data_len, - (unsigned char *)value, CHUNKSZ_SHA384); - *value_len = SHA384_SUM_LEN; - } else if (CONFIG_IS_ENABLED(SHA512) && strcmp(algo, "sha512") == 0) { - sha512_csum_wd((unsigned char *)data, data_len, - (unsigned char *)value, CHUNKSZ_SHA512); - *value_len = SHA512_SUM_LEN; - } else if (IMAGE_ENABLE_MD5 && strcmp(algo, "md5") == 0) { - md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5); - *value_len = 16; - } else { + struct hash_algo *algo; + int ret; + + ret = hash_lookup_algo(name, &algo); + if (ret < 0) { debug("Unsupported hash alogrithm\n"); return -1; } + + algo->hash_func_ws(data, data_len, value, algo->chunk_size); + *value_len = algo->digest_size; #endif + return 0; } diff --git a/common/image-sig.c b/common/image-sig.c index fb0035524e..fa9407bb30 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -51,19 +51,6 @@ struct checksum_algo checksum_algos[] = { }; -struct padding_algo padding_algos[] = { - { - .name = "pkcs-1.5", - .verify = padding_pkcs_15_verify, - }, -#ifdef CONFIG_FIT_RSASSA_PSS - { - .name = "pss", - .verify = padding_pss_verify, - } -#endif /* CONFIG_FIT_RSASSA_PSS */ -}; - struct checksum_algo *image_get_checksum_algo(const char *full_name) { int i; @@ -129,14 +116,16 @@ struct crypto_algo *image_get_crypto_algo(const char *full_name) struct padding_algo *image_get_padding_algo(const char *name) { - int i; + struct padding_algo *padding, *end; if (!name) return NULL; - for (i = 0; i < ARRAY_SIZE(padding_algos); i++) { - if (!strcmp(padding_algos[i].name, name)) - return &padding_algos[i]; + padding = ll_entry_start(struct padding_algo, paddings); + end = ll_entry_end(struct padding_algo, paddings); + for (; padding < end; padding++) { + if (!strcmp(padding->name, name)) + return padding; } return NULL; diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 34e8a12036..34f6fc2cfa 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -439,48 +439,6 @@ config SPL_MD5 applications where images may be changed maliciously, you should consider SHA256 or SHA384. -config SPL_FIT_SHA1 - bool "Support SHA1" - depends on SPL_FIT - select SHA1 - help - Enable this to support SHA1 in FIT images within SPL. A SHA1 - checksum is a 160-bit (20-byte) hash value used to check that the - image contents have not been corrupted or maliciously altered. - While SHA1 is fairly secure it is coming to the end of its life - due to the expanding computing power available to brute-force - attacks. For more security, consider SHA256 or SHA384. - -config SPL_FIT_SHA256 - bool "Support SHA256" - depends on SPL_FIT - select SHA256 - help - Enable this to support SHA256 in FIT images within SPL. A SHA256 - checksum is a 256-bit (32-byte) hash value used to check that the - image contents have not been corrupted. - -config SPL_FIT_SHA384 - bool "Support SHA384" - depends on SPL_FIT - select SHA384 - select SHA512_ALGO - help - Enable this to support SHA384 in FIT images within SPL. A SHA384 - checksum is a 384-bit (48-byte) hash value used to check that the - image contents have not been corrupted. Use this for the highest - security. - -config SPL_FIT_SHA512 - bool "Support SHA512" - depends on SPL_FIT - select SHA512 - select SHA512_ALGO - help - Enable this to support SHA512 in FIT images within SPL. A SHA512 - checksum is a 512-bit (64-byte) hash value used to check that the - image contents have not been corrupted. - config SPL_FIT_IMAGE_TINY bool "Remove functionality from SPL FIT loading to reduce size" depends on SPL_FIT @@ -519,27 +477,6 @@ config SPL_CRYPTO this option to build the drivers in drivers/crypto as part of an SPL build. -config SPL_HASH_SUPPORT - bool "Support hashing drivers" - select SHA1 - select SHA256 - help - Enable hashing drivers in SPL. These drivers can be used to - accelerate secure boot processing in secure applications. Enable - this option to build system-specific drivers for hash acceleration - as part of an SPL build. - -config TPL_HASH_SUPPORT - bool "Support hashing drivers in TPL" - depends on TPL - select SHA1 - select SHA256 - help - Enable hashing drivers in SPL. These drivers can be used to - accelerate secure boot processing in secure applications. Enable - this option to build system-specific drivers for hash acceleration - as part of an SPL build. - config SPL_DMA bool "Support DMA drivers" help @@ -1228,7 +1165,7 @@ config SPL_USB_ETHER config SPL_DFU bool "Support DFU (Device Firmware Upgrade)" - select SPL_HASH_SUPPORT + select SPL_HASH select SPL_DFU_NO_RESET depends on SPL_RAM_SUPPORT help diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig deleted file mode 100644 index 8ac73d7f06..0000000000 --- a/configs/UCP1020_defconfig +++ /dev/null @@ -1,68 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF80000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_MPC85xx=y -CONFIG_TARGET_UCP1020=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n" -CONFIG_AUTOBOOT_STOP_STR="\x1b" -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_LAST_STAGE_INIT=y -# CONFIG_MISC_INIT_R is not set -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="B$ " -CONFIG_CMD_IMLS=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_PCI is not set -# CONFIG_CMD_SATA is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_CRAMFS=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEC0C0000 -CONFIG_DDR_CLK_FREQ=66666666 -# CONFIG_DDR_SPD is not set -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=400000 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_FS_CRAMFS=y -CONFIG_OF_LIBFDT=y diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index 368d013d45..f0b197a050 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_DNS2=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index 1a87eb04b4..94ea4ecab6 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -33,6 +33,7 @@ CONFIG_BOOTP_DNS2=y CONFIG_CMD_MTDPARTS=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle" CONFIG_ENV_OVERWRITE=y # CONFIG_ENV_IS_IN_FAT is not set diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 71c619bd9f..02e53d01f1 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -100,6 +100,8 @@ CONFIG_CLK_TI_SCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index ec605c030d..f13ece9d0b 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -79,6 +79,7 @@ CONFIG_SPL_CLK=y CONFIG_SPL_CLK_CCF=y CONFIG_SPL_CLK_K3_PLL=y CONFIG_SPL_CLK_K3=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 32eace14ec..df1b850f42 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -96,6 +96,8 @@ CONFIG_CLK_TI_SCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x20000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index c95a37b92c..1a58135da4 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -76,6 +76,7 @@ CONFIG_SPL_CLK=y CONFIG_SPL_CLK_CCF=y CONFIG_SPL_CLK_K3_PLL=y CONFIG_SPL_CLK_K3=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index e3659f5a03..4e25dafaaf 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -80,7 +80,6 @@ CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MSCC_FELIX_SWITCH=y CONFIG_NVME=y -CONFIG_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_RV8803=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index e63fd634fb..561a39044a 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -41,8 +41,6 @@ CONFIG_ID_EEPROM=y CONFIG_SPL_FSL_PBL=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 -CONFIG_SPL_CRYPTO=y -CONFIG_SPL_HASH_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 6a11a7c4ad..8e47f81277 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -30,8 +30,6 @@ CONFIG_MISC_INIT_R=y CONFIG_SPL_FSL_PBL=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0 -CONFIG_SPL_CRYPTO=y -CONFIG_SPL_HASH_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_NAND_SUPPORT=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 8934add4c8..fef8121da7 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -30,8 +30,6 @@ CONFIG_MISC_INIT_R=y CONFIG_SPL_FSL_PBL=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 -CONFIG_SPL_CRYPTO=y -CONFIG_SPL_HASH_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_WATCHDOG=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 36b91a05fb..c4a9315890 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -33,8 +33,6 @@ CONFIG_MISC_INIT_R=y CONFIG_SPL_FSL_PBL=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 -CONFIG_SPL_CRYPTO=y -CONFIG_SPL_HASH_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 3efea9e3ae..7301a09b4d 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -33,8 +33,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 -CONFIG_SPL_CRYPTO=y -CONFIG_SPL_HASH_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MPC8XXX_INIT_DDR=y diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig index 6888dbd55d..a6fe5c1bca 100644 --- a/configs/malta64_defconfig +++ b/configs/malta64_defconfig @@ -30,6 +30,5 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PCNET=y -CONFIG_PCI=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig index c533cf400b..909b3647f7 100644 --- a/configs/malta64el_defconfig +++ b/configs/malta64el_defconfig @@ -32,6 +32,5 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PCNET=y -CONFIG_PCI=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y diff --git a/configs/malta_defconfig b/configs/malta_defconfig index 31c4044e6e..0af4617105 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -29,6 +29,5 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PCNET=y -CONFIG_PCI=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index bec322180b..1564e92251 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -31,6 +31,5 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_PCNET=y -CONFIG_PCI=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y diff --git a/configs/mt8516_pumpkin_defconfig b/configs/mt8516_pumpkin_defconfig index 693ce9a5c4..c0786bd98e 100644 --- a/configs/mt8516_pumpkin_defconfig +++ b/configs/mt8516_pumpkin_defconfig @@ -14,7 +14,6 @@ CONFIG_DEBUG_UART_CLOCK=26000000 CONFIG_DEBUG_UART=y CONFIG_SYS_LOAD_ADDR=0x4c000000 CONFIG_FIT=y -# CONFIG_FIT_SHA256 is not set # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_DEFAULT_FDT_FILE="mt8516-pumpkin" # CONFIG_DISPLAY_BOARDINFO is not set @@ -74,4 +73,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d CONFIG_USB_GADGET_PRODUCT_NUM=0x201c CONFIG_WDT=y CONFIG_WDT_MTK=y +# CONFIG_SHA256 is not set # CONFIG_EFI_LOADER is not set diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 50695ea21b..d401f4765f 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -64,7 +64,6 @@ CONFIG_PHY=y CONFIG_MVEBU_COMPHY_SUPPORT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ARMADA_37XX=y -CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_MVEBU_A3700_UART=y CONFIG_MVEBU_A3700_SPI=y @@ -77,4 +76,3 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_SHA1=y -CONFIG_SHA256=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index a3fb223da7..01cf24aec9 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -27,10 +27,12 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y +CONFIG_CMD_SATA=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y @@ -47,6 +49,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_AHCI_PCI=y CONFIG_AHCI_MVEBU=y CONFIG_CLK=y CONFIG_CLK_MVEBU=y @@ -78,7 +81,6 @@ CONFIG_MVEBU_COMPHY_SUPPORT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ARMADA_37XX=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_MVEBU_A3700_UART=y CONFIG_MVEBU_A3700_SPI=y diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig index 85148839f3..2defa119ed 100644 --- a/configs/mx6memcal_defconfig +++ b/configs/mx6memcal_defconfig @@ -43,4 +43,3 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_FSL_USDHC=y CONFIG_MXC_UART=y CONFIG_OF_LIBFDT=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 81f1534926..66aa34281e 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -67,7 +67,6 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y -CONFIG_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index bebd1de771..9a86beb6b4 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -10,6 +10,7 @@ CONFIG_TARGET_OMAP3_EVM=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run envboot; run distro_bootcmd" CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index 91fd8e7e3b..da7a4d2c80 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -12,6 +12,7 @@ CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +CONFIG_CMD_SBI=y # CONFIG_CMD_MII is not set CONFIG_OF_PRIOR_STAGE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 5cf72d74d4..96f2e3ae5d 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -13,6 +13,7 @@ CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +CONFIG_CMD_SBI=y # CONFIG_CMD_MII is not set CONFIG_OF_PRIOR_STAGE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/r8a774a1_beacon_defconfig b/configs/r8a774a1_beacon_defconfig index fb6a831a66..4e52dd0070 100644 --- a/configs/r8a774a1_beacon_defconfig +++ b/configs/r8a774a1_beacon_defconfig @@ -20,7 +20,9 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -49,6 +51,10 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_BITBANGMII=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y @@ -58,6 +64,9 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_SCIF_CONSOLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/r8a774b1_beacon_defconfig b/configs/r8a774b1_beacon_defconfig index 96160567d9..deb0d0e15e 100644 --- a/configs/r8a774b1_beacon_defconfig +++ b/configs/r8a774b1_beacon_defconfig @@ -20,7 +20,9 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -50,7 +52,9 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_RENESAS_SDHI=y CONFIG_MTD=y +CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_BITBANGMII=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y diff --git a/configs/r8a774e1_beacon_defconfig b/configs/r8a774e1_beacon_defconfig index 098e41fe9c..92d0899e9a 100644 --- a/configs/r8a774e1_beacon_defconfig +++ b/configs/r8a774e1_beacon_defconfig @@ -20,7 +20,9 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -49,6 +51,10 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_BITBANGMII=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y @@ -58,6 +64,9 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_SCIF_CONSOLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 7d45fbffc7..55646550d3 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00" CONFIG_SPL_MMC=y CONFIG_SPL=y CONFIG_SPL_SPI=y +CONFIG_AHCI=y CONFIG_TARGET_SIFIVE_UNMATCHED=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y @@ -30,6 +31,8 @@ CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_SPL_CLK=y CONFIG_SYS_I2C_EEPROM_ADDR=0x54 CONFIG_E1000=y @@ -37,6 +40,8 @@ CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCIE_DW_SIFIVE=y CONFIG_DM_RESET=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 9188c1833c..82ad68b6a1 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -12,6 +12,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="armada-3720-turris-mox" CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -29,10 +30,12 @@ CONFIG_CMD_SHA1SUM=y CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y +CONFIG_CMD_SATA=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y @@ -48,6 +51,8 @@ CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y CONFIG_CLK=y @@ -82,7 +87,8 @@ CONFIG_PINCTRL_ARMADA_37XX=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SCSI=y +CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_MVEBU_A3700_UART=y CONFIG_MVEBU_A3700_SPI=y diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index 0a26f401e1..4d080baa14 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -35,12 +35,14 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_I2C=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y CONFIG_CMD_LZMADEC=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y @@ -79,6 +81,7 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y CONFIG_MII=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_PCI_MVEBU=y CONFIG_DM_RTC=y diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index 202c5639bb..a06a25378e 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -80,7 +80,6 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_ARMADA_37XX=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_MVEBU_A3700_UART=y CONFIG_MVEBU_A3700_SPI=y diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 1dbed04871..ffa17e44ca 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -57,4 +57,3 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set CONFIG_ARM_DCC=y # CONFIG_GZIP is not set -# CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index 736586edbb..a831bac020 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -58,4 +58,3 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ARM_DCC=y CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set -# CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index 533ba37330..8cc90c6b41 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -58,4 +58,3 @@ CONFIG_SYS_NAND_MAX_CHIPS=2 CONFIG_ARM_DCC=y CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set -# CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig index 34fd347232..fe467f3151 100644 --- a/configs/xilinx_zynqmp_mini_nand_single_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig @@ -57,4 +57,3 @@ CONFIG_NAND_ARASAN=y CONFIG_ARM_DCC=y CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set -# CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index ea379e240e..8958e3f4d3 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -67,4 +67,3 @@ CONFIG_SPI=y CONFIG_ZYNQMP_GQSPI=y CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set -# CONFIG_EFI_LOADER is not set diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index 01aad948eb..7774b27519 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -62,4 +62,3 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ZYNQ=y CONFIG_ARM_DCC=y # CONFIG_GZIP is not set -# CONFIG_EFI_LOADER is not set diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index 6311989ad9..a74dcc0568 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -64,4 +64,3 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_ARM_DCC=y # CONFIG_GZIP is not set -# CONFIG_EFI_LOADER is not set diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 81cf5c683b..99aaa1a5e8 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -75,4 +75,3 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_ARM_DCC=y CONFIG_ZYNQ_QSPI=y # CONFIG_GZIP is not set -# CONFIG_EFI_LOADER is not set diff --git a/doc/board/toradex/apalix-imx8.rst b/doc/board/toradex/apalis-imx8.rst index 29593faf1a..29593faf1a 100644 --- a/doc/board/toradex/apalix-imx8.rst +++ b/doc/board/toradex/apalis-imx8.rst diff --git a/doc/board/toradex/apalix-imx8x.rst b/doc/board/toradex/apalis-imx8x.rst index e62578b152..e62578b152 100644 --- a/doc/board/toradex/apalix-imx8x.rst +++ b/doc/board/toradex/apalis-imx8x.rst diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst index abba648f86..5652848019 100644 --- a/doc/board/toradex/index.rst +++ b/doc/board/toradex/index.rst @@ -6,8 +6,8 @@ Toradex .. toctree:: :maxdepth: 2 - apalix-imx8 - apalix-imx8x + apalis-imx8 + apalis-imx8x colibri_imx7 colibri-imx8x verdin-imx8mm diff --git a/doc/README.bloblist b/doc/develop/bloblist.rst index 274c460557..317ebc4919 100644 --- a/doc/README.bloblist +++ b/doc/develop/bloblist.rst @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0+ +.. SPDX-License-Identifier: GPL-2.0+ Blob Lists - bloblist ===================== @@ -39,7 +39,7 @@ Blob tags Each blob has a tag which is a 32-bit number. This uniquely identifies the owner of the blob. Blob tags are listed in enum blob_tag_t and are named -with a BLOBT_ prefix. +with a `BLOBT_` prefix. Single structure diff --git a/doc/develop/index.rst b/doc/develop/index.rst index a7e625562c..827b115abc 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -9,6 +9,7 @@ Implementation .. toctree:: :maxdepth: 1 + bloblist ci_testing commands devicetree/index diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index 64fe9346c7..f17138f5c7 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -392,7 +392,6 @@ settings:: CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT=y CONFIG_EFI_CAPSULE_FIRMWARE=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y - CONFIG_EFI_CAPSULE_FMP_HEADER=y In addition, the following config needs to be disabled(QEMU ARM specific):: diff --git a/doc/device-tree-bindings/config.txt b/doc/device-tree-bindings/config.txt index 6cdc16da5b..85379fbbe5 100644 --- a/doc/device-tree-bindings/config.txt +++ b/doc/device-tree-bindings/config.txt @@ -5,15 +5,39 @@ A number of run-time configuration options are provided in the /config node of the control device tree. You can access these using fdtdec_get_config_int(), fdtdec_get_config_bool() and fdtdec_get_config_string(). +These options are designed to affect the operation of U-Boot at runtime. +Runtime-configuration items can help avoid proliferation of different builds +with only minor changes, e.g. enabling and disabling console output. Items +here should be those that can usefully be set by the build system after U-Boot +is built. + Available options are: -silent-console - If present and non-zero, the console is silenced by default on boot. +bootcmd (string) + Allows overwriting of the boot command used by U-Boot on startup. If + present, U-Boot uses this command instead. Note that this feature can + work even if loading the environment is disabled, e.g. for security + reasons. See also bootsecure. + +bootdelay (int) + This allows selecting of the U-Boot bootdelay, to control whether U-Boot + waits on boot or for how long. This allows this option to be configured + by the build system or by a previous-stage binary. For example, if the + images is being packed for testing or a user holds down a button, it may + allow a delay, but disable it for production. -no-keyboard - Tells U-Boot not to expect an attached keyboard with a VGA console +u-boot,boot-led (string) +u-boot,error-led (string) + This is used to specify the label for an LED to indicate an error and + a successful boot, on supported hardware. -u-boot,efi-partition-entries-offset +bootsecure (int) + Indicates that U-Boot should use secure_boot_cmd() to run commands, + rather than the normal CLI. This can be used in production images, to + restrict the amount of parsing done or the options available, to cut + back on the available surface for security attacks. + +u-boot,efi-partition-entries-offset (int) If present, this provides an offset (in bytes, from the start of a device) that should be skipped over before the partition entries. This is used by the EFI/GPT partition implementation when a device @@ -21,17 +45,18 @@ u-boot,efi-partition-entries-offset This setting will override any values configured via Kconfig. -u-boot,mmc-env-partition - if present, the environment shall be placed at the last - CONFIG_ENV_SIZE blocks of the partition on the - CONFIG_SYS_MMC_ENV_DEV. +kernel-offset (int) + This allows setting the 'kernaddr' environment variable, used to select + the address to load the kernel. It is useful for systems that use U-Boot + to flash a device, so the scripts that do this know where to put the + kernel to be flashed. - if u-boot,mmc-env-offset* is present, this setting will take - precedence. In that case, only if the partition is not found, - mmc-env-offset* will be tried. +load-environment (int) + Allows control over whether U-Boot loads its environment after + relocation (0=no, 1 or not present=yes). -u-boot,mmc-env-offset -u-boot,mmc-env-offset-redundant +u-boot,mmc-env-offset (int) +u-boot,mmc-env-offset-redundant (int) If present, the values of the 'u-boot,mmc-env-offset' and/or of the u-boot,mmc-env-offset-redundant' properties overrides CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND, respectively, @@ -42,12 +67,38 @@ u-boot,mmc-env-offset-redundant will point at the beginning of a LBA and values that are not LBA-aligned will be rounded up to the next LBA address. -u-boot,spl-payload-offset +u-boot,mmc-env-partition (int) + if present, the environment shall be placed at the last + CONFIG_ENV_SIZE blocks of the partition on the + CONFIG_SYS_MMC_ENV_DEV. + + if u-boot,mmc-env-offset* is present, this setting will take + precedence. In that case, only if the partition is not found, + mmc-env-offset* will be tried. + +u-boot,no-apm-finalize (bool) + For x86 devices running on coreboot, this tells U-Boot not to lock + down the Intel Management Engine (ME) registers. This allows U-Boot to + access the hardware more fully for platforms that need it. + +u-boot,no-keyboard (bool) + Tells U-Boot not to expect an attached keyboard with a VGA console. + +rootdisk-offset (int) + This allows setting the 'rootdisk' environment variable, used to select + the address to load the rootdisk. It is useful for systems that use + U-Boot to flash a device, so the scripts that do this know where to put + the root disk to be flashed. + +silent-console (int) + If present and non-zero, the console is silenced by default on boot. + +u-boot,spl-payload-offset (int) If present (and SPL is controlled by the device-tree), this allows to override the CONFIG_SYS_SPI_U_BOOT_OFFS setting using a value from the device-tree. -sysreset-gpio +sysreset-gpio (string) If present (and supported by the specific board), indicates a GPIO that can be set to trigger a system reset. It is assumed that such a system reset will effect a complete platform reset, diff --git a/doc/git-mailrc b/doc/git-mailrc index 001681c899..410be387be 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -74,7 +74,7 @@ alias socfpga uboot, marex, dinh, simongoldschmidt, tienfong alias sunxi uboot, jagan, apritzel alias tegra uboot, sjg, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com> alias tegra2 tegra -alias ti uboot, lokeshvutla +alias ti uboot, trini alias uniphier uboot, masahiro alias zynq uboot, monstr alias rockchip uboot, sjg, kevery, ptomsich diff --git a/doc/usage/mmc.rst b/doc/usage/mmc.rst index f20efe3d70..d15b151884 100644 --- a/doc/usage/mmc.rst +++ b/doc/usage/mmc.rst @@ -12,9 +12,9 @@ Synopsis mmc read addr blk# cnt mmc write addr blk# cnt mmc erase blk# cnt - mmc rescan + mmc rescan [mode] mmc part - mmc dev [dev] [part] + mmc dev [dev] [part] [mode] mmc list mmc wp mmc bootbus <dev> <boot_bus_width> <reset_boot_bus_width> <boot_mode> @@ -49,6 +49,27 @@ The 'mmc erase' command erases *cnt* blocks on the MMC device starting at block The 'mmc rescan' command scans the available MMC device. + mode + speed mode to set. + CONFIG_MMC_SPEED_MODE_SET should be enabled. The required speed mode is + passed as the index from the following list. + + 0 - MMC_LEGACY + 1 - MMC_HS + 2 - SD_HS + 3 - MMC_HS_52 + 4 - MMC_DDR_52 + 5 - UHS_SDR12 + 6 - UHS_SDR25 + 7 - UHS_SDR50 + 8 - UHS_DDR50 + 9 - UHS_SDR104 + 10 - MMC_HS_200 + 11 - MMC_HS_400 + 12 - MMC_HS_400_ES + + A speed mode can be set only if it has already been enabled in the device tree + The 'mmc part' command displays the list available partition on current mmc device. The 'mmc dev' command shows or set current mmc device. @@ -58,6 +79,27 @@ The 'mmc dev' command shows or set current mmc device. part partition number to change + mode + speed mode to set. + CONFIG_MMC_SPEED_MODE_SET should be enabled. The required speed mode is + passed as the index from the following list. + + 0 - MMC_LEGACY + 1 - MMC_HS + 2 - SD_HS + 3 - MMC_HS_52 + 4 - MMC_DDR_52 + 5 - UHS_SDR12 + 6 - UHS_SDR25 + 7 - UHS_SDR50 + 8 - UHS_DDR50 + 9 - UHS_SDR104 + 10 - MMC_HS_200 + 11 - MMC_HS_400 + 12 - MMC_HS_400_ES + + A speed mode can be set only if it has already been enabled in the device tree + The 'mmc list' command displays the list available devices. The 'mmc wp' command enables "power on write protect" function for boot partitions. @@ -194,6 +236,9 @@ The current device can be shown or set via 'mmc dev' command: => mmc dev 2 0 switch to partitions #0, OK mmc2 is current device + => mmc dev 0 1 4 + switch to partitions #1, OK + mmc0(part 1) is current device The list of available devices can be shown via 'mmc list' command: :: diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index d4047c04f5..2062197afc 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -170,13 +170,8 @@ int ahci_reset(void __iomem *base) static int ahci_host_init(struct ahci_uc_priv *uc_priv) { #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) -# ifdef CONFIG_DM_PCI struct udevice *dev = uc_priv->dev; struct pci_child_plat *pplat = dev_get_parent_plat(dev); -# else - pci_dev_t pdev = uc_priv->dev; - unsigned short vendor; -# endif u16 tmp16; #endif void __iomem *mmio = uc_priv->mmio_base; @@ -200,23 +195,12 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv) writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) -# ifdef CONFIG_DM_PCI if (pplat->vendor == PCI_VENDOR_ID_INTEL) { u16 tmp16; dm_pci_read_config16(dev, 0x92, &tmp16); dm_pci_write_config16(dev, 0x92, tmp16 | 0xf); } -# else - pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); - - if (vendor == PCI_VENDOR_ID_INTEL) { - u16 tmp16; - pci_read_config_word(pdev, 0x92, &tmp16); - tmp16 |= 0xf; - pci_write_config_word(pdev, 0x92, tmp16); - } -# endif #endif uc_priv->cap = readl(mmio + HOST_CAP); uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL); @@ -331,15 +315,9 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv) debug("HOST_CTL 0x%x\n", tmp); #if !defined(CONFIG_DM_SCSI) #ifndef CONFIG_SCSI_AHCI_PLAT -# ifdef CONFIG_DM_PCI dm_pci_read_config16(dev, PCI_COMMAND, &tmp16); tmp |= PCI_COMMAND_MASTER; dm_pci_write_config16(dev, PCI_COMMAND, tmp16); -# else - pci_read_config_word(pdev, PCI_COMMAND, &tmp16); - tmp |= PCI_COMMAND_MASTER; - pci_write_config_word(pdev, PCI_COMMAND, tmp16); -# endif #endif #endif return 0; @@ -349,11 +327,7 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv) static void ahci_print_info(struct ahci_uc_priv *uc_priv) { #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) -# if defined(CONFIG_DM_PCI) struct udevice *dev = uc_priv->dev; -# else - pci_dev_t pdev = uc_priv->dev; -# endif u16 cc; #endif void __iomem *mmio = uc_priv->mmio_base; @@ -379,11 +353,7 @@ static void ahci_print_info(struct ahci_uc_priv *uc_priv) #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI) scc_s = "SATA"; #else -# ifdef CONFIG_DM_PCI dm_pci_read_config16(dev, 0x0a, &cc); -# else - pci_read_config_word(pdev, 0x0a, &cc); -# endif if (cc == 0x0101) scc_s = "IDE"; else if (cc == 0x0106) @@ -428,11 +398,7 @@ static void ahci_print_info(struct ahci_uc_priv *uc_priv) } #if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT) -# if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI) static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev) -# else -static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev) -# endif { #if !defined(CONFIG_DM_SCSI) u16 vendor; @@ -450,7 +416,6 @@ static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev) uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ #if !defined(CONFIG_DM_SCSI) -#ifdef CONFIG_DM_PCI uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5, PCI_REGION_MEM); @@ -462,18 +427,6 @@ static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev) if (vendor == 0x197b) dm_pci_write_config8(dev, 0x41, 0xa1); #else - uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5, - PCI_REGION_MEM); - - /* Take from kernel: - * JMicron-specific fixup: - * make sure we're in AHCI mode - */ - pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); - if (vendor == 0x197b) - pci_write_config_byte(dev, 0x41, 0xa1); -#endif -#else struct scsi_plat *plat = dev_get_uclass_plat(dev); uc_priv->mmio_base = (void *)plat->base; #endif @@ -1006,7 +959,6 @@ void scsi_low_level_init(int busdevfunc) return; } uc_priv = probe_ent; -# if defined(CONFIG_DM_PCI) struct udevice *dev; int ret; @@ -1014,9 +966,6 @@ void scsi_low_level_init(int busdevfunc) if (ret) return; ahci_init_one(uc_priv, dev); -# else - ahci_init_one(uc_priv, busdevfunc); -# endif #else uc_priv = probe_ent; #endif @@ -1026,7 +975,6 @@ void scsi_low_level_init(int busdevfunc) #endif #ifndef CONFIG_SCSI_AHCI_PLAT -# if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI) int ahci_init_one_dm(struct udevice *dev) { struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); @@ -1034,7 +982,6 @@ int ahci_init_one_dm(struct udevice *dev) return ahci_init_one(uc_priv, dev); } #endif -#endif int ahci_start_ports_dm(struct udevice *dev) { @@ -1196,7 +1143,6 @@ int ahci_probe_scsi(struct udevice *ahci_dev, ulong base) return 0; } -#ifdef CONFIG_DM_PCI int ahci_probe_scsi_pci(struct udevice *ahci_dev) { ulong base; @@ -1221,7 +1167,6 @@ int ahci_probe_scsi_pci(struct udevice *ahci_dev) PCI_REGION_MEM); return ahci_probe_scsi(ahci_dev, base); } -#endif struct scsi_ops scsi_ops = { .exec = ahci_scsi_exec, diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index dadb2c7c2e..003222d47b 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -1068,6 +1068,7 @@ static int sata_mv_probe(struct udevice *dev) int nr_ports; int ret; int i; + int status = -ENODEV; /* If the probe fails to detected any SATA port */ /* Get number of ports of this SATA controller */ nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1), @@ -1078,7 +1079,7 @@ static int sata_mv_probe(struct udevice *dev) IF_TYPE_SATA, -1, 512, 0, &blk); if (ret) { debug("Can't create device\n"); - return ret; + continue; } priv = dev_get_plat(blk); @@ -1088,18 +1089,23 @@ static int sata_mv_probe(struct udevice *dev) ret = sata_mv_init_sata(blk, i); if (ret) { debug("%s: Failed to init bus\n", __func__); - return ret; + continue; } /* Scan SATA port */ ret = sata_mv_scan_sata(blk, i); if (ret) { debug("%s: Failed to scan bus\n", __func__); - return ret; + continue; } + + /* If we got here, the current SATA port was probed + * successfully, so set the probe status to successful. + */ + status = 0; } - return 0; + return status; } static int sata_mv_scan(struct udevice *dev) diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 1e452ad6d9..40f41a817c 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -39,4 +39,11 @@ config NCORE_CACHE controller. The driver initializes cache directories and coherent agent interfaces. +config SIFIVE_CCACHE + bool "SiFive composable cache" + select CACHE + help + This driver is for SiFive Composable L2/L3 cache. It enables cache + ways of composable cache. + endmenu diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index fed50be3f9..ad765774e3 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_SANDBOX) += sandbox_cache.o obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o +obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o diff --git a/drivers/cache/cache-sifive-ccache.c b/drivers/cache/cache-sifive-ccache.c new file mode 100644 index 0000000000..76c0ab26ae --- /dev/null +++ b/drivers/cache/cache-sifive-ccache.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 SiFive + */ + +#include <common.h> +#include <cache.h> +#include <dm.h> +#include <asm/io.h> +#include <dm/device.h> +#include <linux/bitfield.h> + +#define SIFIVE_CCACHE_CONFIG 0x000 +#define SIFIVE_CCACHE_CONFIG_WAYS GENMASK(15, 8) + +#define SIFIVE_CCACHE_WAY_ENABLE 0x008 + +struct sifive_ccache { + void __iomem *base; +}; + +static int sifive_ccache_enable(struct udevice *dev) +{ + struct sifive_ccache *priv = dev_get_priv(dev); + u32 config; + u32 ways; + + /* Enable all ways of composable cache */ + config = readl(priv->base + SIFIVE_CCACHE_CONFIG); + ways = FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS, config); + + writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE); + + return 0; +} + +static int sifive_ccache_get_info(struct udevice *dev, struct cache_info *info) +{ + struct sifive_ccache *priv = dev_get_priv(dev); + + info->base = (phys_addr_t)priv->base; + + return 0; +} + +static const struct cache_ops sifive_ccache_ops = { + .enable = sifive_ccache_enable, + .get_info = sifive_ccache_get_info, +}; + +static int sifive_ccache_probe(struct udevice *dev) +{ + struct sifive_ccache *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + return 0; +} + +static const struct udevice_id sifive_ccache_ids[] = { + { .compatible = "sifive,fu540-c000-ccache" }, + { .compatible = "sifive,fu740-c000-ccache" }, + {} +}; + +U_BOOT_DRIVER(sifive_ccache) = { + .name = "sifive_ccache", + .id = UCLASS_CACHE, + .of_match = sifive_ccache_ids, + .probe = sifive_ccache_probe, + .priv_auto = sizeof(struct sifive_ccache), + .ops = &sifive_ccache_ops, +}; diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 1f5dfb94bb..94ff540111 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -1,6 +1,8 @@ config FSL_CAAM bool "Freescale Crypto Driver Support" select SHA_HW_ACCEL + # hw_sha1() under drivers/crypto, and needed with SHA_HW_ACCEL + imply SPL_CRYPTO if (ARM && SPL) imply CMD_HASH help Enables the Freescale's Cryptographic Accelerator and Assurance diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index afb4c69529..f0439e2417 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -360,7 +360,7 @@ config PIC32_GPIO config OCTEON_GPIO bool "Octeon II/III/TX/TX2 GPIO driver" - depends on DM_GPIO && DM_PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) + depends on DM_GPIO && PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) default y help Add support for the Marvell Octeon GPIO driver. This is used with diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 3a7ecd9274..67841bf3e0 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -18,7 +18,7 @@ obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o -ifdef CONFIG_DM_PCI +ifdef CONFIG_PCI obj-$(CONFIG_SYS_I2C_DW) += designware_i2c_pci.o endif obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o diff --git a/drivers/i2c/ocores_i2c.c b/drivers/i2c/ocores_i2c.c index 088ba9a6a3..f129ec3818 100644 --- a/drivers/i2c/ocores_i2c.c +++ b/drivers/i2c/ocores_i2c.c @@ -626,6 +626,7 @@ static const struct udevice_id ocores_i2c_ids[] = { { .compatible = "aeroflexgaisler,i2cmst", .data = TYPE_GRLIB }, { .compatible = "sifive,fu540-c000-i2c" }, { .compatible = "sifive,i2c0" }, +{ } }; U_BOOT_DRIVER(i2c_ocores) = { diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 1d98fa65c4..ebb307e950 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -361,13 +361,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) ; - /* Wait at least 8 SD clock cycles before the next command */ - /* - * Note: This is way more than 8 cycles, but 1ms seems to - * resolve timing issues with some cards - */ - udelay(1000); - /* Set up for a data transfer if we have one */ if (data) { err = esdhc_setup_data(priv, mmc, data); diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index 0e13238c7e..3ee92d03ca 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -342,6 +342,9 @@ void mmc_do_preinit(void) if (!m) continue; + + m->user_speed_mode = MMC_MODES_END; /* Initialising user set speed mode */ + if (m->preinit) mmc_start_init(m); } @@ -414,7 +417,7 @@ int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg) /* setup initial part type */ bdesc->part_type = cfg->part_type; mmc->dev = dev; - + mmc->user_speed_mode = MMC_MODES_END; return 0; } diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 8078a89f18..d3babbfeb1 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -823,7 +823,7 @@ static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value, * capable of polling by using mmc_wait_dat0, then rely on waiting the * stated timeout to be sufficient. */ - if (ret == -ENOSYS && !send_status) { + if (ret == -ENOSYS || !send_status) { mdelay(timeout_ms); return 0; } @@ -2092,14 +2092,16 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) } #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ - CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) /* * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode * before doing anything else, since a transition from either of * the HS200/HS400 mode directly to legacy mode is not supported. */ if (mmc->selected_mode == MMC_HS_200 || - mmc->selected_mode == MMC_HS_400) + mmc->selected_mode == MMC_HS_400 || + mmc->selected_mode == MMC_HS_400_ES) mmc_set_card_speed(mmc, MMC_HS, true); else #endif @@ -2862,7 +2864,25 @@ int mmc_start_init(struct mmc *mmc) * timings. */ mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(MMC_LEGACY) | - MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT; + MMC_MODE_1BIT; + + if (IS_ENABLED(CONFIG_MMC_SPEED_MODE_SET)) { + if (mmc->user_speed_mode != MMC_MODES_END) { + int i; + /* set host caps */ + if (mmc->host_caps & MMC_CAP(mmc->user_speed_mode)) { + /* Remove all existing speed capabilities */ + for (i = MMC_LEGACY; i < MMC_MODES_END; i++) + mmc->host_caps &= ~MMC_CAP(i); + mmc->host_caps |= (MMC_CAP(mmc->user_speed_mode) + | MMC_CAP(MMC_LEGACY) | + MMC_MODE_1BIT); + } else { + pr_err("bus_mode requested is not supported\n"); + return -EINVAL; + } + } + } #if CONFIG_IS_ENABLED(DM_MMC) mmc_deferred_probe(mmc); #endif @@ -2952,7 +2972,7 @@ int mmc_deinit(struct mmc *mmc) return sd_select_mode_and_width(mmc, caps_filtered); } else { caps_filtered = mmc->card_caps & - ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400)); + ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400) | MMC_CAP(MMC_HS_400_ES)); return mmc_select_mode_and_width(mmc, caps_filtered); } @@ -3060,6 +3080,8 @@ int mmc_init_device(int num) } m = mmc_get_mmc_dev(dev); + m->user_speed_mode = MMC_MODES_END; /* Initialising user set speed mode */ + if (!m) return 0; if (m->preinit) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 2f78da61be..03bfd9d18a 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -258,8 +258,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, flags = SDHCI_CMD_RESP_LONG; else if (cmd->resp_type & MMC_RSP_BUSY) { flags = SDHCI_CMD_RESP_SHORT_BUSY; - if (data) - mask |= SDHCI_INT_DATA_END; + mask |= SDHCI_INT_DATA_END; } else flags = SDHCI_CMD_RESP_SHORT; diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 178b8cf106..aaab0cf866 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -349,10 +349,14 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc, * register without checking the status register after every * read. That saves half of the costly MMIO reads, effectively * doubling the read performance. + * Some SoCs (A20) report a level of 0 if the FIFO is + * completely full (value masked out?). Use a safe minimal + * FIFO size in this case. */ - for (in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status); - in_fifo > 0; - in_fifo--) + in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status); + if (in_fifo == 0 && (status & SUNXI_MMC_STATUS_FIFO_FULL)) + in_fifo = 32; + for (; in_fifo > 0; in_fifo--) buff[i++] = readl_relaxed(&priv->reg->fifo); dmb(); } diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 8b1add19e8..6c12959f37 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -225,7 +225,6 @@ config DWC_ETH_QOS_TEGRA186 config E1000 bool "Intel PRO/1000 Gigabit Ethernet support" - depends on (DM_ETH && DM_PCI) || !DM_ETH help This driver supports Intel(R) PRO/1000 gigabit ethernet family of adapters. For more information on how to identify your adapter, go @@ -509,7 +508,7 @@ config OCTEONTX2_CGX_INTF config PCH_GBE bool "Intel Platform Controller Hub EG20T GMAC driver" - depends on DM_ETH && DM_PCI + depends on DM_ETH select PHYLIB help This MAC is present in Intel Platform Controller Hub EG20T. It @@ -608,7 +607,6 @@ source "drivers/net/ti/Kconfig" config TULIP bool "DEC Tulip DC2114x Ethernet support" - depends on (DM_ETH && DM_PCI) || !DM_ETH help This driver supports DEC DC2114x Fast ethernet chips. @@ -791,7 +789,7 @@ config HIGMACV300_ETH config FSL_ENETC bool "NXP ENETC Ethernet controller" - depends on DM_PCI && DM_ETH && DM_MDIO + depends on DM_ETH && DM_MDIO help This driver supports the NXP ENETC Ethernet controller found on some of the NXP SoCs. diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 5d92257e74..5aaac603a0 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -756,16 +756,16 @@ int designware_eth_write_hwaddr(struct udevice *dev) static int designware_eth_bind(struct udevice *dev) { -#ifdef CONFIG_DM_PCI - static int num_cards; - char name[20]; - - /* Create a unique device name for PCI type devices */ - if (device_is_on_pci_bus(dev)) { - sprintf(name, "eth_designware#%u", num_cards++); - device_set_name(dev, name); + if (IS_ENABLED(CONFIG_PCI)) { + static int num_cards; + char name[20]; + + /* Create a unique device name for PCI type devices */ + if (device_is_on_pci_bus(dev)) { + sprintf(name, "eth_designware#%u", num_cards++); + device_set_name(dev, name); + } } -#endif return 0; } @@ -831,12 +831,11 @@ int designware_eth_probe(struct udevice *dev) else reset_deassert_bulk(&reset_bulk); -#ifdef CONFIG_DM_PCI /* * If we are on PCI bus, either directly attached to a PCI root port, * or via a PCI bridge, fill in plat before we probe the hardware. */ - if (device_is_on_pci_bus(dev)) { + if (IS_ENABLED(CONFIG_PCI) && device_is_on_pci_bus(dev)) { dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); iobase &= PCI_BASE_ADDRESS_MEM_MASK; iobase = dm_pci_mem_to_phys(dev, iobase); @@ -844,7 +843,6 @@ int designware_eth_probe(struct udevice *dev) pdata->iobase = iobase; pdata->phy_interface = PHY_INTERFACE_MODE_RMII; } -#endif debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); ioaddr = iobase; diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig index ccf7822dbe..930d2ef113 100644 --- a/drivers/net/mscc_eswitch/Kconfig +++ b/drivers/net/mscc_eswitch/Kconfig @@ -39,7 +39,7 @@ config MSCC_SERVAL_SWITCH config MSCC_FELIX_SWITCH bool "Felix switch driver" - depends on DM_DSA && DM_PCI + depends on DM_DSA select FSL_ENETC help This driver supports the Ethernet switch integrated in the diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 97d0de5b11..e93518ebc1 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -2,28 +2,20 @@ menuconfig PCI bool "PCI support" depends on DM default y if PPC - select DM_PCI help Enable support for PCI (Peripheral Interconnect Bus), a type of bus used on some devices to allow the CPU to communicate with its peripherals. -config DM_PCI - bool - help - Use driver model for PCI. Driver model is the new method for - orgnising devices in U-Boot. For PCI, driver model keeps track of - available PCI devices, allows scanning of PCI buses and provides - device configuration support. + This subsystem requires driver model. if PCI config DM_PCI_COMPAT bool "Enable compatible functions for PCI" - depends on DM_PCI help Enable compatibility functions for PCI so that old code can be used - with CONFIG_DM_PCI enabled. This should be used as an interim + with CONFIG_PCI enabled. This should be used as an interim measure when porting a board to use driver model for PCI. Once the board is fully supported, this option should be disabled. @@ -39,7 +31,6 @@ config PCI_AARDVARK config PCI_PNP bool "Enable Plug & Play support for PCI" - depends on PCI || DM_PCI default y help Enable PCI memory and I/O space resource allocation and assignment. @@ -55,7 +46,6 @@ config PCI_REGION_MULTI_ENTRY config PCI_MAP_SYSTEM_MEMORY bool "Map local system memory from a virtual base address" - depends on PCI || DM_PCI depends on MIPS help Say Y if base address of system memory is being used as a virtual address @@ -102,14 +92,12 @@ config PCIE_ECAM_SYNQUACER config PCI_PHYTIUM bool "Phytium PCIe support" - depends on DM_PCI help Say Y here if you want to enable PCIe controller support on Phytium SoCs. config PCIE_DW_MVEBU bool "Enable Armada-8K PCIe driver (DesignWare core)" - depends on DM_PCI depends on ARMADA_8K help Say Y here if you want to enable PCIe controller support on @@ -128,7 +116,6 @@ config PCIE_DW_SIFIVE config PCIE_FSL bool "FSL PowerPC PCIe support" - depends on DM_PCI help Say Y here if you want to enable PCIe controller support on FSL PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs. @@ -136,14 +123,12 @@ config PCIE_FSL config PCI_MPC85XX bool "MPC85XX PowerPC PCI support" - depends on DM_PCI help Say Y here if you want to enable PCI controller support on FSL PowerPC MPC85xx SoC. config PCI_RCAR_GEN2 bool "Renesas RCar Gen2 PCIe driver" - depends on DM_PCI depends on RCAR_32 help Say Y here if you want to enable PCIe controller support on @@ -152,7 +137,6 @@ config PCI_RCAR_GEN2 config PCI_RCAR_GEN3 bool "Renesas RCar Gen3 PCIe driver" - depends on DM_PCI depends on RCAR_GEN3 help Say Y here if you want to enable PCIe controller support on @@ -160,7 +144,7 @@ config PCI_RCAR_GEN3 config PCI_SANDBOX bool "Sandbox PCI support" - depends on SANDBOX && DM_PCI + depends on SANDBOX help Support PCI on sandbox, as an emulated bus. This permits testing of PCI feature such as bus scanning, device configuration and device @@ -195,7 +179,6 @@ config PCIE_OCTEON config PCI_XILINX bool "Xilinx AXI Bridge for PCI Express" - depends on DM_PCI help Enable support for the Xilinx AXI bridge for PCI express, an IP block which can be used on some generations of Xilinx FPGAs. @@ -205,7 +188,6 @@ config PCIE_LAYERSCAPE config PCIE_LAYERSCAPE_RC bool "Layerscape PCIe Root Complex mode support" - depends on DM_PCI select PCIE_LAYERSCAPE help Enable Layerscape PCIe Root Complex mode driver support. The Layerscape @@ -227,7 +209,6 @@ config PCI_IOMMU_EXTRA_MAPPINGS config PCIE_LAYERSCAPE_EP bool "Layerscape PCIe Endpoint mode support" - depends on DM_PCI select PCIE_LAYERSCAPE select PCI_ENDPOINT help @@ -238,7 +219,6 @@ config PCIE_LAYERSCAPE_EP config PCIE_LAYERSCAPE_GEN4 bool "Layerscape Gen4 PCIe support" - depends on DM_PCI help Support PCIe Gen4 on NXP Layerscape SoCs, which may have one or several PCIe controllers. The PCIe controller can work in RC or @@ -271,14 +251,12 @@ config FSL_PCIE_EP_COMPAT config PCIE_INTEL_FPGA bool "Intel FPGA PCIe support" - depends on DM_PCI help Say Y here if you want to enable PCIe controller support on Intel FPGA, example Stratix 10. config PCIE_IPROC bool "Iproc PCIe support" - depends on DM_PCI help Broadcom iProc PCIe controller driver. Say Y here if you want to enable Broadcom iProc PCIe controller, @@ -286,7 +264,6 @@ config PCIE_IPROC config PCI_MVEBU bool "Enable Armada XP/38x PCIe driver" depends on ARCH_MVEBU - select DM_PCI select MISC help Say Y here if you want to enable PCIe controller support on @@ -294,7 +271,6 @@ config PCI_MVEBU config PCIE_DW_COMMON bool - select DM_PCI config PCI_KEYSTONE bool "TI Keystone PCIe controller" @@ -304,7 +280,6 @@ config PCI_KEYSTONE config PCIE_MEDIATEK bool "MediaTek PCIe Gen2 controller" - depends on DM_PCI depends on ARCH_MEDIATEK help Say Y here if you want to enable Gen2 PCIe controller, @@ -321,7 +296,6 @@ config PCIE_DW_MESON config PCIE_ROCKCHIP bool "Enable Rockchip PCIe driver" depends on ARCH_ROCKCHIP - select DM_PCI select PHY_ROCKCHIP_PCIE default y if ROCKCHIP_RK3399 help @@ -339,7 +313,6 @@ config PCIE_DW_ROCKCHIP config PCI_BRCMSTB bool "Broadcom STB PCIe controller" - depends on DM_PCI depends on ARCH_BCM283X help Say Y here if you want to enable support for PCIe controller @@ -349,7 +322,6 @@ config PCI_BRCMSTB config PCIE_UNIPHIER bool "Socionext UniPhier PCIe driver" - depends on DM_PCI depends on ARCH_UNIPHIER select PHY_UNIPHIER_PCIE help diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index bdfdec98a0..4a131bf5ca 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -14,7 +14,6 @@ obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o -obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o obj-$(CONFIG_PCI_MPC85XX) += pci_mpc85xx.o obj-$(CONFIG_PCI_MSC01) += pci_msc01.o diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 815b26162f..cf6e30f936 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -234,19 +234,19 @@ static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno) * * Wait up to 1.5 seconds for PIO access to be accomplished. * - * Return 1 (true) if PIO access is accomplished. - * Return 0 (false) if PIO access is timed out. + * Return positive - retry count if PIO access is accomplished. + * Return negative - error if PIO access is timed out. */ static int pcie_advk_wait_pio(struct pcie_advk *pcie) { uint start, isr; uint count; - for (count = 0; count < PIO_MAX_RETRIES; count++) { + for (count = 1; count <= PIO_MAX_RETRIES; count++) { start = advk_readl(pcie, PIO_START); isr = advk_readl(pcie, PIO_ISR); if (!start && isr) - return 1; + return count; /* * Do not check the PIO state too frequently, * 100us delay is appropriate. @@ -255,7 +255,7 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie) } dev_err(pcie->dev, "PIO read/write transfer time out\n"); - return 0; + return -ETIMEDOUT; } /** @@ -265,11 +265,13 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie) * @allow_crs: Only for read requests, if CRS response is allowed * @read_val: Pointer to the read result * + * Return: 0 on success */ static int pcie_advk_check_pio_status(struct pcie_advk *pcie, bool allow_crs, uint *read_val) { + int ret; uint reg; unsigned int status; char *strcomp_status, *str_posted; @@ -282,6 +284,7 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie, case PIO_COMPLETION_STATUS_OK: if (reg & PIO_ERR_STATUS) { strcomp_status = "COMP_ERR"; + ret = -EFAULT; break; } /* Get the read result */ @@ -289,40 +292,46 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie, *read_val = advk_readl(pcie, PIO_RD_DATA); /* No error */ strcomp_status = NULL; + ret = 0; break; case PIO_COMPLETION_STATUS_UR: strcomp_status = "UR"; + ret = -EOPNOTSUPP; break; case PIO_COMPLETION_STATUS_CRS: if (allow_crs && read_val) { /* For reading, CRS is not an error status. */ *read_val = CFG_RD_CRS_VAL; strcomp_status = NULL; + ret = 0; } else { strcomp_status = "CRS"; + ret = -EAGAIN; } break; case PIO_COMPLETION_STATUS_CA: strcomp_status = "CA"; + ret = -ECANCELED; break; default: strcomp_status = "Unknown"; + ret = -EINVAL; break; } if (!strcomp_status) - return 0; + return ret; if (reg & PIO_NON_POSTED_REQ) str_posted = "Non-posted"; else str_posted = "Posted"; - dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n", + dev_dbg(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n", str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); - return -EFAULT; + return ret; } /** @@ -345,6 +354,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, enum pci_size_t size) { struct pcie_advk *pcie = dev_get_priv(bus); + int retry_count; bool allow_crs; uint reg; int ret; @@ -358,7 +368,18 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, return 0; } - allow_crs = (offset == PCI_VENDOR_ID) && (size == 4); + /* + * Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to + * OS is allowed only for 4-byte PCI_VENDOR_ID config read request and + * only when CRSSVE bit in Root Port PCIe device is enabled. In all + * other error PCIe Root Complex must return all-ones. + * Aardvark HW does not have Root Port PCIe device and U-Boot does not + * implement emulation of this device. + * U-Boot currently does not support handling of CRS return value for + * PCI_VENDOR_ID config read request and also does not set CRSSVE bit. + * Therefore disable returning CRS response for now. + */ + allow_crs = false; if (advk_readl(pcie, PIO_START)) { dev_err(pcie->dev, @@ -368,7 +389,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, return 0; } *valuep = pci_get_ff(size); - return -EINVAL; + return -EAGAIN; } /* Program the control register */ @@ -385,21 +406,29 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, advk_writel(pcie, reg, PIO_ADDR_LS); advk_writel(pcie, 0, PIO_ADDR_MS); + retry_count = 0; + +retry: /* Start the transfer */ advk_writel(pcie, 1, PIO_ISR); advk_writel(pcie, 1, PIO_START); - if (!pcie_advk_wait_pio(pcie)) { + ret = pcie_advk_wait_pio(pcie); + if (ret < 0) { if (allow_crs) { *valuep = CFG_RD_CRS_VAL; return 0; } *valuep = pci_get_ff(size); - return -EINVAL; + return ret; } + retry_count += ret; + /* Check PIO status and get the read result */ ret = pcie_advk_check_pio_status(pcie, allow_crs, ®); + if (ret == -EAGAIN && retry_count < PIO_MAX_RETRIES) + goto retry; if (ret) { *valuep = pci_get_ff(size); return ret; @@ -461,7 +490,9 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, enum pci_size_t size) { struct pcie_advk *pcie = dev_get_priv(bus); + int retry_count; uint reg; + int ret; dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ", PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); @@ -476,7 +507,7 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, if (advk_readl(pcie, PIO_START)) { dev_err(pcie->dev, "Previous PIO read/write transfer is still running\n"); - return -EINVAL; + return -EAGAIN; } /* Program the control register */ @@ -504,16 +535,24 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, advk_writel(pcie, reg, PIO_WR_DATA_STRB); dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg); + retry_count = 0; + +retry: /* Start the transfer */ advk_writel(pcie, 1, PIO_ISR); advk_writel(pcie, 1, PIO_START); - if (!pcie_advk_wait_pio(pcie)) { - return -EINVAL; - } + ret = pcie_advk_wait_pio(pcie); + if (ret < 0) + return ret; + + retry_count += ret; /* Check PIO status */ - return pcie_advk_check_pio_status(pcie, false, NULL); + ret = pcie_advk_check_pio_status(pcie, false, NULL); + if (ret == -EAGAIN && retry_count < PIO_MAX_RETRIES) + goto retry; + return ret; } /** diff --git a/drivers/pci/pci_indirect.c b/drivers/pci/pci_indirect.c deleted file mode 100644 index 6134c22d1b..0000000000 --- a/drivers/pci/pci_indirect.c +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Support for indirect PCI bridges. - * - * Copyright (C) 1998 Gabriel Paubert. - */ - -#include <common.h> - -#if !defined(__I386__) && !defined(CONFIG_DM_PCI) - -#include <asm/processor.h> -#include <asm/io.h> -#include <pci.h> - -#define cfg_read(val, addr, type, op) *val = op((type)(addr)) -#define cfg_write(val, addr, type, op) op((type *)(addr), (val)) - -#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) -#define INDIRECT_PCI_OP(rw, size, type, op, mask) \ -static int \ -indirect_##rw##_config_##size(struct pci_controller *hose, \ - pci_dev_t dev, int offset, type val) \ -{ \ - u32 b, d,f; \ - b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ - b = b - hose->first_busno; \ - dev = PCI_BDF(b, d, f); \ - *(hose->cfg_addr) = dev | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; \ - sync(); \ - cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ - return 0; \ -} -#else -#define INDIRECT_PCI_OP(rw, size, type, op, mask) \ -static int \ -indirect_##rw##_config_##size(struct pci_controller *hose, \ - pci_dev_t dev, int offset, type val) \ -{ \ - u32 b, d,f; \ - b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ - b = b - hose->first_busno; \ - dev = PCI_BDF(b, d, f); \ - out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ - cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ - return 0; \ -} -#endif - -INDIRECT_PCI_OP(read, byte, u8 *, in_8, 3) -INDIRECT_PCI_OP(read, word, u16 *, in_le16, 2) -INDIRECT_PCI_OP(read, dword, u32 *, in_le32, 0) -INDIRECT_PCI_OP(write, byte, u8, out_8, 3) -INDIRECT_PCI_OP(write, word, u16, out_le16, 2) -INDIRECT_PCI_OP(write, dword, u32, out_le32, 0) - -void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) -{ - pci_set_ops(hose, - indirect_read_config_byte, - indirect_read_config_word, - indirect_read_config_dword, - indirect_write_config_byte, - indirect_write_config_word, - indirect_write_config_dword); - - hose->cfg_addr = (unsigned int *) cfg_addr; - hose->cfg_data = (unsigned char *) cfg_data; -} - -#endif /* !__I386__ */ diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 77fb851114..30eaa376c8 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -69,7 +69,7 @@ config PINCONF_RECURSIVE direct children of the pin controller device (may be grandchildren for example). It is define is each individual pin controller device. Say Y here if you want to keep this behavior with the pinconfig - u-class: all sub are recursivelly bounded. + u-class: all sub are recursively bounded. If the option is disabled, this behavior is deactivated and only the direct children of pin controller will be assumed as pin configuration; you can save memory footprint when this feature is diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index e12699bec7..d07e9a28af 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -271,7 +271,7 @@ config NXP_FSPI config OCTEON_SPI bool "Octeon SPI driver" - depends on DM_PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) + depends on ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2 help Enable the Octeon SPI driver. This driver can be used to access the SPI NOR flash on Octeon II/III and OcteonTX/TX2 diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index fc81b07343..2db4ae20f1 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -77,6 +77,7 @@ #define GQSPI_GFIFO_SELECT BIT(0) #define GQSPI_FIFO_THRESHOLD 1 +#define GQSPI_GENFIFO_THRESHOLD 31 #define SPI_XFER_ON_BOTH 0 #define SPI_XFER_ON_LOWER 1 @@ -197,14 +198,15 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv) writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->idisr); writel(GQSPI_FIFO_THRESHOLD, ®s->txftr); writel(GQSPI_FIFO_THRESHOLD, ®s->rxftr); + writel(GQSPI_GENFIFO_THRESHOLD, ®s->gqfthr); writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->isr); + writel(~GQSPI_ENABLE_ENABLE_MASK, ®s->enbr); config_reg = readl(®s->confr); config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK | GQSPI_CONFIG_MODE_EN_MASK); - config_reg |= GQSPI_CONFIG_DMA_MODE | - GQSPI_GFIFO_WP_HOLD | - GQSPI_DFLT_BAUD_RATE_DIV; + config_reg |= GQSPI_CONFIG_DMA_MODE | GQSPI_GFIFO_WP_HOLD | + GQSPI_DFLT_BAUD_RATE_DIV | GQSPI_GFIFO_STRT_MODE_MASK; writel(config_reg, ®s->confr); writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr); @@ -242,6 +244,8 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv, u32 config_reg, ier; int ret = 0; + writel(gqspi_fifo_reg, ®s->genfifo); + config_reg = readl(®s->confr); /* Manual start if needed */ config_reg |= GQSPI_STRT_GEN_FIFO; @@ -249,16 +253,15 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv, /* Enable interrupts */ ier = readl(®s->ier); - ier |= GQSPI_IXR_GFNFULL_MASK; + ier |= GQSPI_IXR_GFEMTY_MASK; writel(ier, ®s->ier); - /* Wait until the fifo is not full to write the new command */ - ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFNFULL_MASK, 1, + /* Wait until the gen fifo is empty to write the new command */ + ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1, GQSPI_TIMEOUT, 1); if (ret) printf("%s Timeout\n", __func__); - writel(gqspi_fifo_reg, ®s->genfifo); } static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on) @@ -572,25 +575,20 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, u32 gen_fifo_cmd, u32 *buf) { u32 addr; - u32 size, len; + u32 size; u32 actuallen = priv->len; int ret = 0; struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs; writel((unsigned long)buf, &dma_regs->dmadst); - writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize); + writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize); writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier); addr = (unsigned long)buf; - size = roundup(priv->len, ARCH_DMA_MINALIGN); + size = roundup(priv->len, GQSPI_DMA_ALIGN); flush_dcache_range(addr, addr + size); while (priv->len) { - len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); - if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) && - (len % ARCH_DMA_MINALIGN)) { - gen_fifo_cmd &= ~GENMASK(7, 0); - gen_fifo_cmd |= roundup(len, ARCH_DMA_MINALIGN); - } + zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd); diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig index 1835607083..863c3fbe02 100644 --- a/drivers/virtio/Kconfig +++ b/drivers/virtio/Kconfig @@ -31,7 +31,7 @@ config VIRTIO_MMIO config VIRTIO_PCI bool "PCI driver for virtio devices" - depends on DM_PCI + depends on PCI select VIRTIO help This driver provides support for virtio based paravirtual device diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index 349411c3cc..12f9579fcf 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -804,6 +804,30 @@ static int setup_root_or_create_block(struct btrfs_fs_info *fs_info, return 0; } +static int get_default_subvolume(struct btrfs_fs_info *fs_info, + struct btrfs_key *key_ret) +{ + struct btrfs_root *root = fs_info->tree_root; + struct btrfs_dir_item *dir_item; + struct btrfs_path path; + int ret = 0; + + btrfs_init_path(&path); + + dir_item = btrfs_lookup_dir_item(NULL, root, &path, + BTRFS_ROOT_TREE_DIR_OBJECTID, + "default", 7, 0); + if (IS_ERR(dir_item)) { + ret = PTR_ERR(dir_item); + goto out; + } + + btrfs_dir_item_key_to_cpu(path.nodes[0], dir_item, key_ret); +out: + btrfs_release_path(&path); + return ret; +} + int btrfs_setup_all_roots(struct btrfs_fs_info *fs_info) { struct btrfs_super_block *sb = fs_info->super_copy; @@ -833,9 +857,17 @@ int btrfs_setup_all_roots(struct btrfs_fs_info *fs_info) fs_info->last_trans_committed = generation; - key.objectid = BTRFS_FS_TREE_OBJECTID; - key.type = BTRFS_ROOT_ITEM_KEY; - key.offset = (u64)-1; + ret = get_default_subvolume(fs_info, &key); + if (ret) { + /* + * The default dir item isn't there. Linux kernel behaviour is + * to silently use the top-level subvolume in this case. + */ + key.objectid = BTRFS_FS_TREE_OBJECTID; + key.type = BTRFS_ROOT_ITEM_KEY; + key.offset = (u64)-1; + } + fs_info->fs_root = btrfs_read_fs_root(fs_info, &key); if (IS_ERR(fs_info->fs_root)) diff --git a/include/ahci.h b/include/ahci.h index fb96dd8861..d5453042d1 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -148,16 +148,12 @@ struct ahci_ioports { * where dev is the controller (although at present it sometimes stands alone). */ struct ahci_uc_priv { -#if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI) /* * TODO(sjg@chromium.org): Drop this once this structure is only used * in a driver-model context (i.e. attached to a device with * dev_get_uclass_priv() */ struct udevice *dev; -#else - pci_dev_t dev; -#endif struct ahci_ioports port[AHCI_MAX_PORTS]; u16 *ataid[AHCI_MAX_PORTS]; u32 n_ports; diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 2f1fc6a6a2..dd11e9841e 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -251,10 +251,6 @@ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index d6a151d20c..2a53b14d0b 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -308,10 +308,6 @@ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 0e2e034dcd..26c6180d3a 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -238,8 +238,6 @@ #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 #ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 66cf2053f9..fc9d94984e 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -26,7 +26,6 @@ #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ #endif -#define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ /* diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 2243143664..e1e0717991 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -27,7 +27,6 @@ * assume U-Boot is less than 0.5MB */ -#define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h deleted file mode 100644 index 22b8c3f4e0..0000000000 --- a/include/configs/UCP1020.h +++ /dev/null @@ -1,809 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2019 Arcturus Networks, Inc. - * https://www.arcturusnetworks.com/products/ucp1020/ - * based on include/configs/p1_p2_rdb_pc.h - * original copyright follows: - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * QorIQ uCP1020-xx boards configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -/*** Arcturus FirmWare Environment */ - -#define MAX_SERIAL_SIZE 15 -#define MAX_HWADDR_SIZE 17 - -#define MAX_FWENV_ADDR 4 - -#define FWENV_MMC 1 -#define FWENV_SPI_FLASH 2 -#define FWENV_NOR_FLASH 3 -/* - #define FWENV_TYPE FWENV_MMC - #define FWENV_TYPE FWENV_SPI_FLASH -*/ -#define FWENV_TYPE FWENV_NOR_FLASH - -#if (FWENV_TYPE == FWENV_MMC) -#define FWENV_ADDR1 -1 -#define FWENV_ADDR2 -1 -#define FWENV_ADDR3 -1 -#define FWENV_ADDR4 -1 -#define EMPY_CHAR 0 -#endif - -#if (FWENV_TYPE == FWENV_SPI_FLASH) -#ifndef CONFIG_SF_DEFAULT_SPEED -#define CONFIG_SF_DEFAULT_SPEED 1000000 -#endif -#ifndef CONFIG_SF_DEFAULT_MODE -#define CONFIG_SF_DEFAULT_MODE SPI_MODE0 -#endif -#ifndef CONFIG_SF_DEFAULT_CS -#define CONFIG_SF_DEFAULT_CS 0 -#endif -#ifndef CONFIG_SF_DEFAULT_BUS -#define CONFIG_SF_DEFAULT_BUS 0 -#endif -#define FWENV_ADDR1 (0x200 - sizeof(smac)) -#define FWENV_ADDR2 (0x400 - sizeof(smac)) -#define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac)) -#define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac)) -#define EMPY_CHAR 0xff -#endif - -#if (FWENV_TYPE == FWENV_NOR_FLASH) -#define FWENV_ADDR1 0xEC080000 -#define FWENV_ADDR2 -1 -#define FWENV_ADDR3 -1 -#define FWENV_ADDR4 -1 -#define EMPY_CHAR 0xff -#endif -/***********************************/ - -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#if defined(CONFIG_TARTGET_UCP1020T1) - -#define CONFIG_UCP1020_REV_1_3 - -#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" - -#define CONFIG_TSEC1 -#define CONFIG_TSEC3 -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF -#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE -#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD -#define CONFIG_IPADDR 10.80.41.229 -#define CONFIG_SERVERIP 10.80.41.227 -#define CONFIG_NETMASK 255.255.252.0 -#define CONFIG_ETHPRIME "eTSEC3" - -#define CONFIG_SYS_L2_SIZE (256 << 10) - -#endif - -#if defined(CONFIG_TARGET_UCP1020) - -#define CONFIG_UCP1020 -#define CONFIG_UCP1020_REV_1_3 - -#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" - -#define CONFIG_TSEC1 -#define CONFIG_TSEC3 -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF -#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE -#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD -#define CONFIG_IPADDR 192.168.1.81 -#define CONFIG_IPADDR1 192.168.1.82 -#define CONFIG_IPADDR2 192.168.1.83 -#define CONFIG_SERVERIP 192.168.1.80 -#define CONFIG_GATEWAYIP 102.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_ETHPRIME "eTSEC1" - -#define CONFIG_SYS_L2_SIZE (256 << 10) - -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc -#endif - -#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_LBA48 - -#define CONFIG_SYS_CLK_FREQ 66666666 - -#define CONFIG_HWCONFIG - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE -#define CONFIG_BTB - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k - SPL code*/ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* DDR Setup */ -#define CONFIG_SYS_SPD_BUS_NUM 1 - -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 - -/* Default settings for DDR3 */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 - -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ -#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 - -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 -#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF -#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 -#define CONFIG_SYS_DDR_MODE_1 0x40461520 -#define CONFIG_SYS_DDR_MODE_2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x0C300000 - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable - * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) - * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 - * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable - * (early boot only) - * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ -#define CONFIG_SYS_FLASH_BASE 0xec000000 - -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ - | BR_PS_16 | BR_V) - -#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -/* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -/* Size of used area in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ - -#define CONFIG_SYS_PMC_BASE 0xff980000 -#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE -#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ - BR_PS_8 | BR_V) -#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ - OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ - OR_GPCM_EAD) - -#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#ifdef CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#endif - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } -#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ - -#define CONFIG_RTC_DS1337 -#define CONFIG_RTC_DS1337_NOOSC -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 -#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C -#define CONFIG_SYS_I2C_IDT6V49205B 0x69 - -#if defined(CONFIG_PCI) -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ - -/* controller 1, Slot 2, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* - * Environment - */ -#if !defined(CONFIG_ENV_FIT_UCBOOT) && defined(CONFIG_RAMBOOT_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 - -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#endif -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -/* Misc Extra Settings */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) - -#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3) -#else -#error "UCP1020 module revision is not defined !!!" -#endif - -#define CONFIG_BOOTP_SERVERIP - -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 4 -#define TSEC2_PHY_ADDR 0 -#define TSEC2_PHY_ADDR_SGMII 0x00 -#define TSEC3_PHY_ADDR 6 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#endif - -#define CONFIG_HOSTNAME "UCP1020" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -#if defined(CONFIG_DONGLE) - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"bootcmd=run prog_spi_mbrbootcramfs\0" \ -"bootfile=uImage\0" \ -"consoledev=ttyS0\0" \ -"cramfsfile=image.cramfs\0" \ -"dtbaddr=0x00c00000\0" \ -"dtbfile=image.dtb\0" \ -"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ -"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ -"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ -"fileaddr=0x01000000\0" \ -"filesize=0x00080000\0" \ -"flashmbr=sf probe 0; " \ - "tftp $loadaddr $mbr; " \ - "sf erase $mbr_offset +$filesize; " \ - "sf write $loadaddr $mbr_offset $filesize\0" \ -"flashrecovery=tftp $recoveryaddr $cramfsfile; " \ - "protect off $nor_recoveryaddr +$filesize; " \ - "erase $nor_recoveryaddr +$filesize; " \ - "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ - "protect on $nor_recoveryaddr +$filesize\0 " \ -"flashuboot=tftp $ubootaddr $ubootfile; " \ - "protect off $nor_ubootaddr +$filesize; " \ - "erase $nor_ubootaddr +$filesize; " \ - "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ - "protect on $nor_ubootaddr +$filesize\0 " \ -"flashworking=tftp $workingaddr $cramfsfile; " \ - "protect off $nor_workingaddr +$filesize; " \ - "erase $nor_workingaddr +$filesize; " \ - "cp.b $workingaddr $nor_workingaddr $filesize; " \ - "protect on $nor_workingaddr +$filesize\0 " \ -"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ -"kerneladdr=0x01100000\0" \ -"kernelfile=uImage\0" \ -"loadaddr=0x01000000\0" \ -"mbr=uCP1020d.mbr\0" \ -"mbr_offset=0x00000000\0" \ -"mmbr=uCP1020Quiet.mbr\0" \ -"mmcpart=0:2\0" \ -"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ - "mmc erase 1 1; " \ - "mmc write $loadaddr 1 1\0" \ -"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ - "mmc erase 0x40 0x400; " \ - "mmc write $loadaddr 0x40 0x400\0" \ -"netdev=eth0\0" \ -"nor_recoveryaddr=0xEC0A0000\0" \ -"nor_ubootaddr=0xEFF80000\0" \ -"nor_workingaddr=0xECFA0000\0" \ -"norbootrecovery=setenv bootargs $recoverybootargs" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "run norloadrecovery; " \ - "bootm $kerneladdr - $dtbaddr\0" \ -"norbootworking=setenv bootargs $workingbootargs" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "run norloadworking; " \ - "bootm $kerneladdr - $dtbaddr\0" \ -"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ - "setenv cramfsaddr $nor_recoveryaddr; " \ - "cramfsload $dtbaddr $dtbfile; " \ - "cramfsload $kerneladdr $kernelfile\0" \ -"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ - "setenv cramfsaddr $nor_workingaddr; " \ - "cramfsload $dtbaddr $dtbfile; " \ - "cramfsload $kerneladdr $kernelfile\0" \ -"prog_spi_mbr=run spi__mbr\0" \ -"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ -"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ - "run spi__cramfs\0" \ -"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "tftp $rootfsaddr $rootfsfile; " \ - "tftp $loadaddr $kernelfile; " \ - "tftp $dtbaddr $dtbfile; " \ - "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ -"ramdisk_size=120000\0" \ -"ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"recoveryaddr=0x02F00000\0" \ -"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ -"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ - "mw.l 0xffe0f008 0x00400000\0" \ -"rootfsaddr=0x02F00000\0" \ -"rootfsfile=rootfs.ext2.gz.uboot\0" \ -"rootpath=/opt/nfsroot\0" \ -"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ - "protect off 0xeC000000 +$filesize; " \ - "erase 0xEC000000 +$filesize; " \ - "cp.b $loadaddr 0xEC000000 $filesize; " \ - "cmp.b $loadaddr 0xEC000000 $filesize; " \ - "protect on 0xeC000000 +$filesize\0" \ -"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ - "protect off 0xeFF80000 +$filesize; " \ - "erase 0xEFF80000 +$filesize; " \ - "cp.b $loadaddr 0xEFF80000 $filesize; " \ - "cmp.b $loadaddr 0xEFF80000 $filesize; " \ - "protect on 0xeFF80000 +$filesize\0" \ -"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ - "sf probe 0; sf erase 0x8000 +$filesize; " \ - "sf write $loadaddr 0x8000 $filesize\0" \ -"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ - "protect off 0xec0a0000 +$filesize; " \ - "erase 0xeC0A0000 +$filesize; " \ - "cp.b $loadaddr 0xeC0A0000 $filesize; " \ - "protect on 0xec0a0000 +$filesize\0" \ -"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ - "sf probe 1; sf erase 0 +$filesize; " \ - "sf write $loadaddr 0 $filesize\0" \ -"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ - "sf probe 0; sf erase 0 +$filesize; " \ - "sf write $loadaddr 0 $filesize\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ -"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ -"ubootaddr=0x01000000\0" \ -"ubootfile=u-boot.bin\0" \ -"ubootd=u-boot4dongle.bin\0" \ -"upgrade=run flashworking\0" \ -"usb_phy_type=ulpi\0 " \ -"workingaddr=0x02F00000\0" \ -"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" - -#else - -#if defined(CONFIG_UCP1020T1) - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ -"bootfile=uImage\0" \ -"consoledev=ttyS0\0" \ -"cramfsfile=image.cramfs\0" \ -"dtbaddr=0x00c00000\0" \ -"dtbfile=image.dtb\0" \ -"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ -"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ -"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ -"fileaddr=0x01000000\0" \ -"filesize=0x00080000\0" \ -"flashmbr=sf probe 0; " \ - "tftp $loadaddr $mbr; " \ - "sf erase $mbr_offset +$filesize; " \ - "sf write $loadaddr $mbr_offset $filesize\0" \ -"flashrecovery=tftp $recoveryaddr $cramfsfile; " \ - "protect off $nor_recoveryaddr +$filesize; " \ - "erase $nor_recoveryaddr +$filesize; " \ - "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ - "protect on $nor_recoveryaddr +$filesize\0 " \ -"flashuboot=tftp $ubootaddr $ubootfile; " \ - "protect off $nor_ubootaddr +$filesize; " \ - "erase $nor_ubootaddr +$filesize; " \ - "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ - "protect on $nor_ubootaddr +$filesize\0 " \ -"flashworking=tftp $workingaddr $cramfsfile; " \ - "protect off $nor_workingaddr +$filesize; " \ - "erase $nor_workingaddr +$filesize; " \ - "cp.b $workingaddr $nor_workingaddr $filesize; " \ - "protect on $nor_workingaddr +$filesize\0 " \ -"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ -"kerneladdr=0x01100000\0" \ -"kernelfile=uImage\0" \ -"loadaddr=0x01000000\0" \ -"mbr=uCP1020.mbr\0" \ -"mbr_offset=0x00000000\0" \ -"netdev=eth0\0" \ -"nor_recoveryaddr=0xEC0A0000\0" \ -"nor_ubootaddr=0xEFF80000\0" \ -"nor_workingaddr=0xECFA0000\0" \ -"norbootrecovery=setenv bootargs $recoverybootargs" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "run norloadrecovery; " \ - "bootm $kerneladdr - $dtbaddr\0" \ -"norbootworking=setenv bootargs $workingbootargs" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "run norloadworking; " \ - "bootm $kerneladdr - $dtbaddr\0" \ -"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ - "setenv cramfsaddr $nor_recoveryaddr; " \ - "cramfsload $dtbaddr $dtbfile; " \ - "cramfsload $kerneladdr $kernelfile\0" \ -"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ - "setenv cramfsaddr $nor_workingaddr; " \ - "cramfsload $dtbaddr $dtbfile; " \ - "cramfsload $kerneladdr $kernelfile\0" \ -"othbootargs=quiet\0" \ -"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "tftp $rootfsaddr $rootfsfile; " \ - "tftp $loadaddr $kernelfile; " \ - "tftp $dtbaddr $dtbfile; " \ - "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ -"ramdisk_size=120000\0" \ -"ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"recoveryaddr=0x02F00000\0" \ -"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ -"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ - "mw.l 0xffe0f008 0x00400000\0" \ -"rootfsaddr=0x02F00000\0" \ -"rootfsfile=rootfs.ext2.gz.uboot\0" \ -"rootpath=/opt/nfsroot\0" \ -"silent=1\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ -"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ -"ubootaddr=0x01000000\0" \ -"ubootfile=u-boot.bin\0" \ -"upgrade=run flashworking\0" \ -"workingaddr=0x02F00000\0" \ -"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" - -#else /* For Arcturus Modules */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"bootcmd=run norkernel\0" \ -"bootfile=uImage\0" \ -"consoledev=ttyS0\0" \ -"dtbaddr=0x00c00000\0" \ -"dtbfile=image.dtb\0" \ -"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ -"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ -"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ -"fileaddr=0x01000000\0" \ -"filesize=0x00080000\0" \ -"flashmbr=sf probe 0; " \ - "tftp $loadaddr $mbr; " \ - "sf erase $mbr_offset +$filesize; " \ - "sf write $loadaddr $mbr_offset $filesize\0" \ -"flashuboot=tftp $loadaddr $ubootfile; " \ - "protect off $nor_ubootaddr0 +$filesize; " \ - "erase $nor_ubootaddr0 +$filesize; " \ - "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ - "protect on $nor_ubootaddr0 +$filesize; " \ - "protect off $nor_ubootaddr1 +$filesize; " \ - "erase $nor_ubootaddr1 +$filesize; " \ - "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ - "protect on $nor_ubootaddr1 +$filesize\0 " \ -"format0=protect off $part0base +$part0size; " \ - "erase $part0base +$part0size\0" \ -"format1=protect off $part1base +$part1size; " \ - "erase $part1base +$part1size\0" \ -"format2=protect off $part2base +$part2size; " \ - "erase $part2base +$part2size\0" \ -"format3=protect off $part3base +$part3size; " \ - "erase $part3base +$part3size\0" \ -"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ -"kerneladdr=0x01100000\0" \ -"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ -"kernelfile=uImage\0" \ -"loadaddr=0x01000000\0" \ -"mbr=uCP1020.mbr\0" \ -"mbr_offset=0x00000000\0" \ -"netdev=eth0\0" \ -"nor_ubootaddr0=0xEC000000\0" \ -"nor_ubootaddr1=0xEFF80000\0" \ -"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ - "run norkernelload; " \ - "bootm $kerneladdr - $dtbaddr\0" \ -"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ - "setenv cramfsaddr $part0base; " \ - "cramfsload $dtbaddr $dtbfile; " \ - "cramfsload $kerneladdr $kernelfile\0" \ -"part0base=0xEC100000\0" \ -"part0size=0x00700000\0" \ -"part1base=0xEC800000\0" \ -"part1size=0x02000000\0" \ -"part2base=0xEE800000\0" \ -"part2size=0x00800000\0" \ -"part3base=0xEF000000\0" \ -"part3size=0x00F80000\0" \ -"partENVbase=0xEC080000\0" \ -"partENVsize=0x00080000\0" \ -"program0=tftp part0-000000.bin; " \ - "protect off $part0base +$filesize; " \ - "erase $part0base +$filesize; " \ - "cp.b $loadaddr $part0base $filesize; " \ - "echo Verifying...; " \ - "cmp.b $loadaddr $part0base $filesize\0" \ -"program1=tftp part1-000000.bin; " \ - "protect off $part1base +$filesize; " \ - "erase $part1base +$filesize; " \ - "cp.b $loadaddr $part1base $filesize; " \ - "echo Verifying...; " \ - "cmp.b $loadaddr $part1base $filesize\0" \ -"program2=tftp part2-000000.bin; " \ - "protect off $part2base +$filesize; " \ - "erase $part2base +$filesize; " \ - "cp.b $loadaddr $part2base $filesize; " \ - "echo Verifying...; " \ - "cmp.b $loadaddr $part2base $filesize\0" \ -"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "tftp $rootfsaddr $rootfsfile; " \ - "tftp $loadaddr $kernelfile; " \ - "tftp $dtbaddr $dtbfile; " \ - "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ -"ramdisk_size=120000\0" \ -"ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ - "mw.l 0xffe0f008 0x00400000\0" \ -"rootfsaddr=0x02F00000\0" \ -"rootfsfile=rootfs.ext2.gz.uboot\0" \ -"rootpath=/opt/nfsroot\0" \ -"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ - "sf probe 0; sf erase 0 +$filesize; " \ - "sf write $loadaddr 0 $filesize\0" \ -"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ - "protect off 0xeC000000 +$filesize; " \ - "erase 0xEC000000 +$filesize; " \ - "cp.b $loadaddr 0xEC000000 $filesize; " \ - "cmp.b $loadaddr 0xEC000000 $filesize; " \ - "protect on 0xeC000000 +$filesize\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ -"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ -"ubootfile=u-boot.bin\0" \ -"upgrade=run flashuboot\0" \ -"usb_phy_type=ulpi\0 " \ -"boot_nfs= " \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr\0" \ -"boot_hd = " \ - "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "usb start;" \ - "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ - "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ - "bootm $loadaddr - $fdtaddr\0" \ -"boot_usb_fat = " \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs " \ - "ramdisk_size=$ramdisk_size;" \ - "usb start;" \ - "fatload usb 0:2 $loadaddr $bootfile;" \ - "fatload usb 0:2 $fdtaddr $fdtfile;" \ - "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ -"boot_usb_ext2 = " \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs " \ - "ramdisk_size=$ramdisk_size;" \ - "usb start;" \ - "ext2load usb 0:4 $loadaddr $bootfile;" \ - "ext2load usb 0:4 $fdtaddr $fdtfile;" \ - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ -"boot_nor = " \ - "setenv bootargs root=/dev/$jffs2nor rw " \ - "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ - "bootm $norbootaddr - $norfdtaddr\0 " \ -"boot_ram = " \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs " \ - "ramdisk_size=$ramdisk_size;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" - -#endif -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 16d095584e..99624081c3 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -92,6 +92,34 @@ "${bootdir}/${name_fit}\0" \ "partitions=" PARTS_DEFAULT +#define EXTRA_ENV_AM642_BOARD_SETTING_USBMSC \ + "args_usb=run finduuid;setenv bootargs console=${console} " \ + "${optargs} " \ + "root=PARTUUID=${uuid} rw " \ + "rootfstype=${mmcrootfstype}\0" \ + "init_usb=run args_all args_usb\0" \ + "get_fdt_usb=load usb ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "get_overlay_usb=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $name_overlays;" \ + "do;" \ + "load usb ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \ + "fdt apply ${dtboaddr};" \ + "done;\0" \ + "get_kern_usb=load usb ${bootpart} ${loadaddr} " \ + "${bootdir}/${name_kern}\0" \ + "get_fit_usb=load usb ${bootpart} ${addr_fit} " \ + "${bootdir}/${name_fit}\0" \ + "usbboot=setenv boot usb;" \ + "setenv bootpart 0:2;" \ + "usb start;" \ + "run findfdt;" \ + "run init_usb;" \ + "run get_kern_usb;" \ + "run get_fdt_usb;" \ + "run run_kern\0" + #define EXTRA_ENV_DFUARGS \ DFU_ALT_INFO_MMC \ DFU_ALT_INFO_EMMC \ @@ -104,7 +132,8 @@ DEFAULT_MMC_TI_ARGS \ EXTRA_ENV_AM642_BOARD_SETTINGS \ EXTRA_ENV_AM642_BOARD_SETTINGS_MMC \ - EXTRA_ENV_DFUARGS + EXTRA_ENV_DFUARGS \ + EXTRA_ENV_AM642_BOARD_SETTING_USBMSC /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index 18b80ef8ce..10555d1a6c 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -155,9 +155,7 @@ #define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY #endif -/* set default dfu_bufsiz to 128KB (sector size of OSPI) */ #define EXTRA_ENV_DFUARGS \ - "dfu_bufsiz=0x20000\0" \ DFU_ALT_INFO_MMC \ DFU_ALT_INFO_EMMC \ DFU_ALT_INFO_RAM \ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 65d7dd1430..e460f69a08 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -39,6 +39,15 @@ #define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif +#if defined(CONFIG_ARMADA_38X) && !defined(CONFIG_SYS_BAUDRATE_TABLE) +#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ + 9600, 19200, 38400, 57600, 115200, \ + 230400, 460800, 500000, 576000, \ + 921600, 1000000, 1152000, 1500000, \ + 2000000, 2500000, 3125000, 4000000, \ + 5200000 } +#endif + /* auto boot */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 52a22a9758..b12e3a4028 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -45,9 +45,6 @@ #endif /* CONFIG_SPL_OS_BOOT */ #endif /* CONFIG_MTD_RAW_NAND */ -#define MEM_LAYOUT_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV - #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ "bootcmd_" #devtypel #instance "=" \ "setenv mmcdev " #instance "; " \ @@ -83,8 +80,12 @@ #include <config_distro_bootcmd.h> +#include <environment/ti/mmc.h> + #define CONFIG_EXTRA_ENV_SETTINGS \ - MEM_LAYOUT_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + DEFAULT_FIT_TI_ARGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ @@ -97,42 +98,6 @@ "bootubivol=rootfs\0" \ "bootubipart=rootfs\0" \ "optargs=\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${mtdparts} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "ext4bootenv=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ - "env import -t ${loadaddr} ${filesize}\0" \ - "mmcbootenv=setenv bootpart ${mmcdev}:${mmcpart}; " \ - "mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "run loadbootenv && run importbootenv; " \ - "run ext4bootenv && run importbootenv; " \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...; " \ - "run uenvcmd; " \ - "fi; " \ - "fi\0" \ - "loadimage=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loaddtb=ext4load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "mmcboot=run mmcbootenv; " \ - "if run loadimage && run loaddtb; then " \ - "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} ...; " \ - "run mmcargs; " \ - "if test ${bootfile} = uImage; then " \ - "bootm ${loadaddr} - ${fdtaddr}; " \ - "fi; " \ - "if test ${bootfile} = zImage; then " \ - "bootz ${loadaddr} - ${fdtaddr}; " \ - "fi; " \ - "fi\0" \ "nandroot=ubi0:rootfs ubi.mtd=rootfs rw noinitrd\0" \ "nandrootfstype=ubifs rootwait\0" \ "nandargs=setenv bootargs console=${console} " \ diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index 538cce414c..f68d7d7676 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -34,6 +34,8 @@ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */ +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 + /* Environment options */ #ifndef CONFIG_SPL_BUILD @@ -41,6 +43,7 @@ func(NVME, nvme, 0) \ func(USB, usb, 0) \ func(MMC, mmc, 0) \ + func(SCSI, scsi, 0) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 251a6c9d8e..e10d90cdc7 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -253,7 +253,7 @@ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) # define CONFIG_SPL_ENV_SUPPORT -# define CONFIG_SPL_HASH_SUPPORT +# define CONFIG_SPL_HASH # define CONFIG_ENV_MAX_ENTRIES 10 #endif diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h index b6b958da51..5a1a36212e 100644 --- a/include/efi_tcg2.h +++ b/include/efi_tcg2.h @@ -28,6 +28,8 @@ #define EFI_TCG2_EXTEND_ONLY 0x0000000000000001 #define PE_COFF_IMAGE 0x0000000000000010 +#define EFI_TCG2_MAX_PCR_INDEX 23 + /* Algorithm Registry */ #define EFI_TCG2_BOOT_HASH_ALG_SHA1 0x00000001 #define EFI_TCG2_BOOT_HASH_ALG_SHA256 0x00000002 @@ -127,8 +129,8 @@ struct efi_tcg2_boot_service_capability { efi_tcg_event_algorithm_bitmap active_pcr_banks; }; -#define boot_service_capability_min \ - sizeof(struct efi_tcg2_boot_service_capability) - \ +/* up to and including the vendor ID (manufacturer_id) field */ +#define BOOT_SERVICE_CAPABILITY_MIN \ offsetof(struct efi_tcg2_boot_service_capability, number_of_pcr_banks) #define TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03 "Spec ID Event03" diff --git a/include/efi_variable.h b/include/efi_variable.h index 4623a64142..0440d356bc 100644 --- a/include/efi_variable.h +++ b/include/efi_variable.h @@ -12,6 +12,7 @@ enum efi_auth_var_type { EFI_AUTH_VAR_NONE = 0, + EFI_AUTH_MODE, EFI_AUTH_VAR_PK, EFI_AUTH_VAR_KEK, EFI_AUTH_VAR_DB, @@ -161,10 +162,13 @@ efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t * /** * efi_var_restore() - restore EFI variables from buffer * + * Only if @safe is set secure boot related variables will be restored. + * * @buf: buffer + * @safe: restoring from tamper-resistant storage * Return: status code */ -efi_status_t efi_var_restore(struct efi_var_file *buf); +efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe); /** * efi_var_from_file() - read variables from file diff --git a/include/environment/ti/k3_dfu.h b/include/environment/ti/k3_dfu.h index 2f503b8de8..a16a3adeca 100644 --- a/include/environment/ti/k3_dfu.h +++ b/include/environment/ti/k3_dfu.h @@ -40,7 +40,7 @@ #define DFU_ALT_INFO_RAM \ "dfu_alt_info_ram=" \ - "tispl.bin ram 0x80080000 0x100000;" \ - "u-boot.img ram 0x81000000 0x100000\0" \ + "tispl.bin ram 0x80080000 0x200000;" \ + "u-boot.img ram 0x81000000 0x400000\0" \ #endif /* __TI_DFU_H */ diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h index b86c8dc7a4..769ea9d5ef 100644 --- a/include/environment/ti/mmc.h +++ b/include/environment/ti/mmc.h @@ -11,7 +11,7 @@ #define DEFAULT_MMC_TI_ARGS \ "mmcdev=0\0" \ "mmcrootfstype=ext4 rootwait\0" \ - "finduuid=part uuid mmc ${bootpart} uuid\0" \ + "finduuid=part uuid ${boot} ${bootpart} uuid\0" \ "args_mmc=run finduuid;setenv bootargs console=${console} " \ "${optargs} " \ "root=PARTUUID=${uuid} rw " \ diff --git a/include/image.h b/include/image.h index e20f0b69d5..73a763a693 100644 --- a/include/image.h +++ b/include/image.h @@ -31,9 +31,7 @@ struct fdt_region; #define IMAGE_ENABLE_OF_LIBFDT 1 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ #define CONFIG_FIT_RSASSA_PSS 1 -#define CONFIG_FIT_SHA256 -#define CONFIG_FIT_SHA384 -#define CONFIG_FIT_SHA512 +#define CONFIG_MD5 #define CONFIG_SHA1 #define CONFIG_SHA256 #define CONFIG_SHA384 @@ -62,26 +60,6 @@ struct fdt_region; #include <hash.h> #include <linux/libfdt.h> #include <fdt_support.h> -# ifdef CONFIG_SPL_BUILD -# ifdef CONFIG_SPL_CRC32 -# define IMAGE_ENABLE_CRC32 1 -# endif -# ifdef CONFIG_SPL_MD5 -# define IMAGE_ENABLE_MD5 1 -# endif -# else -# define IMAGE_ENABLE_CRC32 1 -# define IMAGE_ENABLE_MD5 1 -# endif - -#ifndef IMAGE_ENABLE_CRC32 -#define IMAGE_ENABLE_CRC32 0 -#endif - -#ifndef IMAGE_ENABLE_MD5 -#define IMAGE_ENABLE_MD5 0 -#endif - #endif /* IMAGE_ENABLE_FIT */ #ifdef CONFIG_SYS_BOOT_GET_CMDLINE @@ -1334,6 +1312,10 @@ struct padding_algo { const uint8_t *hash, int hash_len); }; +/* Declare a new U-Boot padding algorithm handler */ +#define U_BOOT_PADDING_ALGO(__name) \ +ll_entry_declare(struct padding_algo, __name, paddings) + /** * image_get_checksum_algo() - Look up a checksum algorithm * diff --git a/include/mmc.h b/include/mmc.h index 0bf19de20e..b92e255340 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -726,6 +726,8 @@ struct mmc { */ u32 quirks; u8 hs400_tuning; + + enum bus_mode user_speed_mode; /* input speed mode from user */ }; #if CONFIG_IS_ENABLED(DM_MMC) diff --git a/include/pci.h b/include/pci.h index 4d771133b2..0fc22adffd 100644 --- a/include/pci.h +++ b/include/pci.h @@ -623,13 +623,9 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev * about a small subset of PCI devices. This is normally false. */ struct pci_controller { -#ifdef CONFIG_DM_PCI struct udevice *bus; struct udevice *ctlr; bool skip_auto_config_until_reloc; -#else - struct pci_controller *next; -#endif int first_busno; int last_busno; @@ -655,54 +651,12 @@ struct pci_controller { struct pci_config_table *config_table; void (*fixup_irq)(struct pci_controller *, pci_dev_t); -#ifndef CONFIG_DM_PCI - /* Low-level architecture-dependent routines */ - int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); - int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); - int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *); - int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); - int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); - int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); -#endif /* Used by auto config */ struct pci_region *pci_mem, *pci_io, *pci_prefetch; - -#ifndef CONFIG_DM_PCI - int current_busno; - - void *priv_data; -#endif }; -#ifndef CONFIG_DM_PCI -static inline void pci_set_ops(struct pci_controller *hose, - int (*read_byte)(struct pci_controller*, - pci_dev_t, int where, u8 *), - int (*read_word)(struct pci_controller*, - pci_dev_t, int where, u16 *), - int (*read_dword)(struct pci_controller*, - pci_dev_t, int where, u32 *), - int (*write_byte)(struct pci_controller*, - pci_dev_t, int where, u8), - int (*write_word)(struct pci_controller*, - pci_dev_t, int where, u16), - int (*write_dword)(struct pci_controller*, - pci_dev_t, int where, u32)) { - hose->read_byte = read_byte; - hose->read_word = read_word; - hose->read_dword = read_dword; - hose->write_byte = write_byte; - hose->write_word = write_word; - hose->write_dword = write_dword; -} -#endif - -#ifdef CONFIG_PCI_INDIRECT_BRIDGE -extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); -#endif - -#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) +#if defined(CONFIG_DM_PCI_COMPAT) extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, pci_addr_t addr, unsigned long flags); extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, @@ -752,15 +706,6 @@ extern int pci_hose_write_config_dword(struct pci_controller *hose, pci_dev_t dev, int where, u32 val); #endif -#ifndef CONFIG_DM_PCI -extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); -extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); -extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); -extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); -extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); -extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); -#endif - void pciauto_region_init(struct pci_region *res); void pciauto_region_align(struct pci_region *res, pci_size_t size); void pciauto_config_init(struct pci_controller *hose); @@ -780,7 +725,7 @@ void pciauto_config_init(struct pci_controller *hose); int pciauto_region_allocate(struct pci_region *res, pci_size_t size, pci_addr_t *bar, bool supports_64bit); -#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) +#if defined(CONFIG_DM_PCI_COMPAT) extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, pci_dev_t dev, int where, u8 *val); extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, @@ -827,7 +772,7 @@ int pci_find_next_ext_capability(struct pci_controller *hose, int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev, int cap); -#endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */ +#endif /* defined(CONFIG_DM_PCI_COMPAT) */ const char * pci_class_str(u8 class); int pci_last_busno(void); @@ -890,7 +835,6 @@ enum pci_size_t { struct udevice; -#ifdef CONFIG_DM_PCI /** * struct pci_child_plat - information stored about each PCI device * @@ -1691,8 +1635,6 @@ int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp); */ extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev); -#endif /* CONFIG_DM_PCI */ - /** * PCI_DEVICE - macro used to describe a specific pci device * @vend: the 16 bit PCI Vendor ID diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h index e5cb923d77..d61364c0ae 100644 --- a/include/u-boot/md5.h +++ b/include/u-boot/md5.h @@ -8,6 +8,8 @@ #include "compiler.h" +#define MD5_SUM_LEN 16 + struct MD5Context { __u32 buf[4]; __u32 bits[2]; @@ -32,7 +34,7 @@ void md5 (unsigned char *input, int len, unsigned char output[16]); * 'output' must have enough space to hold 16 bytes. If 'chunk' Trigger the * watchdog every 'chunk_sz' bytes of input processed. */ -void md5_wd (unsigned char *input, int len, unsigned char output[16], - unsigned int chunk_sz); +void md5_wd(const unsigned char *input, unsigned int len, + unsigned char output[16], unsigned int chunk_sz); #endif /* _MD5_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 47f82f7ba4..034af724b5 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -373,14 +373,9 @@ config SHA256 The SHA256 algorithm produces a 256-bit (32-byte) hash value (digest). -config SHA512_ALGO - bool "Enable SHA512 algorithm" - help - This option enables support of internal SHA512 algorithm. config SHA512 bool "Enable SHA512 support" - depends on SHA512_ALGO help This option enables support of hashing using SHA512 algorithm. The hash is calculated in software. @@ -389,10 +384,11 @@ config SHA512 config SHA384 bool "Enable SHA384 support" - depends on SHA512_ALGO + select SHA512 help This option enables support of hashing using SHA384 algorithm. - The hash is calculated in software. + The hash is calculated in software. This is also selects SHA512, + because these implementations share the bulk of the code.. The SHA384 algorithm produces a 384-bit (48-byte) hash value (digest). @@ -407,7 +403,7 @@ if SHA_HW_ACCEL config SHA512_HW_ACCEL bool "Enable hardware acceleration for SHA512" - depends on SHA512_ALGO + depends on SHA512 help This option enables hardware acceleration for the SHA384 and SHA512 hashing algorithms. This affects the 'hash' command and also the @@ -476,7 +472,7 @@ config LZMA config LZO bool "Enable LZO decompression support" help - This enables support for LZO compression algorithm.r + This enables support for the LZO compression algorithm. config GZIP bool "Enable gzip decompression support" @@ -535,7 +531,7 @@ config SPL_GZIP bool "Enable gzip decompression support for SPL build" select SPL_ZLIB help - This enables support for GZIP compression altorithm for SPL boot. + This enables support for the GZIP compression algorithm for SPL boot. config SPL_ZLIB bool diff --git a/lib/Makefile b/lib/Makefile index 2d29cdad1e..dfe772aaff 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -65,7 +65,7 @@ obj-$(CONFIG_$(SPL_)RSA) += rsa/ obj-$(CONFIG_HASH) += hash-checksum.o obj-$(CONFIG_SHA1) += sha1.o obj-$(CONFIG_SHA256) += sha256.o -obj-$(CONFIG_SHA512_ALGO) += sha512.o +obj-$(CONFIG_SHA512) += sha512.o obj-$(CONFIG_CRYPT_PW) += crypt/ obj-$(CONFIG_$(SPL_)ZLIB) += zlib/ @@ -87,7 +87,7 @@ endif ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o -obj-$(CONFIG_$(SPL_TPL_)HASH_SUPPORT) += crc16.o +obj-$(CONFIG_$(SPL_TPL_)HASH) += crc16.o obj-$(CONFIG_MMC_SPI_CRC_ON) += crc16.o obj-y += net_utils.o endif diff --git a/lib/crypt/Kconfig b/lib/crypt/Kconfig index 5495ae8d4c..a59d5c7d1d 100644 --- a/lib/crypt/Kconfig +++ b/lib/crypt/Kconfig @@ -20,7 +20,6 @@ config CRYPT_PW_SHA256 config CRYPT_PW_SHA512 bool "Provide sha512crypt" select SHA512 - select SHA512_ALGO help Enables support for the sha512crypt password-hashing algorithm. The prefix is "$6$". diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 0e5231b925..14bf5f7e92 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -10,6 +10,7 @@ config EFI_LOADER depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT # We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT + depends on BLK default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8 select LIB_UUID select PARTITION_UUIDS @@ -314,7 +315,6 @@ config EFI_TCG2_PROTOCOL depends on TPM_V2 select SHA1 select SHA256 - select SHA512_ALGO select SHA384 select SHA512 select HASH diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index a0eb63fceb..e9572d4d5d 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -801,6 +801,23 @@ efi_status_t efi_check_pe(void *buffer, size_t size, void **nt_header) } /** + * section_size() - determine size of section + * + * The size of a section in memory if normally given by VirtualSize. + * If VirtualSize is not provided, use SizeOfRawData. + * + * @sec: section header + * Return: size of section in memory + */ +static u32 section_size(IMAGE_SECTION_HEADER *sec) +{ + if (sec->Misc.VirtualSize) + return sec->Misc.VirtualSize; + else + return sec->SizeOfRawData; +} + +/** * efi_load_pe() - relocate EFI binary * * This function loads all sections from a PE binary into a newly reserved @@ -869,8 +886,9 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, /* Calculate upper virtual address boundary */ for (i = num_sections - 1; i >= 0; i--) { IMAGE_SECTION_HEADER *sec = §ions[i]; + virt_size = max_t(unsigned long, virt_size, - sec->VirtualAddress + sec->Misc.VirtualSize); + sec->VirtualAddress + section_size(sec)); } /* Read 32/64bit specific header bits */ @@ -880,6 +898,7 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, image_base = opt->ImageBase; efi_set_code_and_data_type(loaded_image_info, opt->Subsystem); handle->image_type = opt->Subsystem; + virt_size = ALIGN(virt_size, opt->SectionAlignment); efi_reloc = efi_alloc(virt_size, loaded_image_info->image_code_type); if (!efi_reloc) { @@ -890,12 +909,12 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, handle->entry = efi_reloc + opt->AddressOfEntryPoint; rel_size = opt->DataDirectory[rel_idx].Size; rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress; - virt_size = ALIGN(virt_size, opt->SectionAlignment); } else if (nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR32_MAGIC) { IMAGE_OPTIONAL_HEADER32 *opt = &nt->OptionalHeader; image_base = opt->ImageBase; efi_set_code_and_data_type(loaded_image_info, opt->Subsystem); handle->image_type = opt->Subsystem; + virt_size = ALIGN(virt_size, opt->SectionAlignment); efi_reloc = efi_alloc(virt_size, loaded_image_info->image_code_type); if (!efi_reloc) { @@ -906,7 +925,6 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, handle->entry = efi_reloc + opt->AddressOfEntryPoint; rel_size = opt->DataDirectory[rel_idx].Size; rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress; - virt_size = ALIGN(virt_size, opt->SectionAlignment); } else { log_err("Invalid optional header magic %x\n", nt->OptionalHeader.Magic); @@ -931,11 +949,16 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, /* Load sections into RAM */ for (i = num_sections - 1; i >= 0; i--) { IMAGE_SECTION_HEADER *sec = §ions[i]; - memset(efi_reloc + sec->VirtualAddress, 0, - sec->Misc.VirtualSize); + u32 copy_size = section_size(sec); + + if (copy_size > sec->SizeOfRawData) { + copy_size = sec->SizeOfRawData; + memset(efi_reloc + sec->VirtualAddress, 0, + sec->Misc.VirtualSize); + } memcpy(efi_reloc + sec->VirtualAddress, efi + sec->PointerToRawData, - min(sec->Misc.VirtualSize, sec->SizeOfRawData)); + copy_size); } /* Run through relocations */ diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index 35e69b9112..cb48919223 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -607,8 +607,8 @@ efi_tcg2_get_capability(struct efi_tcg2_protocol *this, goto out; } - if (capability->size < boot_service_capability_min) { - capability->size = boot_service_capability_min; + if (capability->size < BOOT_SERVICE_CAPABILITY_MIN) { + capability->size = BOOT_SERVICE_CAPABILITY_MIN; efi_ret = EFI_BUFFER_TOO_SMALL; goto out; } @@ -708,6 +708,18 @@ efi_tcg2_get_eventlog(struct efi_tcg2_protocol *this, EFI_ENTRY("%p, %u, %p, %p, %p", this, log_format, event_log_location, event_log_last_entry, event_log_truncated); + if (!this || !event_log_location || !event_log_last_entry || + !event_log_truncated) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + + /* Only support TPMV2 */ + if (log_format != TCG2_EVENT_LOG_FORMAT_TCG_2) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + ret = platform_get_tpm2_device(&dev); if (ret != EFI_SUCCESS) { event_log_location = NULL; @@ -853,20 +865,19 @@ efi_status_t tcg2_measure_pe_image(void *efi, u64 efi_size, if (ret != EFI_SUCCESS) return ret; - ret = EFI_CALL(efi_search_protocol(&handle->header, - &efi_guid_loaded_image_device_path, - &handler)); + ret = efi_search_protocol(&handle->header, + &efi_guid_loaded_image_device_path, &handler); if (ret != EFI_SUCCESS) return ret; - device_path = EFI_CALL(handler->protocol_interface); + device_path = handler->protocol_interface; device_path_length = efi_dp_size(device_path); if (device_path_length > 0) { /* add end node size */ device_path_length += sizeof(struct efi_device_path); } event_size = sizeof(struct uefi_image_load_event) + device_path_length; - image_load_event = (struct uefi_image_load_event *)malloc(event_size); + image_load_event = calloc(1, event_size); if (!image_load_event) return EFI_OUT_OF_RESOURCES; @@ -889,10 +900,8 @@ efi_status_t tcg2_measure_pe_image(void *efi, u64 efi_size, goto out; } - if (device_path_length > 0) { - memcpy(image_load_event->device_path, device_path, - device_path_length); - } + /* device_path_length might be zero */ + memcpy(image_load_event->device_path, device_path, device_path_length); ret = tcg2_agile_log_append(pcr_index, event_type, &digest_list, event_size, (u8 *)image_load_event); @@ -946,7 +955,7 @@ efi_tcg2_hash_log_extend_event(struct efi_tcg2_protocol *this, u64 flags, goto out; } - if (efi_tcg_event->header.pcr_index > TPM2_MAX_PCRS) { + if (efi_tcg_event->header.pcr_index > EFI_TCG2_MAX_PCR_INDEX) { ret = EFI_INVALID_PARAMETER; goto out; } @@ -965,6 +974,7 @@ efi_tcg2_hash_log_extend_event(struct efi_tcg2_protocol *this, u64 flags, data_to_hash_len, (void **)&nt); if (ret != EFI_SUCCESS) { log_err("Not a valid PE-COFF file\n"); + ret = EFI_UNSUPPORTED; goto out; } ret = tcg2_hash_pe_image((void *)(uintptr_t)data_to_hash, @@ -1038,9 +1048,15 @@ efi_tcg2_get_active_pcr_banks(struct efi_tcg2_protocol *this, { efi_status_t ret; + if (!this || !active_pcr_banks) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + EFI_ENTRY("%p, %p", this, active_pcr_banks); ret = __get_active_pcr_banks(active_pcr_banks); +out: return EFI_EXIT(ret); } diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c index 3d92afe2eb..a00bbf1620 100644 --- a/lib/efi_loader/efi_var_common.c +++ b/lib/efi_loader/efi_var_common.c @@ -32,10 +32,10 @@ static const struct efi_auth_var_name_type name_type[] = { {u"KEK", &efi_global_variable_guid, EFI_AUTH_VAR_KEK}, {u"db", &efi_guid_image_security_database, EFI_AUTH_VAR_DB}, {u"dbx", &efi_guid_image_security_database, EFI_AUTH_VAR_DBX}, - /* not used yet {u"dbt", &efi_guid_image_security_database, EFI_AUTH_VAR_DBT}, {u"dbr", &efi_guid_image_security_database, EFI_AUTH_VAR_DBR}, - */ + {u"AuditMode", &efi_global_variable_guid, EFI_AUTH_MODE}, + {u"DeployedMode", &efi_global_variable_guid, EFI_AUTH_MODE}, }; static bool efi_secure_boot; @@ -314,17 +314,40 @@ err: efi_status_t efi_init_secure_state(void) { - enum efi_secure_mode mode = EFI_MODE_SETUP; + enum efi_secure_mode mode; u8 efi_vendor_keys = 0; - efi_uintn_t size = 0; + efi_uintn_t size; efi_status_t ret; - - ret = efi_get_variable_int(L"PK", &efi_global_variable_guid, - NULL, &size, NULL, NULL); - if (ret == EFI_BUFFER_TOO_SMALL) { - if (IS_ENABLED(CONFIG_EFI_SECURE_BOOT)) - mode = EFI_MODE_USER; + u8 deployed_mode = 0; + u8 audit_mode = 0; + u8 setup_mode = 1; + + if (IS_ENABLED(CONFIG_EFI_SECURE_BOOT)) { + size = sizeof(deployed_mode); + ret = efi_get_variable_int(u"DeployedMode", &efi_global_variable_guid, + NULL, &size, &deployed_mode, NULL); + size = sizeof(audit_mode); + ret = efi_get_variable_int(u"AuditMode", &efi_global_variable_guid, + NULL, &size, &audit_mode, NULL); + size = 0; + ret = efi_get_variable_int(u"PK", &efi_global_variable_guid, + NULL, &size, NULL, NULL); + if (ret == EFI_BUFFER_TOO_SMALL) { + setup_mode = 0; + audit_mode = 0; + } else { + setup_mode = 1; + deployed_mode = 0; + } } + if (deployed_mode) + mode = EFI_MODE_DEPLOYED; + else if (audit_mode) + mode = EFI_MODE_AUDIT; + else if (setup_mode) + mode = EFI_MODE_SETUP; + else + mode = EFI_MODE_USER; ret = efi_transfer_secure_state(mode); if (ret != EFI_SUCCESS) diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c index de076b8cbc..c7c6805ed0 100644 --- a/lib/efi_loader/efi_var_file.c +++ b/lib/efi_loader/efi_var_file.c @@ -148,9 +148,10 @@ error: #endif } -efi_status_t efi_var_restore(struct efi_var_file *buf) +efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe) { struct efi_var_entry *var, *last_var; + u16 *data; efi_status_t ret; if (buf->reserved || buf->magic != EFI_VAR_FILE_MAGIC || @@ -160,21 +161,29 @@ efi_status_t efi_var_restore(struct efi_var_file *buf) return EFI_INVALID_PARAMETER; } - var = buf->var; last_var = (struct efi_var_entry *)((u8 *)buf + buf->length); - while (var < last_var) { - u16 *data = var->name + u16_strlen(var->name) + 1; - - if (var->attr & EFI_VARIABLE_NON_VOLATILE && var->length) { - ret = efi_var_mem_ins(var->name, &var->guid, var->attr, - var->length, data, 0, NULL, - var->time); - if (ret != EFI_SUCCESS) - log_err("Failed to set EFI variable %ls\n", - var->name); - } - var = (struct efi_var_entry *) - ALIGN((uintptr_t)data + var->length, 8); + for (var = buf->var; var < last_var; + var = (struct efi_var_entry *) + ALIGN((uintptr_t)data + var->length, 8)) { + + data = var->name + u16_strlen(var->name) + 1; + + /* + * Secure boot related and non-volatile variables shall only be + * restored from U-Boot's preseed. + */ + if (!safe && + (efi_auth_var_get_type(var->name, &var->guid) != + EFI_AUTH_VAR_NONE || + !(var->attr & EFI_VARIABLE_NON_VOLATILE))) + continue; + if (!var->length) + continue; + ret = efi_var_mem_ins(var->name, &var->guid, var->attr, + var->length, data, 0, NULL, + var->time); + if (ret != EFI_SUCCESS) + log_err("Failed to set EFI variable %ls\n", var->name); } return EFI_SUCCESS; } @@ -213,7 +222,7 @@ efi_status_t efi_var_from_file(void) log_err("Failed to load EFI variables\n"); goto error; } - if (buf->length != len || efi_var_restore(buf) != EFI_SUCCESS) + if (buf->length != len || efi_var_restore(buf, false) != EFI_SUCCESS) log_err("Invalid EFI variables file\n"); error: free(buf); diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index ba0874e9e7..fa2b6bc7a8 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -247,7 +247,7 @@ efi_status_t efi_set_variable_int(u16 *variable_name, const efi_guid_t *vendor, return EFI_WRITE_PROTECTED; if (IS_ENABLED(CONFIG_EFI_VARIABLES_PRESEED)) { - if (var_type != EFI_AUTH_VAR_NONE) + if (var_type >= EFI_AUTH_VAR_PK) return EFI_WRITE_PROTECTED; } @@ -268,7 +268,7 @@ efi_status_t efi_set_variable_int(u16 *variable_name, const efi_guid_t *vendor, return EFI_NOT_FOUND; } - if (var_type != EFI_AUTH_VAR_NONE) { + if (var_type >= EFI_AUTH_VAR_PK) { /* authentication is mandatory */ if (!(attributes & EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS)) { @@ -426,7 +426,7 @@ efi_status_t efi_init_variables(void) if (IS_ENABLED(CONFIG_EFI_VARIABLES_PRESEED)) { ret = efi_var_restore((struct efi_var_file *) - __efi_var_file_begin); + __efi_var_file_begin, true); if (ret != EFI_SUCCESS) log_err("Invalid EFI variable seed\n"); } diff --git a/lib/efi_loader/efi_watchdog.c b/lib/efi_loader/efi_watchdog.c index 61ea0f7926..87ca6c5b0b 100644 --- a/lib/efi_loader/efi_watchdog.c +++ b/lib/efi_loader/efi_watchdog.c @@ -27,8 +27,7 @@ static void EFIAPI efi_watchdog_timer_notify(struct efi_event *event, EFI_ENTRY("%p, %p", event, context); printf("\nEFI: Watchdog timeout\n"); - EFI_CALL_VOID(efi_runtime_services.reset_system(EFI_RESET_COLD, - EFI_SUCCESS, 0, NULL)); + do_reset(NULL, 0, 0, NULL); EFI_EXIT(EFI_UNSUPPORTED); } diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 337c4443b0..7358cb6dd1 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -190,7 +190,6 @@ fdt_addr_t fdtdec_get_addr(const void *blob, int node, const char *prop_name) return fdtdec_get_addr_size(blob, node, prop_name, NULL); } -#if CONFIG_IS_ENABLED(PCI) && defined(CONFIG_DM_PCI) int fdtdec_get_pci_vendev(const void *blob, int node, u16 *vendor, u16 *device) { const char *list, *end; @@ -238,7 +237,15 @@ int fdtdec_get_pci_bar32(const struct udevice *dev, struct fdt_pci_addr *addr, return -EINVAL; barnum = (barnum - PCI_BASE_ADDRESS_0) / 4; + + /* + * There is a strange toolchain bug with nds32 which complains about + * an undefined reference here, even if fdtdec_get_pci_bar32() is never + * called. An #ifdef seems to be the only fix! + */ +#if !IS_ENABLED(CONFIG_NDS32) *bar = dm_pci_read_bar32(dev, barnum); +#endif return 0; } @@ -258,7 +265,6 @@ int fdtdec_get_pci_bus_range(const void *blob, int node, return 0; } -#endif uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name, uint64_t default_val) @@ -284,12 +284,12 @@ md5 (unsigned char *input, int len, unsigned char output[16]) * watchdog every 'chunk_sz' bytes of input processed. */ void -md5_wd (unsigned char *input, int len, unsigned char output[16], +md5_wd(const unsigned char *input, unsigned int len, unsigned char output[16], unsigned int chunk_sz) { struct MD5Context context; #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) - unsigned char *end, *curr; + const unsigned char *end, *curr; int chunk; #endif diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index 64db1429c1..c27a784c42 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -251,7 +251,7 @@ static int rsa_engine_get_priv_key(const char *keydir, const char *name, snprintf(key_id, sizeof(key_id), "%s%s", keydir, name); - else if (keydir) + else if (name) snprintf(key_id, sizeof(key_id), "%s", name ? name : ""); diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index 3840764e42..ad6d33d043 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -95,6 +95,13 @@ int padding_pkcs_15_verify(struct image_sign_info *info, return 0; } +#ifndef USE_HOSTCC +U_BOOT_PADDING_ALGO(pkcs_15) = { + .name = "pkcs-1.5", + .verify = padding_pkcs_15_verify, +}; +#endif + #ifdef CONFIG_FIT_RSASSA_PSS static void u32_i2osp(uint32_t val, uint8_t *buf) { @@ -296,6 +303,14 @@ out: return ret; } + +#ifndef USE_HOSTCC +U_BOOT_PADDING_ALGO(pss) = { + .name = "pss", + .verify = padding_pss_verify, +}; +#endif + #endif #if CONFIG_IS_ENABLED(FIT_SIGNATURE) || CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY) diff --git a/lib/sha512.c b/lib/sha512.c index 35f31e3dc5..a421f249ba 100644 --- a/lib/sha512.c +++ b/lib/sha512.c @@ -320,7 +320,6 @@ void sha384_csum_wd(const unsigned char *input, unsigned int ilen, #endif -#if defined(CONFIG_SHA512) void sha512_starts(sha512_context * ctx) { ctx->state[0] = SHA512_H0; @@ -381,4 +380,3 @@ void sha512_csum_wd(const unsigned char *input, unsigned int ilen, sha512_finish(&ctx, output); } -#endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 6abb18b7ae..c98decb6f9 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -138,7 +138,6 @@ CONFIG_CLOCKS CONFIG_CLOCK_SYNTHESIZER CONFIG_CM922T_XA10 CONFIG_CMDLINE_PS_SUPPORT -CONFIG_CMDLINE_TAG CONFIG_CM_INIT CONFIG_CM_MULTIPLE_SSRAM CONFIG_CM_REMAP @@ -637,7 +636,6 @@ CONFIG_IMX6_PWM_PER_CLK CONFIG_IMX_HDMI CONFIG_IMX_VIDEO_SKIP CONFIG_INETSPACE_V2 -CONFIG_INITRD_TAG CONFIG_INIT_IGNORE_ERROR CONFIG_INI_ALLOW_MULTILINE CONFIG_INI_CASE_INSENSITIVE @@ -805,8 +803,6 @@ CONFIG_M520x CONFIG_M5301x CONFIG_MACB_SEARCH_PHY CONFIG_MACH_OMAPL138_LCDK -CONFIG_MACH_TYPE -CONFIG_MACH_TYPE_COMPAT_REV CONFIG_MACRESET_TIMEOUT CONFIG_MALLOC_F_ADDR CONFIG_MALTA @@ -1094,7 +1090,6 @@ CONFIG_RESET_TO_RETRY CONFIG_RESET_VECTOR_ADDRESS CONFIG_RESTORE_FLASH CONFIG_RES_BLOCK_SIZE -CONFIG_REVISION_TAG CONFIG_RMII CONFIG_RMSTP0_ENA CONFIG_RMSTP10_ENA @@ -1167,14 +1162,11 @@ CONFIG_SERIAL_FLASH CONFIG_SERIAL_HW_FLOW_CONTROL CONFIG_SERIAL_MULTI CONFIG_SERIAL_SOFTWARE_FIFO -CONFIG_SERIAL_TAG CONFIG_SERIRQ_CONTINUOUS_MODE CONFIG_SERVERIP CONFIG_SETUP_INITRD_TAG -CONFIG_SETUP_MEMORY_TAGS CONFIG_SET_BOOTARGS CONFIG_SET_DFU_ALT_BUF_LEN -CONFIG_SFIO CONFIG_SGI_IP28 CONFIG_SH73A0 CONFIG_SH7751_PCI @@ -1197,7 +1189,6 @@ CONFIG_SH_QSPI_BASE CONFIG_SH_SCIF_CLK_FREQ CONFIG_SH_SDHI_FREQ CONFIG_SH_SDRAM_OFFSET -CONFIG_SIEMENS_MACH_TYPE CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION CONFIG_SKIP_TRUNOFF_WATCHDOG CONFIG_SLIC diff --git a/test/dm/Makefile b/test/dm/Makefile index 516f69d61c..55162e9499 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -65,7 +65,7 @@ obj-y += of_extra.o obj-$(CONFIG_OSD) += osd.o obj-$(CONFIG_DM_VIDEO) += panel.o obj-$(CONFIG_EFI_PARTITION) += part.o -obj-$(CONFIG_DM_PCI) += pci.o +obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_P2SB) += p2sb.o obj-$(CONFIG_PCI_ENDPOINT) += pci_ep.o obj-$(CONFIG_PCH) += pch.o diff --git a/tools/k3_fit_atf.sh b/tools/k3_fit_atf.sh index 3a476ced98..7bc07ad074 100755 --- a/tools/k3_fit_atf.sh +++ b/tools/k3_fit_atf.sh @@ -67,8 +67,8 @@ cat << __HEADER_EOF arch = "arm32"; compression = "none"; os = "DM"; - load = <0xa0000000>; - entry = <0xa0000000>; + load = <0x89000000>; + entry = <0x89000000>; }; spl { description = "SPL (64-bit)"; diff --git a/tools/kwbimage.c b/tools/kwbimage.c index 00cb338d64..d200ff2425 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -5,8 +5,6 @@ * * (C) Copyright 2013 Thomas Petazzoni * <thomas.petazzoni@free-electrons.com> - * - * Not implemented: support for the register headers in v1 images */ #include "imagetool.h" @@ -59,13 +57,13 @@ struct hash_v1 { }; struct boot_mode boot_modes[] = { - { 0x4D, "i2c" }, - { 0x5A, "spi" }, - { 0x8B, "nand" }, - { 0x78, "sata" }, - { 0x9C, "pex" }, - { 0x69, "uart" }, - { 0xAE, "sdio" }, + { IBR_HDR_I2C_ID, "i2c" }, + { IBR_HDR_SPI_ID, "spi" }, + { IBR_HDR_NAND_ID, "nand" }, + { IBR_HDR_SATA_ID, "sata" }, + { IBR_HDR_PEX_ID, "pex" }, + { IBR_HDR_UART_ID, "uart" }, + { IBR_HDR_SDIO_ID, "sdio" }, {}, }; @@ -75,10 +73,10 @@ struct nand_ecc_mode { }; struct nand_ecc_mode nand_ecc_modes[] = { - { 0x00, "default" }, - { 0x01, "hamming" }, - { 0x02, "rs" }, - { 0x03, "disabled" }, + { IBR_HDR_ECC_DEFAULT, "default" }, + { IBR_HDR_ECC_FORCED_HAMMING, "hamming" }, + { IBR_HDR_ECC_FORCED_RS, "rs" }, + { IBR_HDR_ECC_DISABLED, "disabled" }, {}, }; @@ -832,6 +830,12 @@ static int kwb_dump_fuse_cmds(struct secure_hdr_v1 *sec_hdr) if (!strcmp(e->name, "a38x")) { FILE *out = fopen("kwb_fuses_a38x.txt", "w+"); + if (!out) { + fprintf(stderr, "Couldn't open eFuse settings: '%s': %s\n", + "kwb_fuses_a38x.txt", strerror(errno)); + return -ENOENT; + } + kwb_dump_fuse_cmds_38x(out, sec_hdr); fclose(out); goto done; @@ -1060,6 +1064,11 @@ int export_pub_kak_hash(RSA *kak, struct secure_hdr_v1 *secure_hdr) int res; hashf = fopen("pub_kak_hash.txt", "w"); + if (!hashf) { + fprintf(stderr, "Couldn't open hash file: '%s': %s\n", + "pub_kak_hash.txt", strerror(errno)); + return 1; + } res = kwb_export_pubkey(kak, &secure_hdr->kak, hashf, "KAK"); @@ -1076,7 +1085,7 @@ int kwb_sign_csk_with_kak(struct image_tool_params *params, int csk_idx = image_get_csk_index(); struct sig_v1 tmp_sig; - if (csk_idx >= 16) { + if (csk_idx < 0 || csk_idx > 15) { fprintf(stderr, "Invalid CSK index %d\n", csk_idx); return 1; } @@ -1670,6 +1679,9 @@ static int kwbimage_verify_header(unsigned char *ptr, int image_size, if (mhdr->ext & 0x1) { struct ext_hdr_v0 *ext_hdr; + if (header_size + sizeof(*ext_hdr) > image_size) + return -FDT_ERR_BADSTRUCTURE; + ext_hdr = (struct ext_hdr_v0 *) (ptr + sizeof(struct main_hdr_v0)); checksum = image_checksum8(ext_hdr, @@ -1678,9 +1690,7 @@ static int kwbimage_verify_header(unsigned char *ptr, int image_size, if (checksum != ext_hdr->checksum) return -FDT_ERR_BADSTRUCTURE; } - } - - if (image_version((void *)ptr) == 1) { + } else if (image_version((void *)ptr) == 1) { struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr; uint32_t offset; uint32_t size; @@ -1744,12 +1754,14 @@ static int kwbimage_verify_header(unsigned char *ptr, int image_size, return -FDT_ERR_BADSTRUCTURE; size = le32_to_cpu(mhdr->blocksize); - if (offset + size > image_size || size % 4 != 0) + if (size < 4 || offset + size > image_size || size % 4 != 0) return -FDT_ERR_BADSTRUCTURE; if (image_checksum32(ptr + offset, size - 4) != *(uint32_t *)(ptr + offset + size - 4)) return -FDT_ERR_BADSTRUCTURE; + } else { + return -FDT_ERR_BADSTRUCTURE; } return 0; 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