diff options
167 files changed, 1776 insertions, 5450 deletions
@@ -1476,6 +1476,17 @@ cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ u-boot.img > $@ || rm -f $@ u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE $(call if_changed,socboot) + +quiet_cmd_socnandboot = SOCNANDBOOT $@ +cmd_socnandboot = dd if=/dev/zero of=spl/u-boot-spl.pad bs=64 count=1024 ; \ + cat spl/u-boot-spl.sfp spl/u-boot-spl.pad \ + spl/u-boot-spl.sfp spl/u-boot-spl.pad \ + spl/u-boot-spl.sfp spl/u-boot-spl.pad \ + spl/u-boot-spl.sfp spl/u-boot-spl.pad \ + u-boot.img > $@ || rm -f $@ spl/u-boot-spl.pad +u-boot-with-nand-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE + $(call if_changed,socnandboot) + endif ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c index 30c7b37f1a9..7a1053cebb4 100644 --- a/arch/arm/cpu/armv7/ls102xa/clock.c +++ b/arch/arm/cpu/armv7/ls102xa/clock.c @@ -109,8 +109,6 @@ unsigned int mxc_get_clock(enum mxc_clock clk) switch (clk) { case MXC_I2C_CLK: return get_bus_freq(0) / 2; - case MXC_ESDHC_CLK: - return get_bus_freq(0); case MXC_DSPI_CLK: return get_bus_freq(0) / 2; case MXC_UART_CLK: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index df4df9aca79..6d82cfeb58e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -227,16 +227,6 @@ ulong get_ddr_freq(ulong dummy) return gd->mem_clk; } -#ifdef CONFIG_FSL_ESDHC -int get_sdhc_freq(ulong dummy) -{ - if (!gd->arch.sdhc_clk) - get_clocks(); - - return gd->arch.sdhc_clk; -} -#endif - int get_serial_clock(void) { return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; @@ -264,11 +254,6 @@ unsigned int mxc_get_clock(enum mxc_clock clk) switch (clk) { case MXC_I2C_CLK: return get_i2c_freq(0); -#if defined(CONFIG_FSL_ESDHC) - case MXC_ESDHC_CLK: - case MXC_ESDHC2_CLK: - return get_sdhc_freq(0); -#endif case MXC_DSPI_CLK: return get_dspi_freq(0); #ifdef CONFIG_FSL_LPUART diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index bbd550b0365..ede96742aad 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -236,16 +236,6 @@ int get_dspi_freq(ulong dummy) return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV; } -#ifdef CONFIG_FSL_ESDHC -int get_sdhc_freq(ulong dummy) -{ - if (!gd->arch.sdhc_clk) - get_clocks(); - - return gd->arch.sdhc_clk; -} -#endif - int get_serial_clock(void) { return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; @@ -256,11 +246,6 @@ unsigned int mxc_get_clock(enum mxc_clock clk) switch (clk) { case MXC_I2C_CLK: return get_i2c_freq(0); -#if defined(CONFIG_FSL_ESDHC) - case MXC_ESDHC_CLK: - case MXC_ESDHC2_CLK: - return get_sdhc_freq(0); -#endif case MXC_DSPI_CLK: return get_dspi_freq(0); default: diff --git a/arch/arm/dts/st-pincfg.h b/arch/arm/dts/st-pincfg.h index 4851c387d52..d8055120229 100644 --- a/arch/arm/dts/st-pincfg.h +++ b/arch/arm/dts/st-pincfg.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ST_PINCFG_H_ #define _ST_PINCFG_H_ diff --git a/arch/arm/dts/stm32429i-eval.dts b/arch/arm/dts/stm32429i-eval.dts index 1eec9511889..c5afa0c1620 100644 --- a/arch/arm/dts/stm32429i-eval.dts +++ b/arch/arm/dts/stm32429i-eval.dts @@ -20,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x2000000>; }; @@ -39,18 +40,18 @@ dma-ranges = <0xc0000000 0x0 0x10000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + vdda: regulator-vdda { + compatible = "regulator-fixed"; + regulator-name = "vdda"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; - reg_vref: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vref"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + vref: regulator-vref { + compatible = "regulator-fixed"; + regulator-name = "vref"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; leds { @@ -72,6 +73,7 @@ gpio_keys { compatible = "gpio-keys"; + #address-cells = <1>; #size-cells = <0>; autorepeat; button@0 { @@ -114,7 +116,8 @@ &adc { pinctrl-names = "default"; pinctrl-0 = <&adc3_in8_pin>; - vref-supply = <®_vref>; + vdda-supply = <&vdda>; + vref-supply = <&vref>; status = "okay"; adc3: adc@200 { st,adc-channels = <8>; @@ -227,7 +230,7 @@ pinctrl-0 = <&sdio_pins>; pinctrl-1 = <&sdio_pins_od>; bus-width = <4>; - max-frequency = <14000000>; + max-frequency = <12500000>; }; &timers1 { diff --git a/arch/arm/dts/stm32746g-eval.dts b/arch/arm/dts/stm32746g-eval.dts index 8c081eaf20f..d77eb53c6aa 100644 --- a/arch/arm/dts/stm32746g-eval.dts +++ b/arch/arm/dts/stm32746g-eval.dts @@ -1,49 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 /* * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; #include "stm32f746.dtsi" #include "stm32f746-pinctrl.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> / { model = "STMicroelectronics STM32746g-EVAL board"; @@ -55,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0xc0000000 0x2000000>; }; @@ -68,9 +34,15 @@ gpios = <&gpiof 10 1>; linux,default-trigger = "heartbeat"; }; + orange { + gpios = <&stmfx_pinctrl 17 1>; + }; red { gpios = <&gpiob 7 1>; }; + blue { + gpios = <&stmfx_pinctrl 19 1>; + }; }; gpio_keys { @@ -85,6 +57,43 @@ }; }; + joystick { + compatible = "gpio-keys"; + #size-cells = <0>; + pinctrl-0 = <&joystick_pins>; + pinctrl-names = "default"; + button-0 { + label = "JoySel"; + linux,code = <KEY_ENTER>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + }; + button-1 { + label = "JoyDown"; + linux,code = <KEY_DOWN>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + button-2 { + label = "JoyLeft"; + linux,code = <KEY_LEFT>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + }; + button-3 { + label = "JoyRight"; + linux,code = <KEY_RIGHT>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + }; + button-4 { + label = "JoyUp"; + linux,code = <KEY_UP>; + interrupt-parent = <&stmfx_pinctrl>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + }; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; @@ -114,6 +123,28 @@ i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; + + stmfx: stmfx@42 { + compatible = "st,stmfx-0300"; + reg = <0x42>; + interrupts = <8 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&gpioi>; + + stmfx_pinctrl: stmfx-pin-controller { + compatible = "st,stmfx-0300-pinctrl"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&stmfx_pinctrl 0 0 24>; + + joystick_pins: joystick { + pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; + drive-push-pull; + bias-pull-up; + }; + }; + }; }; &rtc { diff --git a/arch/arm/dts/stm32f4-pinctrl.dtsi b/arch/arm/dts/stm32f4-pinctrl.dtsi index 35202896c09..7ed68286ba5 100644 --- a/arch/arm/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/dts/stm32f4-pinctrl.dtsi @@ -1,43 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 /* * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/pinctrl/stm32-pinfunc.h> diff --git a/arch/arm/dts/stm32f429-disco.dts b/arch/arm/dts/stm32f429-disco.dts index d99f47aa724..3a83ef5f604 100644 --- a/arch/arm/dts/stm32f429-disco.dts +++ b/arch/arm/dts/stm32f429-disco.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 /* * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -55,6 +18,7 @@ }; memory { + device_type = "memory"; reg = <0x90000000 0x800000>; }; diff --git a/arch/arm/dts/stm32f429-pinctrl.dtsi b/arch/arm/dts/stm32f429-pinctrl.dtsi index 3e7a17d9112..575c7eecab0 100644 --- a/arch/arm/dts/stm32f429-pinctrl.dtsi +++ b/arch/arm/dts/stm32f429-pinctrl.dtsi @@ -1,43 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 /* * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "stm32f4-pinctrl.dtsi" diff --git a/arch/arm/dts/stm32f429.dtsi b/arch/arm/dts/stm32f429.dtsi index c5c029b9e36..db0b82e89ea 100644 --- a/arch/arm/dts/stm32f429.dtsi +++ b/arch/arm/dts/stm32f429.dtsi @@ -1,51 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 /* * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include "armv7-m.dtsi" #include <dt-bindings/clock/stm32fx-clock.h> #include <dt-bindings/mfd/stm32f4-rcc.h> / { + #address-cells = <1>; + #size-cells = <1>; + clocks { clk_hse: clk-hse { #clock-cells = <0>; @@ -73,6 +39,19 @@ }; soc { + romem: nvmem@1fff7800 { + compatible = "st,stm32f4-otp"; + reg = <0x1fff7800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ts_cal1: calib@22c { + reg = <0x22c 0x2>; + }; + ts_cal2: calib@22e { + reg = <0x22e 0x2>; + }; + }; + timer2: timer@40000000 { compatible = "st,stm32-timer"; reg = <0x40000000 0x400>; @@ -92,6 +71,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -121,6 +101,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -150,6 +131,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -178,6 +160,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -247,6 +230,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -268,6 +252,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; }; @@ -283,6 +268,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; }; @@ -309,6 +295,26 @@ status = "disabled"; }; + spi2: spi@40003800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40003800 0x400>; + interrupts = <36>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>; + status = "disabled"; + }; + + spi3: spi@40003c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40003c00 0x400>; + interrupts = <51>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>; + status = "disabled"; + }; + usart2: serial@40004400 { compatible = "st,stm32-uart"; reg = <0x40004400 0x400>; @@ -408,6 +414,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -429,6 +436,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -518,6 +526,26 @@ status = "disabled"; }; + spi1: spi@40013000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40013000 0x400>; + interrupts = <35>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>; + status = "disabled"; + }; + + spi4: spi@40013400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40013400 0x400>; + interrupts = <84>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>; + status = "disabled"; + }; + syscfg: system-config@40013800 { compatible = "syscon"; reg = <0x40013800 0x400>; @@ -542,6 +570,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -563,6 +592,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; }; @@ -578,10 +608,31 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; }; + spi5: spi@40015000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40015000 0x400>; + interrupts = <85>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>; + status = "disabled"; + }; + + spi6: spi@40015400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40015400 0x400>; + interrupts = <86>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>; + status = "disabled"; + }; + pwrcfg: power-config@40007000 { compatible = "syscon"; reg = <0x40007000 0x400>; diff --git a/arch/arm/dts/stm32f469-disco.dts b/arch/arm/dts/stm32f469-disco.dts index 3ceb84d8ba8..d50c38dc788 100644 --- a/arch/arm/dts/stm32f469-disco.dts +++ b/arch/arm/dts/stm32f469-disco.dts @@ -1,43 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 /* * Copyright 2016 - Lee Jones <lee.jones@linaro.org> * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -56,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x1000000>; }; diff --git a/arch/arm/dts/stm32f469-pinctrl.dtsi b/arch/arm/dts/stm32f469-pinctrl.dtsi index fff542662ee..1e2bb0191e6 100644 --- a/arch/arm/dts/stm32f469-pinctrl.dtsi +++ b/arch/arm/dts/stm32f469-pinctrl.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 /* * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "stm32f4-pinctrl.dtsi" diff --git a/arch/arm/dts/stm32f469.dtsi b/arch/arm/dts/stm32f469.dtsi index 0d58d40649f..69c862d973b 100644 --- a/arch/arm/dts/stm32f469.dtsi +++ b/arch/arm/dts/stm32f469.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */ #include "stm32f429.dtsi" diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index e3a7bd338d6..4fef0164cf5 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -1,43 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 /* * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -56,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0xC0000000 0x800000>; }; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index f48d06a80d1..3f312ab3a77 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -1,51 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 /* * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include "armv7-m.dtsi" #include <dt-bindings/clock/stm32fx-clock.h> #include <dt-bindings/mfd/stm32f7-rcc.h> / { + #address-cells = <1>; + #size-cells = <1>; + clocks { clk_hse: clk-hse { #clock-cells = <0>; @@ -92,6 +58,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -121,6 +88,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -150,6 +118,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -178,6 +147,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -247,6 +217,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -268,6 +239,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; }; @@ -283,6 +255,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; }; @@ -417,6 +390,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -438,6 +412,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -510,6 +485,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -531,6 +507,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; }; @@ -546,6 +523,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; }; diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts index 483d896e2bc..8d51e5b0fb8 100644 --- a/arch/arm/dts/stm32f769-disco.dts +++ b/arch/arm/dts/stm32f769-disco.dts @@ -1,43 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 /* * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -56,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0xC0000000 0x1000000>; }; @@ -101,6 +66,10 @@ }; }; +&rcc { + compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; +}; + &cec { pinctrl-0 = <&cec_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi index 99fa0e673a1..361c8e5d80f 100644 --- a/arch/arm/dts/stm32h7-u-boot.dtsi +++ b/arch/arm/dts/stm32h7-u-boot.dtsi @@ -61,17 +61,6 @@ st,sdram-refcount = <1539>; }; }; - - sdmmc1: sdmmc@52007000 { - compatible = "st,stm32-sdmmc2"; - reg = <0x52007000 0x1000>; - interrupts = <49>; - clocks = <&rcc SDMMC1_CK>; - resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; - st,idma = <1>; - cap-sd-highspeed; - cap-mmc-highspeed; - }; }; }; @@ -216,32 +205,6 @@ slew-rate = <3>; }; }; - - pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 { - pins { - pinmux = <STM32_PINMUX('B', 8, AF7)>, - <STM32_PINMUX('B', 9, AF7)>, - <STM32_PINMUX('C', 6, AF8)>, - <STM32_PINMUX('C', 7, AF8)>; - drive-push-pull; - slew-rate = <3>; - }; - }; - - sdmmc1_pins: sdmmc@0 { - pins { - pinmux = <STM32_PINMUX('C', 8, AF12)>, - <STM32_PINMUX('C', 9, AF12)>, - <STM32_PINMUX('C',10, AF12)>, - <STM32_PINMUX('C',11, AF12)>, - <STM32_PINMUX('C',12, AF12)>, - <STM32_PINMUX('D', 2, AF12)>; - - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - }; }; &pwrcfg { @@ -251,3 +214,7 @@ &rcc { u-boot,dm-pre-reloc; }; + +&sdmmc1 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +}; diff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi b/arch/arm/dts/stm32h743-pinctrl.dtsi index c823541a0d8..e3a5c537f3c 100644 --- a/arch/arm/dts/stm32h743-pinctrl.dtsi +++ b/arch/arm/dts/stm32h743-pinctrl.dtsi @@ -173,6 +173,89 @@ }; }; + ethernet_rmii: rmii@0 { + pins { + pinmux = <STM32_PINMUX('G', 11, AF11)>, + <STM32_PINMUX('G', 13, AF11)>, + <STM32_PINMUX('G', 12, AF11)>, + <STM32_PINMUX('C', 4, AF11)>, + <STM32_PINMUX('C', 5, AF11)>, + <STM32_PINMUX('A', 7, AF11)>, + <STM32_PINMUX('C', 1, AF11)>, + <STM32_PINMUX('A', 2, AF11)>, + <STM32_PINMUX('A', 1, AF11)>; + slew-rate = <2>; + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins { + pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */ + slew-rate = <3>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { + pins { + pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ + <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */ + }; + }; + usart1_pins: usart1@0 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */ diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index cbdd69ca9e7..4b4e7a99f74 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -1,52 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 /* * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include "armv7-m.dtsi" #include <dt-bindings/clock/stm32h7-clks.h> #include <dt-bindings/mfd/stm32h7-rcc.h> #include <dt-bindings/interrupt-controller/irq.h> / { + #address-cells = <1>; + #size-cells = <1>; + clocks { clk_hse: clk-hse { #clock-cells = <0>; @@ -337,6 +303,20 @@ dma-requests = <32>; }; + sdmmc1: sdmmc@52007000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x52007000 0x1000>; + interrupts = <49>; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC1_CK>; + clock-names = "apb_pclk"; + resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + }; + exti: interrupt-controller@58000000 { compatible = "st,stm32h7-exti"; interrupt-controller; @@ -511,6 +491,19 @@ status = "disabled"; }; }; + + mac: ethernet@40028000 { + compatible = "st,stm32-dwmac", "snps,dwmac-4.10a"; + reg = <0x40028000 0x8000>; + reg-names = "stmmaceth"; + interrupts = <61>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; + clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>; + st,syscon = <&syscfg 0x4>; + snps,pbl = <8>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi index 2d6b41bfb96..5965afcbe46 100644 --- a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi @@ -1,11 +1,3 @@ // SPDX-License-Identifier: GPL-2.0+ #include <stm32h7-u-boot.dtsi> - -&sdmmc1 { - status = "okay"; - pinctrl-0 = <&sdmmc1_pins>; - pinctrl-names = "default"; - bus-width = <4>; - cd-gpios = <&gpioi 8 1>; -}; diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts index 45e088c5574..43c30bfcbe5 100644 --- a/arch/arm/dts/stm32h743i-disco.dts +++ b/arch/arm/dts/stm32h743i-disco.dts @@ -1,43 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 /* * Copyright 2017 - Patrice Chotard <patrice.chotard@st.com> * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -54,18 +18,56 @@ }; memory { + device_type = "memory"; reg = <0xd0000000 0x2000000>; }; aliases { serial0 = &usart2; }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; &clk_hse { clock-frequency = <25000000>; }; +&mac { + status = "disabled"; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + &usart2 { pinctrl-0 = <&usart2_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi index 251977abe02..5965afcbe46 100644 --- a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi @@ -1,12 +1,3 @@ // SPDX-License-Identifier: GPL-2.0+ #include <stm32h7-u-boot.dtsi> - -&sdmmc1 { - status = "okay"; - pinctrl-0 = <&sdmmc1_pins>, - <&pinctrl_sdmmc1_level_shifter>; - pinctrl-names = "default"; - bus-width = <4>; - st,sig-dir; -}; diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts index 3f8e0c4a998..e4d3c58f3d9 100644 --- a/arch/arm/dts/stm32h743i-eval.dts +++ b/arch/arm/dts/stm32h743i-eval.dts @@ -54,6 +54,7 @@ }; memory { + device_type = "memory"; reg = <0xd0000000 0x2000000>; }; @@ -69,16 +70,24 @@ regulator-always-on; }; + v2v9_sd: regulator-v2v9_sd { + compatible = "regulator-fixed"; + regulator-name = "v2v9_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; clocks = <&rcc USB1ULPI_CK>; clock-names = "main_clk"; }; - }; &adc_12 { + vdda-supply = <&vdda>; vref-supply = <&vdda>; status = "okay"; adc1: adc@0 { @@ -104,6 +113,37 @@ status = "okay"; }; +&mac { + status = "disabled"; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; + broken-cd; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&v2v9_sd>; + status = "okay"; +}; + &usart1 { pinctrl-0 = <&usart1_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 4367e8dcf75..0d53396119f 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -565,7 +565,7 @@ }; }; - m_can1_sleep_pins_a: m_can1-sleep@0 { + m_can1_sleep_pins_a: m_can1-sleep-0 { pins { pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */ @@ -812,31 +812,80 @@ }; sdmmc2_b4_pins_a: sdmmc2-b4-0 { - pins { + pins1 { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ - <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ - slew-rate = <3>; + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ + slew-rate = <2>; drive-push-pull; bias-pull-up; }; }; + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ + <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ + <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ + }; + }; + sdmmc2_d47_pins_a: sdmmc2-d47-0 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ - slew-rate = <3>; + slew-rate = <1>; drive-push-pull; bias-pull-up; }; }; + sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ + }; + }; + spdifrx_pins_a: spdifrx-0 { pins { pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index 1ff681afb87..1104a70a65c 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -155,7 +155,10 @@ &sdmmc2_b4_pins_a { u-boot,dm-spl; - pins { + pins1 { + u-boot,dm-spl; + }; + pins2 { u-boot,dm-spl; }; }; diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index c210acc0aa2..46522530128 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -33,6 +33,42 @@ #size-cells = <1>; ranges; + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + gpu_reserved: gpu@d4000000 { reg = <0xd4000000 0x4000000>; no-map; @@ -48,6 +84,17 @@ default-state = "off"; }; }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP1-DK"; + routing = + "Playback" , "MCLK", + "Capture" , "MCLK", + "MICL" , "Mic Bias"; + dais = <&sai2a_port &sai2b_port>; + status = "okay"; + }; }; &cec { @@ -116,6 +163,39 @@ }; }; }; + + cs42l51: cs42l51@4a { + compatible = "cirrus,cs42l51"; + reg = <0x4a>; + #sound-dai-cells = <0>; + VL-supply = <&v3v3>; + VD-supply = <&v1v8_audio>; + VA-supply = <&v1v8_audio>; + VAHP-supply = <&v1v8_audio>; + reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; + clocks = <&sai2a>; + clock-names = "MCLK"; + status = "okay"; + + cs42l51_port: port { + #address-cells = <1>; + #size-cells = <0>; + + cs42l51_tx_endpoint: endpoint@0 { + reg = <0>; + remote-endpoint = <&sai2a_endpoint>; + frame-master; + bitclock-master; + }; + + cs42l51_rx_endpoint: endpoint@1 { + reg = <1>; + remote-endpoint = <&sai2b_endpoint>; + frame-master; + bitclock-master; + }; + }; + }; }; &i2c4 { @@ -308,8 +388,12 @@ }; &m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; status = "okay"; }; @@ -328,6 +412,51 @@ status = "okay"; }; +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>; + pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>; + status = "okay"; + + sai2a: audio-controller@4400b004 { + #clock-cells = <0>; + dma-names = "tx"; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + status = "okay"; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&cs42l51_tx_endpoint>; + format = "i2s"; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + }; + }; + + sai2b: audio-controller@4400b024 { + dma-names = "rx"; + st,sync = <&sai2a 2>; + clocks = <&rcc SAI2_K>, <&sai2a>; + clock-names = "sai_ck", "MCLK"; + status = "okay"; + + sai2b_port: port { + sai2b_endpoint: endpoint { + remote-endpoint = <&cs42l51_rx_endpoint>; + format = "i2s"; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + }; + }; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>; diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 4953a0db555..b2ac49472a7 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -174,7 +174,10 @@ &sdmmc2_b4_pins_a { u-boot,dm-spl; - pins { + pins1 { + u-boot,dm-spl; + }; + pins2 { u-boot,dm-spl; }; }; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index 1d9cc734f12..bc4d7e1ab5d 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -28,6 +28,42 @@ #size-cells = <1>; ranges; + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + gpu_reserved: gpu@e8000000 { reg = <0xe8000000 0x8000000>; no-map; @@ -176,10 +212,10 @@ regulator-over-current-protection; }; - bst_out: boost { + bst_out: boost { regulator-name = "bst_out"; interrupts = <IT_OCP_BOOST 0>; - }; + }; vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; @@ -218,8 +254,12 @@ }; &m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; status = "okay"; }; @@ -254,15 +294,18 @@ }; &sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; non-removable; no-sd; no-sdio; - st,sig-dir; st,neg-edge; bus-width = <8>; vmmc-supply = <&v3v3>; - vqmmc-supply = <&vdd>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index 23de232831c..89d29b50c3f 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -101,6 +101,7 @@ &dsi { #address-cells = <1>; #size-cells = <0>; + phy-dsi-supply = <®18>; status = "okay"; ports { @@ -165,7 +166,7 @@ #address-cells = <1>; #size-cells = <0>; - nand: nand@0 { + nand@0 { reg = <0>; nand-on-flash-bbt; #address-cells = <1>; diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index a6045dd682c..6c670cf9a36 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -109,6 +109,12 @@ }; }; + booster: regulator-booster { + compatible = "st,stm32mp1-booster"; + st,syscfg = <&syscfg>; + status = "disabled"; + }; + reboot { compatible = "syscon-reboot"; regmap = <&rcc>; @@ -140,6 +146,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -168,6 +175,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -194,6 +202,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -222,6 +231,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -279,6 +289,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -300,6 +311,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -321,6 +333,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -574,6 +587,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -604,6 +618,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -677,6 +692,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -701,6 +717,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; timer@15 { @@ -724,6 +741,7 @@ pwm { compatible = "st,stm32-pwm"; + #pwm-cells = <3>; status = "disabled"; }; @@ -990,6 +1008,7 @@ clocks = <&rcc ADC12>, <&rcc ADC12_K>; clock-names = "bus", "adc"; interrupt-controller; + st,syscfg = <&syscfg>; #interrupt-cells = <1>; #address-cells = <1>; #size-cells = <0>; @@ -1313,6 +1332,10 @@ <0x89010000 0x1000>, <0x89020000 0x1000>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>, + <&mdma1 20 0x10 0x12000a08 0x0 0x0>, + <&mdma1 21 0x10 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; clocks = <&rcc FMC_K>; resets = <&rcc FMC_R>; status = "disabled"; @@ -1323,6 +1346,9 @@ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; reg-names = "qspi", "qspi_mm"; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>, + <&mdma1 22 0x10 0x100008 0x0 0x0>; + dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; status = "disabled"; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h index b37a08d2653..95d6156476f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h @@ -14,8 +14,6 @@ enum mxc_clock { MXC_ARM_CLK = 0, MXC_BUS_CLK, MXC_UART_CLK, - MXC_ESDHC_CLK, - MXC_ESDHC2_CLK, MXC_I2C_CLK, MXC_DSPI_CLK, }; diff --git a/arch/arm/include/asm/arch-ls102xa/clock.h b/arch/arm/include/asm/arch-ls102xa/clock.h index bf67df561a0..e66e57f7598 100644 --- a/arch/arm/include/asm/arch-ls102xa/clock.h +++ b/arch/arm/include/asm/arch-ls102xa/clock.h @@ -12,7 +12,6 @@ enum mxc_clock { MXC_ARM_CLK = 0, MXC_UART_CLK, - MXC_ESDHC_CLK, MXC_I2C_CLK, MXC_DSPI_CLK, }; diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 31681b799d4..22042d0de09 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -79,6 +79,8 @@ static const struct { { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" }, /* Arria V */ { 0x2d03, "Arria V, D5", "av_d5" }, + /* Arria V ST/SX */ + { 0x2d13, "Arria V, ST/D3 or SX/B3", "av_st_d3" }, }; static int socfpga_fpga_id(const bool print_id) @@ -228,10 +230,13 @@ void do_bridge_reset(int enable, unsigned int mask) writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); writel(iswgrp_handoff[1], &nic301_regs->remap); + + writel(0x7, &reset_manager_base->brg_mod_reset); + writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); } else { writel(0, &sysmgr_regs->fpgaintfgrp_module); writel(0, &sdr_ctrl->fpgaport_rst); - writel(0, &reset_manager_base->brg_mod_reset); + writel(0x7, &reset_manager_base->brg_mod_reset); writel(1, &nic301_regs->remap); } } diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 47e63709ad8..408e4093754 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -138,6 +138,13 @@ void board_init_f(ulong dummy) if (ret) debug("Reset init failed: %d\n", ret); +#ifdef CONFIG_SPL_NAND_DENALI + struct socfpga_reset_manager *reset_manager_base = + (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; + + clrbits_le32(&reset_manager_base->per_mod_reset, BIT(4)); +#endif + /* enable console uart printing */ preloader_console_init(); diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index eb1f67dcccb..a3ae6030448 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -152,7 +152,6 @@ endchoice source "board/imgtec/boston/Kconfig" source "board/imgtec/malta/Kconfig" source "board/imgtec/xilfpga/Kconfig" -source "board/micronas/vct/Kconfig" source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" source "arch/mips/mach-mscc/Kconfig" diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 1e5e67804b8..fb3b203a245 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -24,6 +24,13 @@ single-cpu-affinity; last-interrupt-source = <255>; }; + + esdhc: esdhc@2e000 { + compatible = "fsl,esdhc"; + reg = <0x2e000 0x1000>; + /* Filled in by U-Boot */ + clock-frequency = <0>; + }; }; /* PCIe controller base address 0x9000 */ diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index f696f359608..c07ed667263 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -24,6 +24,13 @@ single-cpu-affinity; last-interrupt-source = <255>; }; + + esdhc: esdhc@2e000 { + compatible = "fsl,esdhc"; + reg = <0x2e000 0x1000>; + /* Filled in by U-Boot */ + clock-frequency = <0>; + }; }; /* PCIe controller base address 0x8000 */ diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi index 239439dd4dd..223052ac1ce 100644 --- a/arch/powerpc/dts/p2041.dtsi +++ b/arch/powerpc/dts/p2041.dtsi @@ -68,6 +68,12 @@ sata-number = <2>; sata-fpdma = <0>; }; + + esdhc: esdhc@114000 { + compatible = "fsl,esdhc"; + reg = <0x114000 0x1000>; + clock-frequency = <0>; + }; }; pcie@ffe200000 { diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi index 23bde81418f..e873db2a363 100644 --- a/arch/powerpc/dts/p3041.dtsi +++ b/arch/powerpc/dts/p3041.dtsi @@ -68,6 +68,12 @@ sata-number = <2>; sata-fpdma = <0>; }; + + esdhc: esdhc@114000 { + compatible = "fsl,esdhc"; + reg = <0x114000 0x1000>; + clock-frequency = <0>; + }; }; pcie@ffe200000 { diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi index ab766803a33..08ac26df67d 100644 --- a/arch/powerpc/dts/p4080.dtsi +++ b/arch/powerpc/dts/p4080.dtsi @@ -79,6 +79,12 @@ device_type = "open-pic"; clock-frequency = <0x0>; }; + + esdhc: esdhc@114000 { + compatible = "fsl,esdhc"; + reg = <0x114000 0x1000>; + clock-frequency = <0>; + }; }; pcie@ffe200000 { diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi index 7b8218acc3f..71019245f0b 100644 --- a/arch/powerpc/dts/p5040.dtsi +++ b/arch/powerpc/dts/p5040.dtsi @@ -67,6 +67,12 @@ sata-number = <2>; sata-fpdma = <0>; }; + + esdhc: esdhc@114000 { + compatible = "fsl,esdhc"; + reg = <0x114000 0x1000>; + clock-frequency = <0>; + }; }; pcie@ffe200000 { diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi index 7d3f7c53abc..0bc1d809a4b 100644 --- a/arch/powerpc/dts/t102x.dtsi +++ b/arch/powerpc/dts/t102x.dtsi @@ -57,6 +57,12 @@ sata-number = <2>; sata-fpdma = <0>; }; + + esdhc: esdhc@114000 { + compatible = "fsl,esdhc"; + reg = <0x114000 0x1000>; + clock-frequency = <0>; + }; }; pcie@ffe240000 { diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi index fe6cc3cf148..0828f73b93d 100644 --- a/arch/powerpc/dts/t104x.dtsi +++ b/arch/powerpc/dts/t104x.dtsi @@ -67,6 +67,12 @@ sata-number = <2>; sata-fpdma = <0>; }; + + esdhc: esdhc@114000 { + compatible = "fsl,esdhc"; + reg = <0x114000 0x1000>; + clock-frequency = <0>; + }; }; pcie@ffe240000 { diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi index 3bda2fa7809..5170083b5b0 100644 --- a/arch/powerpc/dts/t4240.dtsi +++ b/arch/powerpc/dts/t4240.dtsi @@ -107,6 +107,12 @@ sata-number = <2>; sata-fpdma = <0>; }; + + esdhc: esdhc@114000 { + compatible = "fsl,esdhc"; + reg = <0x114000 0x1000>; + clock-frequency = <0>; + }; }; pcie@ffe240000 { diff --git a/arch/powerpc/include/asm/arch-mpc83xx/clock.h b/arch/powerpc/include/asm/arch-mpc83xx/clock.h deleted file mode 100644 index d57e93c2df9..00000000000 --- a/arch/powerpc/include/asm/arch-mpc83xx/clock.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2018 - * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_POWERPC_CLOCK_H -#define __ASM_POWERPC_CLOCK_H - -/* Make fsl_esdhc driver happy */ -enum mxc_clock { - MXC_ESDHC_CLK, -}; - -DECLARE_GLOBAL_DATA_PTR; - -uint mxc_get_clock(int clk) -{ - return gd->arch.sdhc_clk; -} -#endif /* __ASM_POWERPC_CLOCK_H */ diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c index 357aba91225..a1c7a94a90e 100644 --- a/board/freescale/common/sdhc_boot.c +++ b/board/freescale/common/sdhc_boot.c @@ -28,7 +28,11 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) return 1; /* read out the first block, get the config data information */ +#ifdef CONFIG_BLK + n = blk_dread(mmc_get_blk_desc(mmc), 0, 1, tmp_buf); +#else n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf); +#endif if (!n) { free(tmp_buf); return 1; diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index 70992a5ce4e..621a3db6f6c 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -12,7 +12,6 @@ #include <asm/arch/ls102xa_devdis.h> #include <asm/arch/ls102xa_soc.h> #include <fsl_csu.h> -#include <fsl_esdhc.h> #include <fsl_immap.h> #include <netdev.h> #include <fsl_mdio.h> @@ -103,20 +102,6 @@ int dram_init(void) return 0; } -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {CONFIG_SYS_FSL_ESDHC_ADDR}, -}; - -int board_mmc_init(bd_t *bis) -{ - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} - -#endif - #ifdef CONFIG_TSEC_ENET int board_eth_init(bd_t *bis) { diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 2ca2bd99093..4034b7dec69 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -14,7 +14,6 @@ #include <hwconfig.h> #include <mmc.h> #include <fsl_csu.h> -#include <fsl_esdhc.h> #include <fsl_ifc.h> #include <fsl_sec.h> #include <spl.h> @@ -161,19 +160,6 @@ int dram_init(void) return fsl_initdram(); } -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {CONFIG_SYS_FSL_ESDHC_ADDR}, -}; - -int board_mmc_init(bd_t *bis) -{ - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} -#endif - int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index fcf2ec97889..1a412eed1c7 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -14,7 +14,6 @@ #include <hwconfig.h> #include <mmc.h> #include <fsl_csu.h> -#include <fsl_esdhc.h> #include <fsl_ifc.h> #include <fsl_immap.h> #include <netdev.h> @@ -233,19 +232,6 @@ int dram_init(void) return 0; } -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {CONFIG_SYS_FSL_ESDHC_ADDR}, -}; - -int board_mmc_init(bd_t *bis) -{ - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} -#endif - int board_eth_init(bd_t *bis) { return pci_eth_init(bis); diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig deleted file mode 100644 index df7c0296c7d..00000000000 --- a/board/micronas/vct/Kconfig +++ /dev/null @@ -1,52 +0,0 @@ -if TARGET_VCT - -config SYS_BOARD - default "vct" - -config SYS_VENDOR - default "micronas" - -config SYS_CONFIG_NAME - default "vct" - -config SYS_TEXT_BASE - default 0x87000000 - -config SYS_DCACHE_SIZE - default 16384 - -config SYS_DCACHE_LINE_SIZE - default 32 - -config SYS_ICACHE_SIZE - default 16384 - -config SYS_ICACHE_LINE_SIZE - default 32 - -menu "vct board options" - -choice - prompt "Board variant" - optional - -config VCT_PLATINUM - bool "Enable VCT_PLATINUM" - -config VCT_PLATINUMAVC - bool "Enable VCT_PLATINUMAVC" - -config VCT_PREMIUM - bool "Enable VCT_PLATINUMAVC" - -endchoice - -config VCT_ONENAND - bool "Enable VCT_ONENAND" - -config VCT_SMALL_IMAGE - bool "Enable VCT_SMALL_IMAGE" - -endmenu - -endif diff --git a/board/micronas/vct/MAINTAINERS b/board/micronas/vct/MAINTAINERS deleted file mode 100644 index cbaa585134a..00000000000 --- a/board/micronas/vct/MAINTAINERS +++ /dev/null @@ -1,17 +0,0 @@ -VCT BOARD -#M: - -S: Maintained -F: board/micronas/vct/ -F: include/configs/vct.h -F: configs/vct_platinum_defconfig -F: configs/vct_platinum_onenand_defconfig -F: configs/vct_platinum_onenand_small_defconfig -F: configs/vct_platinum_small_defconfig -F: configs/vct_platinumavc_defconfig -F: configs/vct_platinumavc_onenand_defconfig -F: configs/vct_platinumavc_onenand_small_defconfig -F: configs/vct_platinumavc_small_defconfig -F: configs/vct_premium_defconfig -F: configs/vct_premium_onenand_defconfig -F: configs/vct_premium_onenand_small_defconfig -F: configs/vct_premium_small_defconfig diff --git a/board/micronas/vct/Makefile b/board/micronas/vct/Makefile deleted file mode 100644 index d82c28d2244..00000000000 --- a/board/micronas/vct/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - -obj-y := vct.o -obj-y += ebi.o -obj-$(CONFIG_VCT_NOR) += ebi_nor_flash.o -obj-$(CONFIG_VCT_ONENAND) += ebi_onenand.o -obj-$(CONFIG_DRIVER_SMC911X) += ebi_smc911x.o smc_eeprom.o -obj-y += gpio.o -obj-y += top.o -obj-$(CONFIG_USB_EHCI_VCT) += dcgu.o ehci.o scc.o diff --git a/board/micronas/vct/bcu.h b/board/micronas/vct/bcu.h deleted file mode 100644 index f52833ab920..00000000000 --- a/board/micronas/vct/bcu.h +++ /dev/null @@ -1,156 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Copyright (C) 2006 Micronas GmbH - */ - -#ifndef _BCU_H -#define _BCU_H - -enum bcu_tags { - BCU_VBV1 = 0, - BCU_VBV2 = 1, - BCU_BSS1 = 2, - BCU_BSS2 = 3, - BCU_TSD_TXT = 4, - BCU_TSD_SUBTITLES = 5, - BCU_TSD_PES_0 = 6, - BCU_TSD_PES_1 = 7, - BCU_TSD_PES_2 = 8, - BCU_TSD_PES_3 = 9, - BCU_TSIO_RECORD_0 = 10, - BCU_TSIO_RECORD_1 = 11, - BCU_TSIO_PLAYBACK_0 = 12, - BCU_TSIO_PLAYBACK_1 = 13, - BCU_SECURE_BUFFER = 14, - BCU_PCM1 = 15, - BCU_PCM2 = 16, - BCU_BSS_COPY = 17, - BCU_BSS_EXT1 = 18, - BCU_BSS_EXT2 = 19, - BCU_PCM_JINGLE = 20, - BCU_EBI_CPU_BUFFER = 21, - BCU_PCM_DELAY = 22, - BCU_FH_BUFFER_0 = 23, - BCU_FH_BUFFER_1 = 24, - BCU_TSD_SECTION_0 = 25, - BCU_TSD_SECTION_1 = 26, - BCU_TSD_SECTION_2 = 27, - BCU_TSD_SECTION_3 = 28, - BCU_TSD_SECTION_4 = 29, - BCU_TSD_SECTION_5 = 30, - BCU_TSD_SECTION_6 = 31, - BCU_TSD_SECTION_7 = 32, - BCU_TSD_SECTION_8 = 33, - BCU_TSD_SECTION_9 = 34, - BCU_TSD_SECTION_10 = 35, - BCU_TSD_SECTION_11 = 36, - BCU_TSD_SECTION_12 = 37, - BCU_TSD_SECTION_13 = 38, - BCU_TSD_SECTION_14 = 39, - BCU_TSD_SECTION_15 = 40, - BCU_TSD_SECTION_16 = 41, - BCU_TSD_SECTION_17 = 42, - BCU_TSD_SECTION_18 = 43, - BCU_TSD_SECTION_19 = 44, - BCU_TSD_SECTION_20 = 45, - BCU_TSD_SECTION_21 = 46, - BCU_TSD_SECTION_22 = 47, - BCU_TSD_SECTION_23 = 48, - BCU_TSD_SECTION_24 = 49, - BCU_TSD_SECTION_25 = 50, - BCU_TSD_SECTION_26 = 51, - BCU_TSD_SECTION_27 = 52, - BCU_TSD_SECTION_28 = 53, - BCU_TSD_SECTION_29 = 54, - BCU_TSD_SECTION_30 = 55, - BCU_TSD_SECTION_31 = 56, - BCU_TSD_SECTION_32 = 57, - BCU_TSD_SECTION_33 = 58, - BCU_TSD_SECTION_34 = 59, - BCU_TSD_SECTION_35 = 60, - BCU_TSD_SECTION_36 = 61, - BCU_TSD_SECTION_37 = 62, - BCU_TSD_SECTION_38 = 63, - BCU_TSD_SECTION_39 = 64, - BCU_TSD_SECTION_40 = 65, - BCU_TSD_SECTION_41 = 66, - BCU_TSD_SECTION_42 = 67, - BCU_TSD_SECTION_43 = 68, - BCU_TSD_SECTION_44 = 69, - BCU_TSD_SECTION_45 = 70, - BCU_TSD_SECTION_46 = 71, - BCU_TSD_SECTION_47 = 72, - BCU_TSD_SECTION_48 = 73, - BCU_TSD_SECTION_49 = 74, - BCU_TSD_SECTION_50 = 75, - BCU_TSD_SECTION_51 = 76, - BCU_TSD_SECTION_52 = 77, - BCU_TSD_SECTION_53 = 78, - BCU_TSIO_RECORD_2 = 79, - BCU_TSIO_RECORD_3 = 80, - BCU_TSIO_RECORD_4 = 81, - BCU_TSIO_RECORD_5 = 82, - BCU_TSIO_RECORD_6 = 83, - BCU_TSIO_RECORD_7 = 84, - BCU_TSIO_RECORD_8 = 85, - BCU_TSIO_RECORD_9 = 86, - BCU_PCM_DELAY_LINEAR = 87, - BCU_VD_MASTER_USER_DATA = 88, - BCU_VD_SLAVE_USER_DATA = 89, - BCU_VD_MASTER_REF0 = 90, - BCU_VD_MASTER_REF1 = 91, - BCU_VD_SLAVE_REF0 = 92, - BCU_VD_SLAVE_REF1 = 93, - BCU_VD_MASTER_DISP0_Y = 94, - BCU_VD_MASTER_DISP1_Y = 95, - BCU_VD_MASTER_DISP2_Y = 96, - BCU_VD_MASTER_DISP0_C = 97, - BCU_VD_MASTER_DISP1_C = 98, - BCU_VD_MASTER_DISP2_C = 99, - BCU_VD_SLAVE_DISP0_Y = 100, - BCU_VD_SLAVE_DISP1_Y = 101, - BCU_VD_SLAVE_DISP2_Y = 102, - BCU_VD_SLAVE_DISP0_C = 103, - BCU_VD_SLAVE_DISP1_C = 104, - BCU_VD_SLAVE_DISP2_C = 105, - BCU_CLUT_BUFFER_0 = 106, - BCU_CLUT_BUFFER_1 = 107, - BCU_OSD_FRAME_BUFFER_0 = 108, - BCU_OSD_FRAME_BUFFER_1 = 109, - BCU_GRAPHIC_FRAME_BUFFER0 = 110, - BCU_GRAPHIC_FRAME_BUFFER1 = 111, - BCU_DVP_VBI_REINSERTION = 112, - BCU_DVP_OSD_FRAME_BUFFER0 = 113, - BCU_DVP_OSD_FRAME_BUFFER1 = 114, - BCU_GAI_BUFFER = 115, - BCU_GA_SRC_BUFFER_0 = 116, - BCU_GA_SRC_BUFFER_1 = 117, - BCU_USB_BUFFER_0 = 118, - BCU_USB_BUFFER_1 = 119, - BCU_FE_3DCOMB_0 = 120, - BCU_FE_3DCOMB_1 = 121, - BCU_FE_3DCOMB_2 = 122, - BCU_FE_3DCOMB_3 = 123, - BCU_TNR_BUFFER_0 = 124, - BCU_TNR_BUFFER_1 = 125, - BCU_TNR_BUFFER_2 = 126, - BCU_MVAL_BUFFER = 127, - BCU_RC_BUFFER_0 = 128, - BCU_RC_BUFFER_1 = 129, - BCU_RC_BUFFER_2 = 130, - BCU_RC_BUFFER_3 = 131, - BCU_PIP_BUFFER_0 = 132, - BCU_PIP_BUFFER_1 = 133, - BCU_PIP_BUFFER_2 = 134, - BCU_PIP_BUFFER_3 = 135, - BCU_EWARP_BUFFER = 136, - BCU_OSD_BUFFER_0 = 137, - BCU_OSD_BUFFER_1 = 138, - BCU_GLOBAL_BUFFER_0 = 139, - BCU_GLOBAL_BUFFER_1 = 140, - BCU_MAX = 141 -}; - -#endif /* _BCU_H */ diff --git a/board/micronas/vct/dcgu.c b/board/micronas/vct/dcgu.c deleted file mode 100644 index e72d57f0e08..00000000000 --- a/board/micronas/vct/dcgu.c +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Original Author Guenter Gebhardt - * Copyright (C) 2006 Micronas GmbH - */ - -#include <common.h> -#include <linux/errno.h> - -#include "vct.h" - -int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup) -{ - u32 enable; - union dcgu_clk_en1 en1; - union dcgu_clk_en2 en2; - - switch (setup) { - case DCGU_SWITCH_ON: - enable = 1; - break; - case DCGU_SWITCH_OFF: - enable = 0; - break; - default: - printf("%s:%i:Invalid clock switch: %i\n", __FILE__, __LINE__, - setup); - return -EINVAL; - } - - if (module == DCGU_HW_MODULE_CPU) - en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE)); - else - en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); - - switch (module) { - case DCGU_HW_MODULE_MSMC: - en1.bits.en_clkmsmc = enable; - break; - case DCGU_HW_MODULE_SSI_S: - en1.bits.en_clkssi_s = enable; - break; - case DCGU_HW_MODULE_SSI_M: - en1.bits.en_clkssi_m = enable; - break; - case DCGU_HW_MODULE_SMC: - en1.bits.en_clksmc = enable; - break; - case DCGU_HW_MODULE_EBI: - en1.bits.en_clkebi = enable; - break; - case DCGU_HW_MODULE_USB_PLL: - en1.bits.en_usbpll = enable; - break; - case DCGU_HW_MODULE_USB_60: - en1.bits.en_clkusb60 = enable; - break; - case DCGU_HW_MODULE_USB_24: - en1.bits.en_clkusb24 = enable; - break; - case DCGU_HW_MODULE_UART_2: - en1.bits.en_clkuart2 = enable; - break; - case DCGU_HW_MODULE_UART_1: - en1.bits.en_clkuart1 = enable; - break; - case DCGU_HW_MODULE_PERI: - en1.bits.en_clkperi20 = enable; - break; - case DCGU_HW_MODULE_CPU: - en2.bits.en_clkcpu = enable; - break; - case DCGU_HW_MODULE_I2S: - en1.bits.en_clk_i2s_dly = enable; - break; - case DCGU_HW_MODULE_ABP_SCC: - en1.bits.en_clk_scc_abp = enable; - break; - case DCGU_HW_MODULE_SPDIF: - en1.bits.en_clk_dtv_spdo = enable; - break; - case DCGU_HW_MODULE_AD: - en1.bits.en_clkad = enable; - break; - case DCGU_HW_MODULE_MVD: - en1.bits.en_clkmvd = enable; - break; - case DCGU_HW_MODULE_TSD: - en1.bits.en_clktsd = enable; - break; - case DCGU_HW_MODULE_GA: - en1.bits.en_clkga = enable; - break; - case DCGU_HW_MODULE_DVP: - en1.bits.en_clkdvp = enable; - break; - case DCGU_HW_MODULE_MR2: - en1.bits.en_clkmr2 = enable; - break; - case DCGU_HW_MODULE_MR1: - en1.bits.en_clkmr1 = enable; - break; - default: - printf("%s:%i:Invalid hardware module: %i\n", __FILE__, - __LINE__, module); - return -EINVAL; - } - - /* - * The reg_read() following the reg_write() below forces the write to - * be really done on the bus. - * Otherwise the clock may not be switched on when this API function - * returns, which may cause an bus error if a registers of the hardware - * module connected to the clock is accessed. - */ - if (module == DCGU_HW_MODULE_CPU) { - reg_write(DCGU_CLK_EN2(DCGU_BASE), en2.reg); - en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE)); - } else { - reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg); - en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); - } - - return 0; -} - -int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup) -{ - union dcgu_reset_unit1 val; - u32 enable; - - switch (setup) { - case DCGU_SWITCH_ON: - enable = 1; - break; - case DCGU_SWITCH_OFF: - enable = 0; - break; - default: - printf("%s:%i:Invalid reset switch: %i\n", __FILE__, __LINE__, - setup); - return -EINVAL; - } - - val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE)); - switch (module) { - case DCGU_HW_MODULE_MSMC: - val.bits.swreset_clkmsmc = enable; - break; - case DCGU_HW_MODULE_SSI_S: - val.bits.swreset_clkssi_s = enable; - break; - case DCGU_HW_MODULE_SSI_M: - val.bits.swreset_clkssi_m = enable; - break; - case DCGU_HW_MODULE_SMC: - val.bits.swreset_clksmc = enable; - break; - case DCGU_HW_MODULE_EBI: - val.bits.swreset_clkebi = enable; - break; - case DCGU_HW_MODULE_USB_60: - val.bits.swreset_clkusb60 = enable; - break; - case DCGU_HW_MODULE_USB_24: - val.bits.swreset_clkusb24 = enable; - break; - case DCGU_HW_MODULE_UART_2: - val.bits.swreset_clkuart2 = enable; - break; - case DCGU_HW_MODULE_UART_1: - val.bits.swreset_clkuart1 = enable; - break; - case DCGU_HW_MODULE_PWM: - val.bits.swreset_pwm = enable; - break; - case DCGU_HW_MODULE_GPT: - val.bits.swreset_gpt = enable; - break; - case DCGU_HW_MODULE_I2C2: - val.bits.swreset_i2c2 = enable; - break; - case DCGU_HW_MODULE_I2C1: - val.bits.swreset_i2c1 = enable; - break; - case DCGU_HW_MODULE_GPIO2: - val.bits.swreset_gpio2 = enable; - break; - case DCGU_HW_MODULE_GPIO1: - val.bits.swreset_gpio1 = enable; - break; - case DCGU_HW_MODULE_CPU: - val.bits.swreset_clkcpu = enable; - break; - case DCGU_HW_MODULE_I2S: - val.bits.swreset_clk_i2s_dly = enable; - break; - case DCGU_HW_MODULE_ABP_SCC: - val.bits.swreset_clk_scc_abp = enable; - break; - case DCGU_HW_MODULE_SPDIF: - val.bits.swreset_clk_dtv_spdo = enable; - break; - case DCGU_HW_MODULE_AD: - val.bits.swreset_clkad = enable; - break; - case DCGU_HW_MODULE_MVD: - val.bits.swreset_clkmvd = enable; - break; - case DCGU_HW_MODULE_TSD: - val.bits.swreset_clktsd = enable; - break; - case DCGU_HW_MODULE_TSIO: - val.bits.swreset_clktsio = enable; - break; - case DCGU_HW_MODULE_GA: - val.bits.swreset_clkga = enable; - break; - case DCGU_HW_MODULE_MPC: - val.bits.swreset_clkmpc = enable; - break; - case DCGU_HW_MODULE_CVE: - val.bits.swreset_clkcve = enable; - break; - case DCGU_HW_MODULE_DVP: - val.bits.swreset_clkdvp = enable; - break; - case DCGU_HW_MODULE_MR2: - val.bits.swreset_clkmr2 = enable; - break; - case DCGU_HW_MODULE_MR1: - val.bits.swreset_clkmr1 = enable; - break; - default: - printf("%s:%i:Invalid hardware module: %i\n", __FILE__, - __LINE__, module); - return -EINVAL; - } - reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg); - - return 0; -} diff --git a/board/micronas/vct/dcgu.h b/board/micronas/vct/dcgu.h deleted file mode 100644 index 0f2277f61a9..00000000000 --- a/board/micronas/vct/dcgu.h +++ /dev/null @@ -1,165 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Copyright (C) 2006 Micronas GmbH - */ - -#ifndef _DCGU_H -#define _DCGU_H - -enum dcgu_switch { - DCGU_SWITCH_OFF, /* Switch off */ - DCGU_SWITCH_ON /* Switch on */ -}; - -enum dcgu_hw_module { - DCGU_HW_MODULE_DCGU, /* Selects digital clock gen. unit */ - - DCGU_HW_MODULE_MIC32_SCI, /* Selects MIC32 SoC interface */ - DCGU_HW_MODULE_SCI, /* Selects SCI target agent port modules*/ - - DCGU_HW_MODULE_MR1, /* Selects first MPEG reader module */ - DCGU_HW_MODULE_MR2, /* Selects second MPEG reader module */ - DCGU_HW_MODULE_MVD, /* Selects MPEG video decoder module */ - DCGU_HW_MODULE_DVP, /* Selects dig video processing module */ - DCGU_HW_MODULE_CVE, /* Selects color video encoder module */ - DCGU_HW_MODULE_VID_ENC, /* Selects video encoder module */ - - DCGU_HW_MODULE_SSI_S, /* Selects slave sync serial interface */ - DCGU_HW_MODULE_SSI_M, /* Selects master sync serial interface */ - - DCGU_HW_MODULE_GA, /* Selects graphics accelerator module */ - DCGU_HW_MODULE_DGPU, /* Selects digital graphics processing */ - - DCGU_HW_MODULE_UART_1, /* Selects first UART module */ - DCGU_HW_MODULE_UART_2, /* Selects second UART module */ - - DCGU_HW_MODULE_AD, /* Selects audio decoder module */ - DCGU_HW_MODULE_ABP_DTV, /* Selects audio baseband processing */ - DCGU_HW_MODULE_ABP_SCC, /* Selects audio base band processor SCC*/ - DCGU_HW_MODULE_SPDIF, /* Selects sony philips digital interf. */ - - DCGU_HW_MODULE_TSIO, /* Selects trasnport stream input/output*/ - DCGU_HW_MODULE_TSD, /* Selects trasnport stream decoder */ - DCGU_HW_MODULE_TSD_KEY, /* Selects trasnport stream decoder key */ - - DCGU_HW_MODULE_USBH, /* Selects USB hub module */ - DCGU_HW_MODULE_USB_PLL, /* Selects USB phase locked loop module */ - DCGU_HW_MODULE_USB_60, /* Selects USB 60 module */ - DCGU_HW_MODULE_USB_24, /* Selects USB 24 module */ - - DCGU_HW_MODULE_PERI, /* Selects all mod connected to clkperi20*/ - DCGU_HW_MODULE_WDT, /* Selects wtg timer mod con to clkperi20*/ - DCGU_HW_MODULE_I2C1, /* Selects first I2C mod con to clkperi20*/ - DCGU_HW_MODULE_I2C2, /* Selects 2nd I2C mod con to clkperi20 */ - DCGU_HW_MODULE_GPIO1, /* Selects gpio module 1 */ - DCGU_HW_MODULE_GPIO2, /* Selects gpio module 2 */ - - DCGU_HW_MODULE_GPT, /* Selects gpt mod connected to clkperi20*/ - DCGU_HW_MODULE_PWM, /* Selects pwm mod connected to clkperi20*/ - - DCGU_HW_MODULE_MPC, /* Selects multi purpose cipher module */ - DCGU_HW_MODULE_MPC_KEY, /* Selects multi purpose cipher key */ - - DCGU_HW_MODULE_COM, /* Selects COM unit module */ - DCGU_HW_MODULE_VCTY_CORE, /* Selects VCT-Y core module */ - DCGU_HW_MODULE_FWSRAM, /* Selects firmware SRAM module */ - - DCGU_HW_MODULE_EBI, /* Selects external bus interface module*/ - DCGU_HW_MODULE_I2S, /* Selects integrated interchip sound */ - DCGU_HW_MODULE_MSMC, /* Selects memory stick and mmc module */ - DCGU_HW_MODULE_SMC, /* Selects smartcard interface module */ - - DCGU_HW_MODULE_IRQC, /* Selects interrupt C module */ - DCGU_HW_MODULE_TOP, /* Selects top level pinmux module */ - DCGU_HW_MODULE_SRAM, /* Selects SRAM module */ - DCGU_HW_MODULE_EIC, /* Selects External Interrupt controller*/ - DCGU_HW_MODULE_CPU, /* Selects CPU subsystem module */ - DCGU_HW_MODULE_SCC, /* Selects SCC module */ - DCGU_HW_MODULE_MM, /* Selects Memory Manager module */ - DCGU_HW_MODULE_BCU, /* Selects Buffer Configuration Unit */ - DCGU_HW_MODULE_FH, /* Selects FIFO Handler module */ - DCGU_HW_MODULE_IMU, /* Selects Interrupt Management Unit */ - DCGU_HW_MODULE_MDU, /* Selects MCI Debug Unit module */ - DCGU_HW_MODULE_SI2OCP /* Selects Standard Interface to OCP bridge*/ -}; - -union dcgu_clk_en1 { - u32 reg; - struct { - u32 res1:8; /* reserved */ - u32 en_clkmsmc:1; /* Enable bit for clkmsmc (#) */ - u32 en_clkssi_s:1; /* Enable bit for clkssi_s (#) */ - u32 en_clkssi_m:1; /* Enable bit for clkssi_m (#) */ - u32 en_clksmc:1; /* Enable bit for clksmc (#) */ - u32 en_clkebi:1; /* Enable bit for clkebi (#) */ - u32 en_usbpll:1; /* Enable bit for the USB PLL */ - u32 en_clkusb60:1; /* Enable bit for clkusb60 (#) */ - u32 en_clkusb24:1; /* Enable bit for clkusb24 (#) */ - u32 en_clkuart2:1; /* Enable bit for clkuart2 (#) */ - u32 en_clkuart1:1; /* Enable bit for clkuart1 (#) */ - u32 en_clkperi20:1; /* Enable bit for clkperi20 (#) */ - u32 res2:3; /* reserved */ - u32 en_clk_i2s_dly:1; /* Enable bit for clk_scc_abp */ - u32 en_clk_scc_abp:1; /* Enable bit for clk_scc_abp */ - u32 en_clk_dtv_spdo:1; /* Enable bit for clk_dtv_spdo */ - u32 en_clkad:1; /* Enable bit for clkad (#) */ - u32 en_clkmvd:1; /* Enable bit for clkmvd (#) */ - u32 en_clktsd:1; /* Enable bit for clktsd (#) */ - u32 en_clkga:1; /* Enable bit for clkga (#) */ - u32 en_clkdvp:1; /* Enable bit for clkdvp (#) */ - u32 en_clkmr2:1; /* Enable bit for clkmr2 (#) */ - u32 en_clkmr1:1; /* Enable bit for clkmr1 (#) */ - } bits; -}; - -union dcgu_clk_en2 { - u32 reg; - struct { - u32 res1:31; /* reserved */ - u32 en_clkcpu:1; /* Enable bit for clkcpu */ - } bits; -}; - -union dcgu_reset_unit1 { - u32 reg; - struct { - u32 res1:1; - u32 swreset_clkmsmc:1; - u32 swreset_clkssi_s:1; - u32 swreset_clkssi_m:1; - u32 swreset_clksmc:1; - u32 swreset_clkebi:1; - u32 swreset_clkusb60:1; - u32 swreset_clkusb24:1; - u32 swreset_clkuart2:1; - u32 swreset_clkuart1:1; - u32 swreset_pwm:1; - u32 swreset_gpt:1; - u32 swreset_i2c2:1; - u32 swreset_i2c1:1; - u32 swreset_gpio2:1; - u32 swreset_gpio1:1; - u32 swreset_clkcpu:1; - u32 res2:2; - u32 swreset_clk_i2s_dly:1; - u32 swreset_clk_scc_abp:1; - u32 swreset_clk_dtv_spdo:1; - u32 swreset_clkad:1; - u32 swreset_clkmvd:1; - u32 swreset_clktsd:1; - u32 swreset_clktsio:1; - u32 swreset_clkga:1; - u32 swreset_clkmpc:1; - u32 swreset_clkcve:1; - u32 swreset_clkdvp:1; - u32 swreset_clkmr2:1; - u32 swreset_clkmr1:1; - } bits; -}; - -int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup); -int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup); - -#endif /* _DCGU_H */ diff --git a/board/micronas/vct/ebi.c b/board/micronas/vct/ebi.c deleted file mode 100644 index 8a730866955..00000000000 --- a/board/micronas/vct/ebi.c +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Copyright (C) 2006 Micronas GmbH - */ - -#include <common.h> -#include <asm/io.h> -#include "vct.h" - -int ebi_initialize(void) -{ -#if defined(CONFIG_VCT_NOR) - if (ebi_init_nor_flash()) - return -1; -#endif - -#if defined(CONFIG_VCT_ONENAND) - if (ebi_init_onenand()) - return -1; -#endif - -#if defined(CONFIG_DRIVER_SMC911X) - if (ebi_init_smc911x()) - return -1; -#endif - - reg_write(EBI_CTRL_SIG_ACTLV(EBI_BASE), 0x00004100); - - ebi_wait(); - - return 0; -} diff --git a/board/micronas/vct/ebi.h b/board/micronas/vct/ebi.h deleted file mode 100644 index ea5b5cf5ad9..00000000000 --- a/board/micronas/vct/ebi.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - */ - -#ifndef __EBI__ -#define __EBI__ - -#include <common.h> -#include <asm/io.h> -#include "vct.h" - -#define EXT_DEVICE_CHANNEL_3 (0x30000000) -#define EXT_DEVICE_CHANNEL_2 (0x20000000) -#define EXT_DEVICE_CHANNEL_1 (0x10000000) -#define EXT_CPU_ACCESS_ACTIVE (0x00000001) -#define EXT_DMA_ACCESS_ACTIVE (1 << 14) -#define EXT_CPU_IORDY_SL (0x00000001) - -#define EBI_CPU_WRITE (1 << 31) -#define EBI_CPU_ID_SHIFT (28) -#define EBI_CPU_ADDR_MASK ~(~0UL << EBI_CPU_ID_SHIFT) - -/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */ -#define ADDR_LATCH_ENABLE 0 -#define ADDR_ACTIVATION 4 -#define CHIP_SELECT_START 8 -#define OUTPUT_ENABLE_START 12 -#define WAIT_TIME 28 -#define READ_DURATION 20 - -/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */ -#define OUTPUT_ENABLE_END 0 -#define CHIP_SELECT_END 4 -#define ADDR_DEACTIVATION 8 -#define RECOVER_TIME 12 -#define ACK_TIME 20 - -/* various bits in configuration register EBI_DEV[01]_CONFIG1 */ -#define EBI_EXTERNAL_DATA_8 (1 << 8) -#define EBI_EXT_ADDR_SHIFT (1 << 22) -#define EBI_EXTERNAL_DATA_16 EBI_EXT_ADDR_SHIFT -#define EBI_CHIP_SELECT_1 0x2 -#define EBI_CHIP_SELECT_2 0x4 -#define EBI_BUSY_EN_RD (1 << 12) -#define DIR_ACCESS_WRITE (1 << 20) -#define DIR_ACCESS_MASK (1 << 20) - -/* various bits in configuration register EBI_DEV[01]_CONFIG2 */ -#define ADDRESS_INCREMENT_ON 0x0 -#define ADDRESS_INCREMENT_OFF 0x100 -#define QUEUE_LENGTH_1 0x40 -#define QUEUE_LENGTH_2 0x80 -#define QUEUE_LENGTH_3 0xC0 -#define QUEUE_LENGTH_4 0 -#define CPU_TRANSFER_SIZE_32 0 -#define CPU_TRANSFER_SIZE_16 0x10 -#define CPU_TRANSFER_SIZE_8 0x20 -#define READ_ENDIANNESS_ABCD 0 -#define READ_ENDIANNESS_DCBA 0x4 -#define READ_ENDIANNESS_BADC 0x8 -#define READ_ENDIANNESS_CDAB 0xC -#define WRITE_ENDIANNESS_ABCD 0 -#define WRITE_ENDIANNESS_DCBA 0x1 -#define WRITE_ENDIANNESS_BADC 0x2 -#define WRITE_ENDIANNESS_CDAB 0x3 - -/* various bits in configuration register EBI_CTRL_SIG_ACTLV */ -#define IORDY_ACTIVELEVEL_HIGH (1 << 14) -#define ALE_ACTIVELEVEL_HIGH (1 << 8) - -/* bits in register EBI_SIG_LEVEL */ -#define IORDY_LEVEL_MASK 1 - -static inline void ebi_wait(void) -{ - while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE) - ; /* wait */ -} - -#endif diff --git a/board/micronas/vct/ebi_nor_flash.c b/board/micronas/vct/ebi_nor_flash.c deleted file mode 100644 index 548443e35ae..00000000000 --- a/board/micronas/vct/ebi_nor_flash.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - */ - -#include <common.h> -#include <asm/io.h> -#include "vct.h" - -static u32 ebi_read(u32 addr) -{ - addr &= ~0xFC000000; - - reg_write(EBI_CPU_IO_ACCS(EBI_BASE), EXT_DEVICE_CHANNEL_2 | addr); - ebi_wait(); - - return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); -} - -static int ebi_write_u16(u32 addr, u32 data, int fetchIO) -{ - u32 val = (data << 16); - - addr &= ~0xFC000000; - - ebi_wait(); - - reg_write(EBI_IO_ACCS_DATA(EBI_BASE), val); - reg_write(EBI_CPU_IO_ACCS(EBI_BASE), - EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | addr); - ebi_wait(); - - if (fetchIO) { - u32 counter = 0; - while (!(reg_read(EBI_SIG_LEVEL(EBI_BASE)) & EXT_CPU_IORDY_SL)) { - if (counter++ > 0xFFFFFF) - return 1; - } - } - - return 0; -} - -static u16 ebi_read_u16(u32 addr) -{ - return ((ebi_read(addr) >> 16) & 0xFFFF); -} - -static u8 ebi_read_u8(u32 addr) -{ - u32 val = ebi_read(addr) >> 16; - - if (addr & 0x1) - return val & 0xff; - else - return (val >> 8) & 0xff; -} - -/* - * EBI initialization for NOR FLASH access - */ -int ebi_init_nor_flash(void) -{ - reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); - - reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x400002); - reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); - - reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x409113); - reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0xFF01000); - reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x04003113); - reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC12011); - reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000); - - return 0; -} - -/* - * Accessor functions replacing the "weak" functions in - * drivers/mtd/cfi_flash.c - */ -void flash_write8(u8 value, void *addr) -{ - ebi_write_u16((u32)addr, value, 0); -} - -void flash_write16(u16 value, void *addr) -{ - ebi_write_u16((u32)addr, value, 0); -} - -u8 flash_read8(void *addr) -{ - return ebi_read_u8((u32)addr); -} - -u16 flash_read16(void *addr) -{ - return ebi_read_u16((u32)addr); -} - -u32 flash_read32(void *addr) -{ - return ((u32)ebi_read_u16((u32)addr) << 16) | - ebi_read_u16((u32)addr + 2); -} - -void *board_flash_read_memcpy(void *dest, const void *src, size_t count) -{ - u16 *tmp = (u16 *)dest, *s = (u16 *)src; - int i; - - for (i = 0; i < count; i += 2) - *tmp++ = flash_read16(s++); - - return dest; -} diff --git a/board/micronas/vct/ebi_onenand.c b/board/micronas/vct/ebi_onenand.c deleted file mode 100644 index 862ce2682eb..00000000000 --- a/board/micronas/vct/ebi_onenand.c +++ /dev/null @@ -1,185 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - */ - -#include <common.h> -#include <asm/io.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/onenand.h> -#include "vct.h" - -#define BURST_SIZE_WORDS 4 - -static u16 ebi_nand_read_word(void __iomem *addr) -{ - reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_2 | (u32)addr)); - ebi_wait(); - - return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)) >> 16; -} - -static void ebi_nand_write_word(u16 data, void __iomem * addr) -{ - ebi_wait(); - reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16)); - reg_write(EBI_CPU_IO_ACCS(EBI_BASE), - EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | (u32)addr); - ebi_wait(); -} - -/* - * EBI initialization for OneNAND FLASH access - */ -int ebi_init_onenand(void) -{ - reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); - - reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002); - reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); - - reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002); - reg_write(EBI_DEV3_CONFIG2(EBI_BASE), 0x0); /* byte/word ordering */ - - reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x00504000); - reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0x00001000); - reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x12002223); - reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC02220); - reg_write(EBI_DEV3_TIM1_RD1(EBI_BASE), 0x00504000); - reg_write(EBI_DEV3_TIM1_RD2(EBI_BASE), 0x00001000); - reg_write(EBI_DEV3_TIM1_WR1(EBI_BASE), 0x05001000); - reg_write(EBI_DEV3_TIM1_WR2(EBI_BASE), 0x00010200); - - reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000); - reg_write(EBI_DEV2_EXT_ACC(EBI_BASE), 0x0FFFFFFF); - - reg_write(EBI_DEV3_TIM_EXT(EBI_BASE), 0xFFF00000); - reg_write(EBI_DEV3_EXT_ACC(EBI_BASE), 0x0FFFFFFF); - - /* prepare DMA configuration for EBI */ - reg_write(EBI_DEV3_FIFO_CONFIG(EBI_BASE), 0x0101ff00); - - /* READ only no byte order change, TAG 1 used */ - reg_write(EBI_DEV3_DMA_CONFIG2(EBI_BASE), 0x00000004); - - reg_write(EBI_TAG1_SYS_ID(EBI_BASE), 0x0); /* SCC DMA channel 0 */ - reg_write(EBI_TAG2_SYS_ID(EBI_BASE), 0x1); - reg_write(EBI_TAG3_SYS_ID(EBI_BASE), 0x2); - reg_write(EBI_TAG4_SYS_ID(EBI_BASE), 0x3); - - return 0; -} - -static void *memcpy_16_from_onenand(void *dst, const void *src, unsigned int len) -{ - void *ret = dst; - u16 *d = dst; - u16 *s = (u16 *)src; - - len >>= 1; - while (len-- > 0) - *d++ = ebi_nand_read_word(s++); - - return ret; -} - -static void *memcpy_32_from_onenand(void *dst, const void *src, unsigned int len) -{ - void *ret = dst; - u32 *d = (u32 *)dst; - u32 s = (u32)src; - u32 bytes_per_block = BURST_SIZE_WORDS * sizeof(int); - u32 n_blocks = len / bytes_per_block; - u32 block = 0; - u32 burst_word; - - for (block = 0; block < n_blocks; block++) { - /* Trigger read channel 3 */ - reg_write(EBI_CPU_IO_ACCS(EBI_BASE), - (EXT_DEVICE_CHANNEL_3 | (s + (block * bytes_per_block)))); - /* Poll status to see whether read has finished */ - ebi_wait(); - - /* Squirrel the data away in a safe place */ - for (burst_word = 0; burst_word < BURST_SIZE_WORDS; burst_word++) - *d++ = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); - } - - return ret; -} - -static void *memcpy_16_to_onenand(void *dst, const void *src, unsigned int len) -{ - void *ret = dst; - u16 *d = dst; - u16 *s = (u16 *)src; - - len >>= 1; - while (len-- > 0) - ebi_nand_write_word(*s++, d++); - - return ret; -} - -static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) -{ - struct onenand_chip *this = mtd->priv; - - if (ONENAND_CURRENT_BUFFERRAM(this)) { - if (area == ONENAND_DATARAM) - return mtd->writesize; - if (area == ONENAND_SPARERAM) - return mtd->oobsize; - } - - return 0; -} - -static int ebi_read_bufferram(struct mtd_info *mtd, loff_t addr, int area, - unsigned char *buffer, int offset, - size_t count) -{ - struct onenand_chip *this = mtd->priv; - void __iomem *bufferram; - - bufferram = this->base + area; - bufferram += onenand_bufferram_offset(mtd, area); - - if (count < 4) - memcpy_16_from_onenand(buffer, bufferram + offset, count); - else - memcpy_32_from_onenand(buffer, bufferram + offset, count); - - return 0; -} - -static int ebi_write_bufferram(struct mtd_info *mtd, loff_t addr, int area, - const unsigned char *buffer, int offset, - size_t count) -{ - struct onenand_chip *this = mtd->priv; - void __iomem *bufferram; - - bufferram = this->base + area; - bufferram += onenand_bufferram_offset(mtd, area); - - memcpy_16_to_onenand(bufferram + offset, buffer, count); - - return 0; -} - -int onenand_board_init(struct mtd_info *mtd) -{ - struct onenand_chip *chip = mtd->priv; - - /* - * Insert board specific OneNAND access functions - */ - chip->read_word = ebi_nand_read_word; - chip->write_word = ebi_nand_write_word; - - chip->read_bufferram = ebi_read_bufferram; - chip->write_bufferram = ebi_write_bufferram; - - return 0; -} diff --git a/board/micronas/vct/ebi_smc911x.c b/board/micronas/vct/ebi_smc911x.c deleted file mode 100644 index 9e59f0a2de2..00000000000 --- a/board/micronas/vct/ebi_smc911x.c +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - */ - -#include <common.h> -#include <netdev.h> -#include <asm/io.h> -#include "vct.h" - -/* - * EBI initialization for SMC911x access - */ -int ebi_init_smc911x(void) -{ - reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x00003020); - reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); - - reg_write(EBI_DEV1_TIM1_RD1(EBI_BASE), 0x00501100); - reg_write(EBI_DEV1_TIM1_RD2(EBI_BASE), 0x0FF02111); - - reg_write(EBI_DEV1_TIM_EXT(EBI_BASE), 0xFFF00000); - reg_write(EBI_DEV1_EXT_ACC(EBI_BASE), 0x0FFFFFFF); - - reg_write(EBI_DEV1_TIM1_WR1(EBI_BASE), 0x05001100); - reg_write(EBI_DEV1_TIM1_WR2(EBI_BASE), 0x3FC21110); - - return 0; -} - -/* - * Accessor functions replacing the "weak" functions in - * drivers/net/smc911x.c - */ -u32 smc911x_reg_read(struct eth_device *dev, u32 addr) -{ - volatile u32 data; - - addr += dev->iobase; - reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); - ebi_wait(); - reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr)); - ebi_wait(); - data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); - - return (data); -} - -void smc911x_reg_write(struct eth_device *dev, u32 addr, u32 data) -{ - addr += dev->iobase; - reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); - ebi_wait(); - reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data); - reg_write(EBI_CPU_IO_ACCS(EBI_BASE), - EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr); - ebi_wait(); -} - -void pkt_data_push(struct eth_device *dev, u32 addr, u32 data) -{ - addr += dev->iobase; - reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A); - ebi_wait(); - reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data); - reg_write(EBI_CPU_IO_ACCS(EBI_BASE), - EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr); - ebi_wait(); - - return; -} - -u32 pkt_data_pull(struct eth_device *dev, u32 addr) -{ - volatile u32 data; - - addr += dev->iobase; - reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A); - ebi_wait(); - reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr)); - ebi_wait(); - data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); - - return data; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_DRIVER_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/micronas/vct/ehci.c b/board/micronas/vct/ehci.c deleted file mode 100644 index 2d6966c2ae3..00000000000 --- a/board/micronas/vct/ehci.c +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Original Author Guenter Gebhardt - * Copyright (C) 2006 Micronas GmbH - */ - -#include <common.h> - -#include "vct.h" - -int vct_ehci_hcd_init(u32 *hccr, u32 *hcor) -{ - int retval; - u32 val; - u32 addr; - - dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON); - dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON); - dcgu_set_clk_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON); - dcgu_set_clk_switch(DCGU_HW_MODULE_USB_PLL, DCGU_SWITCH_ON); - dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_OFF); - - /* Wait until (DCGU_USBPHY_STAT == 7) */ - addr = DCGU_USBPHY_STAT(DCGU_BASE); - val = reg_read(addr); - while (val != 7) - val = reg_read(addr); - - dcgu_set_clk_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON); - dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_OFF); - - retval = scc_reset(SCC_USB_RW, 0); - if (retval) { - printf("scc_reset(SCC_USB_RW, 0) returned: 0x%x\n", retval); - return retval; - } else { - retval = scc_reset(SCC_CPU1_SPDMA_RW, 0); - if (retval) { - printf("scc_reset(SCC_CPU1_SPDMA_RW, 0) returned: 0x%x\n", - retval); - return retval; - } - } - - if (!retval) { - /* - * For the AGU bypass, where the SCC client provides full - * physical address - */ - scc_set_usb_address_generation_mode(1); - scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_1, DMA_LINEAR, - USE_NO_FH, DMA_READ, 0); - scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_1, DMA_LINEAR, - USE_NO_FH, DMA_WRITE, 0); - scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_0, DMA_LINEAR, - USE_NO_FH, DMA_WRITE, 0); - scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_0, DMA_LINEAR, - USE_NO_FH, DMA_READ, 0); - - /* Enable memory interface */ - scc_enable(SCC_USB_RW, 1); - - /* Start (start_cmd=0) DMAs */ - scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_READ); - scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_WRITE); - } else { - printf("Cannot configure USB memory channel.\n"); - printf("USB can not access RAM. SCC configuration failed.\n"); - return retval; - } - - /* Wait a short while */ - udelay(300000); - - reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c); - - /* Set EHCI structures and DATA in RAM */ - reg_write(USBH_USBHMISC(USBH_BASE), 0x00840003); - /* Set USBMODE to bigendian and set host mode */ - reg_write(USBH_USBMODE(USBH_BASE), 0x00000007); - - /* - * USBH_BURSTSIZE MUST EQUAL 0x00001c1c in order for - * 512 byte USB transfers on the bulk pipe to work properly. - * Set USBH_BURSTSIZE to 0x00001c1c - */ - reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c); - - /* Insert access register addresses */ - *hccr = REG_GLOBAL_START_ADDR + USBH_CAPLENGTH(USBH_BASE); - *hcor = REG_GLOBAL_START_ADDR + USBH_USBCMD(USBH_BASE); - - return 0; -} diff --git a/board/micronas/vct/gpio.c b/board/micronas/vct/gpio.c deleted file mode 100644 index 776bb2d91cc..00000000000 --- a/board/micronas/vct/gpio.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - */ - -#include <common.h> -#include <asm/io.h> -#include "vct.h" - -/* - * Find out to which of the 2 gpio modules the pin specified in the - * argument belongs: - * GPIO_MODULE yields 0 for pins 0 to 31, - * 1 for pins 32 to 63 - */ -#define GPIO_MODULE(pin) ((pin) >> 5) - -/* - * Bit position within a 32-bit peripheral register (where every - * bit is one bitslice) - */ -#define MASK(pin) (1 << ((pin) & 0x1F)) -#define BASE_ADDR(mod) module_base[mod] - -/* - * Lookup table for transforming gpio module number 0 to 2 to - * address offsets - */ -static u32 module_base[] = { - GPIO1_BASE, - GPIO2_BASE -}; - -static void clrsetbits(u32 addr, u32 and_mask, u32 or_mask) -{ - reg_write(addr, (reg_read(addr) & ~and_mask) | or_mask); -} - -int vct_gpio_dir(int pin, int dir) -{ - u32 gpio_base; - - gpio_base = BASE_ADDR(GPIO_MODULE(pin)); - - if (dir == 0) - clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0); - else - clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin)); - - return 0; -} - -void vct_gpio_set(int pin, int val) -{ - u32 gpio_base; - - gpio_base = BASE_ADDR(GPIO_MODULE(pin)); - - if (val == 0) - clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0); - else - clrsetbits(GPIO_SWPORTA_DR(gpio_base), 0, MASK(pin)); -} - -int vct_gpio_get(int pin) -{ - u32 gpio_base; - u32 value; - - gpio_base = BASE_ADDR(GPIO_MODULE(pin)); - value = reg_read(GPIO_EXT_PORTA(gpio_base)); - - return ((value & MASK(pin)) ? 1 : 0); -} diff --git a/board/micronas/vct/scc.c b/board/micronas/vct/scc.c deleted file mode 100644 index 6621231b07b..00000000000 --- a/board/micronas/vct/scc.c +++ /dev/null @@ -1,657 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Copyright (C) 2006 Micronas GmbH - */ - -#include <common.h> -#include <linux/errno.h> - -#include "vct.h" - -/* - * List of statically defined buffers per SCC. - * The first entry in the table is the number of fixed buffers - * followed by the list of buffer IDs - */ -static u32 buffer_list_0[] = { 6, 120, 121, 122, 123, 139, 140 }; -static u32 buffer_list_1[] = { 6, 120, 121, 122, 123, 139, 140 }; -static u32 buffer_list_2[] = { 5, 124, 125, 126, 139, 140 }; -static u32 buffer_list_3[] = { 5, 124, 125, 126, 139, 140 }; -static u32 buffer_list_4[] = { 5, 124, 125, 126, 139, 140 }; -static u32 buffer_list_5[] = { 3, 127, 139, 140 }; -static u32 buffer_list_6[] = { 3, 127, 139, 140 }; -static u32 buffer_list_7[] = { 6, 128, 129, 130, 131, 139, 140 }; -static u32 buffer_list_8[] = { 6, 128, 129, 130, 131, 139, 140 }; -static u32 buffer_list_9[] = { 5, 124, 125, 126, 139, 140 }; -static u32 buffer_list_10[] = { 5, 124, 125, 126, 139, 140 }; -static u32 buffer_list_11[] = { 5, 124, 125, 126, 139, 140 }; -static u32 buffer_list_12[] = { 6, 132, 133, 134, 135, 139, 140 }; -static u32 buffer_list_13[] = { 6, 132, 133, 134, 135, 139, 140 }; -static u32 buffer_list_14[] = { 4, 137, 138, 139, 140 }; -static u32 buffer_list_15[] = { 6, 136, 136, 137, 138, 139, 140 }; - -/** Issue#7674 (new) - DP/DVP buffer assignment */ -static u32 buffer_list_16[] = { 6, 106, 108, 109, 107, 139, 140 }; -static u32 buffer_list_17[] = { 6, 106, 110, 107, 111, 139, 140 }; -static u32 buffer_list_18[] = { 6, 106, 113, 107, 114, 139, 140 }; -static u32 buffer_list_19[] = { 3, 112, 139, 140 }; -static u32 buffer_list_20[] = { 35, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, - 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 79, 80, 81, 82, 83, 84, 85, 86, 139, 140 }; -static u32 buffer_list_21[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, - 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 139, 140 }; -static u32 buffer_list_22[] = { 81, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, - 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, - 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, - 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, - 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, - 73, 74, 75, 76, 77, 78, 139, 140 }; -static u32 buffer_list_23[] = { 29, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, - 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 88, 89, 139, 140 }; -static u32 buffer_list_24[] = { 6, 90, 91, 92, 93, 139, 140 }; -static u32 buffer_list_25[] = { 18, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, - 100, 101, 102, 103, 104, 105, 139, 140 }; -static u32 buffer_list_26[] = { 5, 94, 95, 96, 139, 140 }; -static u32 buffer_list_27[] = { 5, 97, 98, 99, 139, 140 }; -static u32 buffer_list_28[] = { 5, 100, 101, 102, 139, 140 }; -static u32 buffer_list_29[] = { 5, 103, 104, 105, 139, 140 }; -static u32 buffer_list_30[] = { 10, 108, 109, 110, 111, 113, 114, 116, 117, - 139, 140 }; -static u32 buffer_list_31[] = { 13, 106, 107, 108, 109, 110, 111, 113, 114, - 115, 116, 117, 139, 140 }; -static u32 buffer_list_32[] = { 13, 106, 107, 108, 109, 110, 111, 113, 114, - 115, 116, 117, 139, 140 }; -static u32 buffer_list_33[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, - 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 139, 140 }; -static u32 buffer_list_34[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, - 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 139, 140 }; -static u32 buffer_list_35[] = { 28, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, - 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 87, 139, 140 }; -static u32 buffer_list_36[] = { 28, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, - 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 87, 139, 140 }; -static u32 buffer_list_37[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, - 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 139, 140 }; -static u32 buffer_list_38[] = { 29, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, - 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 118, 119, 139, 140 }; -static u32 buffer_list_39[] = { 91, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, - 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, - 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, - 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, - 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, - 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, - 85, 86, 118, 119, 139, 140 }; -static u32 buffer_list_40[] = { 0 }; - -/* - * List of statically defined vcid.csize values. - * The first entry in the table is the number of possible csize values - * followed by the list of data path values in bits. - */ -static u32 csize_list_0[] = { 2, 0, 1 }; -static u32 csize_list_1[] = { 2, 0, 1 }; -static u32 csize_list_2[] = { 1, 1 }; -static u32 csize_list_3[] = { 1, 1 }; -static u32 csize_list_4[] = { 1, 1 }; -static u32 csize_list_5[] = { 1, 0 }; -static u32 csize_list_6[] = { 1, 0 }; -static u32 csize_list_7[] = { 1, 1 }; -static u32 csize_list_8[] = { 1, 1 }; -static u32 csize_list_9[] = { 1, 1 }; -static u32 csize_list_10[] = { 1, 1 }; -static u32 csize_list_11[] = { 1, 1 }; -static u32 csize_list_12[] = { 1, 1 }; -static u32 csize_list_13[] = { 1, 1 }; -static u32 csize_list_14[] = { 1, 2 }; -static u32 csize_list_15[] = { 1, 4 }; -static u32 csize_list_16[] = { 3, 0, 1, 2 }; -static u32 csize_list_17[] = { 3, 0, 1, 2 }; -static u32 csize_list_18[] = { 3, 0, 1, 2 }; -static u32 csize_list_19[] = { 1, 2 }; -static u32 csize_list_20[] = { 1, 0 }; -static u32 csize_list_21[] = { 1, 0 }; -static u32 csize_list_22[] = { 1, 2 }; -static u32 csize_list_23[] = { 1, 3 }; -static u32 csize_list_24[] = { 1, 3 }; -static u32 csize_list_25[] = { 1, 3 }; -static u32 csize_list_26[] = { 1, 0 }; -static u32 csize_list_27[] = { 1, 0 }; -static u32 csize_list_28[] = { 1, 0 }; -static u32 csize_list_29[] = { 1, 0 }; -static u32 csize_list_30[] = { 1, 2 }; -static u32 csize_list_31[] = { 1, 2 }; -static u32 csize_list_32[] = { 1, 2 }; -static u32 csize_list_33[] = { 1, 2 }; -static u32 csize_list_34[] = { 1, 2 }; -static u32 csize_list_35[] = { 1, 2 }; -static u32 csize_list_36[] = { 1, 2 }; -static u32 csize_list_37[] = { 2, 0, 1 }; -static u32 csize_list_38[] = { 1, 2 }; -static u32 csize_list_39[] = { 1, 3 }; -static u32 csize_list_40[] = { 1, 3 }; - -/* - * SCC_Configuration table - */ -static const struct scc_descriptor scc_descriptor_table[] = { -/* scn scc_name profile SCC scc_id mci_id rd wr m p fh si cfg sta */ - {"fe_", "fe_3dcomb_wr", STRM_P, SCC0_BASE, 0, 0, 0, 4, 1, 1, 0, 0, 0, 1, - buffer_list_0, csize_list_0}, - {"fe_", "fe_3dcomb_rd", STRM_P, SCC1_BASE, 1, 18, 4, 0, 1, 1, 0, 1, 0, - 1, buffer_list_1, csize_list_1}, - {"di_", "di_tnr_wr", STRM_P, SCC2_BASE, 2, 1, 0, 3, 1, 1, 0, 2, 0, 1, - buffer_list_2, csize_list_2}, - {"di_", "di_tnr_field_rd", STRM_P, SCC3_BASE, 3, 19, 3, 0, 1, 1, 0, 3, - 0, 1, buffer_list_3, csize_list_3}, - {"di_", "di_tnr_frame_rd", STRM_P, SCC4_BASE, 4, 20, 3, 0, 1, 1, 0, 4, - 0, 1, buffer_list_4, csize_list_4}, - {"di_", "di_mval_wr", STRM_P, SCC5_BASE, 5, 2, 0, 1, 1, 1, 0, 5, 0, 1, - buffer_list_5, csize_list_5}, - {"di_", "di_mval_rd", STRM_P, SCC6_BASE, 6, 21, 1, 0, 1, 1, 0, 6, 0, 1, - buffer_list_6, csize_list_6}, - {"rc_", "rc_frame_wr", STRM_P, SCC7_BASE, 7, 3, 0, 4, 1, 1, 0, 7, 0, 1, - buffer_list_7, csize_list_7}, - {"rc_", "rc_frame0_rd", STRM_P, SCC8_BASE, 8, 22, 4, 0, 1, 1, 0, 8, 0, - 1, buffer_list_8, csize_list_8}, - {"opt", "opt_field0_rd", STRM_P, SCC9_BASE, 9, 23, 3, 0, 1, 1, 0, 9, 0, - 1, buffer_list_9, csize_list_9}, - {"opt", "opt_field1_rd", STRM_P, SCC10_BASE, 10, 24, 3, 0, 1, 1, 0, 10, - 0, 1, buffer_list_10, csize_list_10}, - {"opt", "opt_field2_rd", STRM_P, SCC11_BASE, 11, 25, 3, 0, 1, 1, 0, 11, - 0, 1, buffer_list_11, csize_list_11}, - {"pip", "pip_frame_wr", STRM_P, SCC12_BASE, 12, 4, 0, 4, 1, 1, 0, 12, 0, - 1, buffer_list_12, csize_list_12}, - {"pip", "pip_frame_rd", STRM_P, SCC13_BASE, 13, 26, 4, 0, 1, 1, 0, 13, - 0, 1, buffer_list_13, csize_list_13}, - {"dp_", "dp_agpu_rd", STRM_P, SCC14_BASE, 14, 27, 2, 0, 2, 1, 0, 14, 0, - 1, buffer_list_14, csize_list_14}, - {"ewa", "ewarp_rw", SRMD, SCC15_BASE, 15, 11, 1, 1, 0, 0, 0, -1, 0, 0, - buffer_list_15, csize_list_15}, - {"dp_", "dp_osd_rd", STRM_P, SCC16_BASE, 16, 28, 3, 0, 2, 1, 0, 15, 0, - 1, buffer_list_16, csize_list_16}, - {"dp_", "dp_graphic_rd", STRM_P, SCC17_BASE, 17, 29, 3, 0, 2, 1, 0, 16, - 0, 1, buffer_list_17, csize_list_17}, - {"dvp", "dvp_osd_rd", STRM_P, SCC18_BASE, 18, 30, 2, 0, 2, 1, 0, 17, 0, - 1, buffer_list_18, csize_list_18}, - {"dvp", "dvp_vbi_rd", STRM_D, SCC19_BASE, 19, 31, 1, 0, 0, 1, 0, -1, 0, - 0, buffer_list_19, csize_list_19}, - {"tsi", "tsio_wr", STRM_P, SCC20_BASE, 20, 5, 0, 8, 2, 1, 1, -1, 0, 0, - buffer_list_20, csize_list_20}, - {"tsi", "tsio_rd", STRM_P, SCC21_BASE, 21, 32, 4, 0, 2, 1, 1, -1, 0, 0, - buffer_list_21, csize_list_21}, - {"tsd", "tsd_wr", SRMD, SCC22_BASE, 22, 6, 0, 64, 0, 0, 1, -1, 0, 0, - buffer_list_22, csize_list_22}, - {"vd_", "vd_ud_st_rw", SRMD, SCC23_BASE, 23, 12, 2, 2, 0, 0, 1, -1, 0, - 0, buffer_list_23, csize_list_23}, - {"vd_", "vd_frr_rd", SRMD, SCC24_BASE, 24, 33, 4, 0, 0, 0, 0, -1, 0, 0, - buffer_list_24, csize_list_24}, - {"vd_", "vd_frw_disp_wr", SRMD, SCC25_BASE, 25, 7, 0, 16, 0, 0, 0, -1, - 0, 0, buffer_list_25, csize_list_25}, - {"mr_", "mr_vd_m_y_rd", STRM_P, SCC26_BASE, 26, 34, 3, 0, 2, 1, 0, 18, - 0, 1, buffer_list_26, csize_list_26}, - {"mr_", "mr_vd_m_c_rd", STRM_P, SCC27_BASE, 27, 35, 3, 0, 2, 1, 0, 19, - 0, 1, buffer_list_27, csize_list_27}, - {"mr_", "mr_vd_s_y_rd", STRM_P, SCC28_BASE, 28, 36, 3, 0, 2, 1, 0, 20, - 0, 1, buffer_list_28, csize_list_28}, - {"mr_", "mr_vd_s_c_rd", STRM_P, SCC29_BASE, 29, 37, 3, 0, 2, 1, 0, 21, - 0, 1, buffer_list_29, csize_list_29}, - {"ga_", "ga_wr", STRM_P, SCC30_BASE, 30, 8, 0, 1, 1, 1, 0, -1, 1, 1, - buffer_list_30, csize_list_30}, - {"ga_", "ga_src1_rd", STRM_P, SCC31_BASE, 31, 38, 1, 0, 1, 1, 0, -1, 1, - 1, buffer_list_31, csize_list_31}, - {"ga_", "ga_src2_rd", STRM_P, SCC32_BASE, 32, 39, 1, 0, 1, 1, 0, -1, 1, - 1, buffer_list_32, csize_list_32}, - {"ad_", "ad_rd", STRM_D, SCC33_BASE, 33, 40, 2, 0, 0, 1, 1, -1, 0, 0, - buffer_list_33, csize_list_33}, - {"ad_", "ad_wr", STRM_D, SCC34_BASE, 34, 9, 0, 3, 0, 1, 1, -1, 0, 0, - buffer_list_34, csize_list_34}, - {"abp", "abp_rd", STRM_D, SCC35_BASE, 35, 41, 5, 0, 0, 1, 1, -1, 0, 0, - buffer_list_35, csize_list_35}, - {"abp", "abp_wr", STRM_D, SCC36_BASE, 36, 10, 0, 3, 0, 1, 1, -1, 0, 0, - buffer_list_36, csize_list_36}, - {"ebi", "ebi_rw", STRM_P, SCC37_BASE, 37, 13, 4, 4, 2, 1, 1, -1, 0, 0, - buffer_list_37, csize_list_37}, - {"usb", "usb_rw", SRMD, SCC38_BASE, 38, 14, 1, 1, 0, 0, 1, -1, 0, 0, - buffer_list_38, csize_list_38}, - {"cpu", "cpu1_spdma_rw", SRMD, SCC39_BASE, 39, 15, 1, 1, 0, 0, 1, -1, 0, - 0, buffer_list_39, csize_list_39}, - {"cpu", "cpu1_bridge_rw", SRMD, SCC40_BASE, 40, 16, 0, 0, 0, 0, 0, -1, - 0, 0, buffer_list_40, csize_list_40}, -}; - -/* DMA state structures for read and write channels for each SCC */ - -static struct scc_dma_state scc_state_rd_0[] = { {-1} }; -static struct scc_dma_state scc_state_wr_0[] = { {0}, {0}, {0}, {0} }; -static struct scc_dma_state scc_state_rd_1[] = { {0}, {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_1[] = { {-1} }; -static struct scc_dma_state scc_state_rd_2[] = { {-1} }; -static struct scc_dma_state scc_state_wr_2[] = { {0}, {0}, {0} }; -static struct scc_dma_state scc_state_rd_3[] = { {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_3[] = { {-1} }; -static struct scc_dma_state scc_state_rd_4[] = { {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_4[] = { {-1} }; -static struct scc_dma_state scc_state_rd_5[] = { {-1} }; -static struct scc_dma_state scc_state_wr_5[] = { {0} }; -static struct scc_dma_state scc_state_rd_6[] = { {0} }; -static struct scc_dma_state scc_state_wr_6[] = { {-1} }; -static struct scc_dma_state scc_state_rd_7[] = { {-1} }; -static struct scc_dma_state scc_state_wr_7[] = { {0}, {0}, {0}, {0} }; -static struct scc_dma_state scc_state_rd_8[] = { {0}, {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_8[] = { {-1} }; -static struct scc_dma_state scc_state_rd_9[] = { {0}, {0}, {0}, }; -static struct scc_dma_state scc_state_wr_9[] = { {-1} }; -static struct scc_dma_state scc_state_rd_10[] = { {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_10[] = { {-1} }; -static struct scc_dma_state scc_state_rd_11[] = { {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_11[] = { {-1} }; -static struct scc_dma_state scc_state_rd_12[] = { {-1} }; -static struct scc_dma_state scc_state_wr_12[] = { {0}, {0}, {0}, {0} }; -static struct scc_dma_state scc_state_rd_13[] = { {0}, {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_13[] = { {-1} }; -static struct scc_dma_state scc_state_rd_14[] = { {0}, {0} }; -static struct scc_dma_state scc_state_wr_14[] = { {-1} }; -static struct scc_dma_state scc_state_rd_15[] = { {0} }; -static struct scc_dma_state scc_state_wr_15[] = { {0} }; -static struct scc_dma_state scc_state_rd_16[] = { {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_16[] = { {-1} }; -static struct scc_dma_state scc_state_rd_17[] = { {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_17[] = { {-1} }; -static struct scc_dma_state scc_state_rd_18[] = { {0}, {0} }; -static struct scc_dma_state scc_state_wr_18[] = { {-1} }; -static struct scc_dma_state scc_state_rd_19[] = { {0} }; -static struct scc_dma_state scc_state_wr_19[] = { {-1} }; -static struct scc_dma_state scc_state_rd_20[] = { {-1} }; -static struct scc_dma_state scc_state_wr_20[] = { - {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0} }; -static struct scc_dma_state scc_state_rd_21[] = { {0}, {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_21[] = { {-1} }; -static struct scc_dma_state scc_state_rd_22[] = { {-1} }; -static struct scc_dma_state scc_state_wr_22[] = { - {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, - {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, - {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, - {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, - {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0} }; -static struct scc_dma_state scc_state_rd_23[] = { {0}, {0} }; -static struct scc_dma_state scc_state_wr_23[] = { {0}, {0} }; -static struct scc_dma_state scc_state_rd_24[] = { {0}, {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_24[] = { {-1} }; -static struct scc_dma_state scc_state_rd_25[] = { {-1} }; -static struct scc_dma_state scc_state_wr_25[] = { - {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, - {0}, {0} }; -static struct scc_dma_state scc_state_rd_26[] = { {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_26[] = { {-1} }; -static struct scc_dma_state scc_state_rd_27[] = { {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_27[] = { {-1} }; -static struct scc_dma_state scc_state_rd_28[] = { {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_28[] = { {-1} }; -static struct scc_dma_state scc_state_rd_29[] = { {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_29[] = { {-1} }; -static struct scc_dma_state scc_state_rd_30[] = { {-1} }; -static struct scc_dma_state scc_state_wr_30[] = { {0} }; -static struct scc_dma_state scc_state_rd_31[] = { {0} }; -static struct scc_dma_state scc_state_wr_31[] = { {-1} }; -static struct scc_dma_state scc_state_rd_32[] = { {0} }; -static struct scc_dma_state scc_state_wr_32[] = { {-1} }; -static struct scc_dma_state scc_state_rd_33[] = { {0}, {0} }; -static struct scc_dma_state scc_state_wr_33[] = { {-1} }; -static struct scc_dma_state scc_state_rd_34[] = { {-1} }; -static struct scc_dma_state scc_state_wr_34[] = { {0}, {0}, {0} }; -static struct scc_dma_state scc_state_rd_35[] = { {0}, {0}, {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_35[] = { {-1} }; -static struct scc_dma_state scc_state_rd_36[] = { {-1} }; -static struct scc_dma_state scc_state_wr_36[] = { {0}, {0}, {0} }; -static struct scc_dma_state scc_state_rd_37[] = { {0}, {0}, {0}, {0} }; -static struct scc_dma_state scc_state_wr_37[] = { {0}, {0}, {0}, {0} }; -static struct scc_dma_state scc_state_rd_38[] = { {0} }; -static struct scc_dma_state scc_state_wr_38[] = { {0} }; -static struct scc_dma_state scc_state_rd_39[] = { {0} }; -static struct scc_dma_state scc_state_wr_39[] = { {0} }; -static struct scc_dma_state scc_state_rd_40[] = { {-1} }; -static struct scc_dma_state scc_state_wr_40[] = { {-1} }; - -/* DMA state references to access from the driver */ -static struct scc_dma_state *scc_state_rd[] = { - scc_state_rd_0, - scc_state_rd_1, - scc_state_rd_2, - scc_state_rd_3, - scc_state_rd_4, - scc_state_rd_5, - scc_state_rd_6, - scc_state_rd_7, - scc_state_rd_8, - scc_state_rd_9, - scc_state_rd_10, - scc_state_rd_11, - scc_state_rd_12, - scc_state_rd_13, - scc_state_rd_14, - scc_state_rd_15, - scc_state_rd_16, - scc_state_rd_17, - scc_state_rd_18, - scc_state_rd_19, - scc_state_rd_20, - scc_state_rd_21, - scc_state_rd_22, - scc_state_rd_23, - scc_state_rd_24, - scc_state_rd_25, - scc_state_rd_26, - scc_state_rd_27, - scc_state_rd_28, - scc_state_rd_29, - scc_state_rd_30, - scc_state_rd_31, - scc_state_rd_32, - scc_state_rd_33, - scc_state_rd_34, - scc_state_rd_35, - scc_state_rd_36, - scc_state_rd_37, - scc_state_rd_38, - scc_state_rd_39, - scc_state_rd_40, -}; - -static struct scc_dma_state *scc_state_wr[] = { - scc_state_wr_0, - scc_state_wr_1, - scc_state_wr_2, - scc_state_wr_3, - scc_state_wr_4, - scc_state_wr_5, - scc_state_wr_6, - scc_state_wr_7, - scc_state_wr_8, - scc_state_wr_9, - scc_state_wr_10, - scc_state_wr_11, - scc_state_wr_12, - scc_state_wr_13, - scc_state_wr_14, - scc_state_wr_15, - scc_state_wr_16, - scc_state_wr_17, - scc_state_wr_18, - scc_state_wr_19, - scc_state_wr_20, - scc_state_wr_21, - scc_state_wr_22, - scc_state_wr_23, - scc_state_wr_24, - scc_state_wr_25, - scc_state_wr_26, - scc_state_wr_27, - scc_state_wr_28, - scc_state_wr_29, - scc_state_wr_30, - scc_state_wr_31, - scc_state_wr_32, - scc_state_wr_33, - scc_state_wr_34, - scc_state_wr_35, - scc_state_wr_36, - scc_state_wr_37, - scc_state_wr_38, - scc_state_wr_39, - scc_state_wr_40, -}; - -static u32 scc_takeover_mode = SCC_TO_IMMEDIATE; - -/* Change mode of the SPDMA for given direction */ -static u32 scc_agu_mode_sp = AGU_BYPASS; - -/* Change mode of the USB for given direction */ -static u32 scc_agu_mode_usb = AGU_BYPASS; - -static union scc_softwareconfiguration scc_software_configuration[SCC_MAX]; - -static u32 dma_fsm[4][4] = { - /* DMA_CMD_RESET DMA_CMD_SETUP DMA_CMD_START DMA_CMD_STOP */ - /* DMA_STATE_RESET */ - {DMA_STATE_RESET, DMA_STATE_SETUP, DMA_STATE_ERROR, DMA_STATE_ERROR}, - /* DMA_STATE_SETUP */ - {DMA_STATE_RESET, DMA_STATE_SETUP, DMA_STATE_START, DMA_STATE_SETUP}, - /* DMA_STATE_START */ - {DMA_STATE_RESET, DMA_STATE_ERROR, DMA_STATE_START, DMA_STATE_SETUP}, - /* DMA_STATE_ERROR */ - {DMA_STATE_RESET, DMA_STATE_ERROR, DMA_STATE_ERROR, DMA_STATE_ERROR}, -}; - -static void dma_state_process(struct scc_dma_state *dma_state, u32 cmd) -{ - dma_state->dma_status = dma_fsm[dma_state->dma_status][cmd]; - dma_state->dma_cmd = cmd; -} - -static void dma_state_process_dma_command(struct scc_dma_state *dma_state, - u32 dma_cmd) -{ - dma_state->dma_cmd = dma_cmd; - switch (dma_cmd) { - case DMA_START: - case DMA_START_FH_RESET: - dma_state_process(dma_state, DMA_CMD_START); - break; - case DMA_STOP: - dma_state_process(dma_state, DMA_CMD_STOP); - break; - default: - break; - } -} - -static void scc_takeover_dma(enum scc_id id, u32 dma_id, u32 drs) -{ - union scc_cmd dma_cmd; - - dma_cmd.reg = 0; - - /* Prepare the takeover for the DMA channel */ - dma_cmd.bits.action = DMA_TAKEOVER; - dma_cmd.bits.id = dma_id; - dma_cmd.bits.rid = TO_DMA_CFG; /* this is DMA_CFG register takeover */ - if (drs == DMA_WRITE) - dma_cmd.bits.drs = DMA_WRITE; - - reg_write(SCC_CMD(scc_descriptor_table[id].base_address), dma_cmd.reg); -} - -int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs) -{ - union scc_cmd dma_cmd; - struct scc_dma_state *dma_state; - - if ((id >= SCC_MAX) || (id < 0)) - return -EINVAL; - - dma_cmd.reg = 0; - - /* Prepare the takeover for the DMA channel */ - dma_cmd.bits.action = cmd; - dma_cmd.bits.id = dma_id; - if (drs == DMA_WRITE) { - dma_cmd.bits.drs = DMA_WRITE; - dma_state = &scc_state_wr[id][dma_id]; - } else { - dma_state = &scc_state_rd[id][dma_id]; - } - - dma_state->scc_id = id; - dma_state->dma_id = dma_id; - dma_state_process_dma_command(dma_state, cmd); - - reg_write(SCC_CMD(scc_descriptor_table[id].base_address), dma_cmd.reg); - - return 0; -} - -int scc_set_usb_address_generation_mode(u32 agu_mode) -{ - if (AGU_ACTIVE == agu_mode) { - /* Ensure both DMAs are stopped */ - scc_dma_cmd(SCC_USB_RW, DMA_STOP, 0, DMA_WRITE); - scc_dma_cmd(SCC_USB_RW, DMA_STOP, 0, DMA_READ); - } else { - agu_mode = AGU_BYPASS; - } - - scc_agu_mode_usb = agu_mode; - - return 0; -} - -int scc_setup_dma(enum scc_id id, u32 buffer_tag, - u32 type, u32 fh_mode, u32 drs, u32 dma_id) -{ - struct scc_dma_state *dma_state; - int return_value = 0; - union scc_dma_cfg dma_cfg; - u32 *buffer_tag_list; - u32 tag_count, t, t_valid; - - if ((id >= SCC_MAX) || (id < 0)) - return -EINVAL; - - buffer_tag_list = scc_descriptor_table[id].buffer_tag_list; - - /* if the register is only configured by hw, cannot write! */ - if (1 == scc_descriptor_table[id].hw_dma_cfg) - return -EACCES; - - if (DMA_WRITE == drs) { - if (dma_id >= scc_descriptor_table[id].p_dma_channels_wr) - return -EINVAL; - dma_state = &scc_state_wr[id][dma_id]; - } else { - if (dma_id >= scc_descriptor_table[id].p_dma_channels_rd) - return -EINVAL; - dma_state = &scc_state_rd[id][dma_id]; - } - - /* Compose the DMA configuration register */ - tag_count = buffer_tag_list[0]; - t_valid = 0; - for (t = 1; t <= tag_count; t++) { - if (buffer_tag == buffer_tag_list[t]) { - /* Tag found - validate */ - t_valid = 1; - break; - } - } - - if (!t_valid) - return -EACCES; - - /* - * Read the register first -- two functions write into the register - * it does not make sense to read the DMA config back, because there - * are two register configuration sets (drs) - */ - dma_cfg.reg = 0; - dma_cfg.bits.buffer_id = buffer_tag; - dma_state_process(dma_state, DMA_CMD_SETUP); - - /* - * This is Packet CFG set select - usable for TSIO, EBI and those SCCs - * which habe 2 packet configs - */ - dma_cfg.bits.packet_cfg_id = - scc_software_configuration[id].bits.packet_select; - - if (type == DMA_CYCLIC) - dma_cfg.bits.buffer_type = 1; - else - dma_cfg.bits.buffer_type = 0; - - if (fh_mode == USE_FH) - dma_cfg.bits.fh_mode = 1; - else - dma_cfg.bits.fh_mode = 0; - - if (id == SCC_CPU1_SPDMA_RW) - dma_cfg.bits.agu_mode = scc_agu_mode_sp; - - if (id == SCC_USB_RW) - dma_cfg.bits.agu_mode = scc_agu_mode_usb; - - reg_write(SCC_DMA_CFG(scc_descriptor_table[id].base_address), - dma_cfg.reg); - - /* The DMA_CFG needs a takeover! */ - if (SCC_TO_IMMEDIATE == scc_takeover_mode) - scc_takeover_dma(id, dma_id, drs); - - /* if (buffer_tag is not used) */ - dma_state->buffer_tag = buffer_tag; - - dma_state->scc_id = id; - dma_state->dma_id = dma_id; - - return return_value; -} - -int scc_enable(enum scc_id id, u32 value) -{ - if ((id >= SCC_MAX) || (id < 0)) - return -EINVAL; - - if (value == 0) { - scc_software_configuration[id].bits.enable_status = 0; - } else { - value = 1; - scc_software_configuration[id].bits.enable_status = 1; - } - reg_write(SCC_ENABLE(scc_descriptor_table[id].base_address), value); - - return 0; -} - -static inline void ehb(void) -{ - __asm__ __volatile__( - " .set mips32r2 \n" - " ehb \n" - " .set mips0 \n"); -} - -int scc_reset(enum scc_id id, u32 value) -{ - if ((id >= SCC_MAX) || (id < 0)) - return -EINVAL; - - /* Invert value to the strait logic from the negative hardware logic */ - if (value == 0) - value = 1; - else - value = 0; - - /* Write the value to the register */ - reg_write(SCC_RESET(scc_descriptor_table[id].base_address), value); - - /* sync flush */ - asm("sync"); /* request bus write queue flush */ - ehb(); /* wait until previous bus commit instr has finished */ - asm("nop"); /* wait for flush to occur */ - asm("nop"); /* wait for flush to occur */ - - udelay(100); - - return 0; -} diff --git a/board/micronas/vct/scc.h b/board/micronas/vct/scc.h deleted file mode 100644 index 48cae55eee9..00000000000 --- a/board/micronas/vct/scc.h +++ /dev/null @@ -1,191 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Copyright (C) 2006 Micronas GmbH - */ - -#ifndef _SCC_H -#define _SCC_H - -#define DMA_READ 0 /* SCC read DMA */ -#define DMA_WRITE 1 /* SCC write DMA */ - -#define DMA_LINEAR 0 /* DMA linear buffer access method */ -#define DMA_CYCLIC 1 /* DMA cyclic buffer access method */ - -#define DMA_START 0 /* DMA command - start DMA */ -#define DMA_STOP 1 /* DMA command - stop DMA */ -#define DMA_START_FH_RESET 2 /* DMA command - start DMA reset FH */ -#define DMA_TAKEOVER 15 /* DMA command - commit the DMA conf */ - -#define AGU_ACTIVE 0 /* enable AGU address calculation */ -#define AGU_BYPASS 1 /* set AGU to bypass mode */ - -#define USE_NO_FH 0 /* order the DMA to not use FH */ -#define USE_FH 1 /* order the DMA to work with FH*/ - -#define SCC_DBG_IDLE 0 /* DEBUG status (idle interfaces) */ -#define SCC_DBG_SYNC_RES 0x0001 /* synchronuous reset */ - -#define SCC_TO_IMMEDIATE 1 /* takeover command issued immediately*/ -#define TO_DMA_CFG 2 /* takeover command for the DMA config*/ - -#define DMA_CMD_RESET 0 -#define DMA_CMD_SETUP 1 -#define DMA_CMD_START 2 -#define DMA_CMD_STOP 3 - -#define DMA_STATE_RESET 0 -#define DMA_STATE_SETUP 1 -#define DMA_STATE_START 2 -#define DMA_STATE_ERROR 3 - -#define SRMD 0 -#define STRM_D 1 -#define STRM_P 2 - -/* - * Slowest Monterey domain is DVP 27 MHz (324/27 = 12; 12*16 = 192 CPU clocks) - */ -#define RESET_TIME 2 /* cycle calc see in SCC_Reset */ - -struct scc_descriptor { - char *pu_name; /* PU identifier */ - char *scc_instance; /* SCC Name */ - u32 profile; /* SCC VCI_D profile */ - - u32 base_address; /* base address of the SCC unit reg shell*/ - - /* SCS Interconnect configuration */ - u32 p_scc_id; /* instance number of SCC unit */ - u32 p_mci_id; /* memory channel ID */ - - /* DMA Registers configuration */ - u32 p_dma_channels_rd; /* Number of Read DMA channels */ - u32 p_dma_channels_wr; /* Number of Write DMA channels */ - - u32 p_dma_packet_desc; /* Number of packet descriptors */ - u32 p_dma_mci_desc; /* Number of MCI_CFG Descriptors */ - - int use_fh; /* the flag tells if SCC uses an FH */ - - int p_si2ocp_id; /* instance number of SI2OCP unit */ - int hw_dma_cfg; /* HW or SW DMA config flag */ - int hw_dma_start; /* HW or SW DMA start/stop flag */ - - u32 *buffer_tag_list; /* list of the buffer tags available */ - u32 *csize_list; /* list of the valid CSIZE values */ -}; - -struct scc_dma_state { - u32 scc_id:8; /* SCC id */ - u32 dma_id:8; /* DMA id, used for match with array idx*/ - u32 buffer_tag:8; /* mem buf tag, assigned to this DMA */ - u32 dma_status:2; /* state of DMA, of the DMA_STATE_ const*/ - u32 dma_drs:2; /* DMA dir, either DMA_READ or DMA_WRITE*/ - u32 dma_cmd:4; /* last executed command on this DMA */ -}; - -union scc_cmd { - u32 reg; - struct { - u32 res1:19; /* reserved */ - u32 drs:1; /* DMA Register Set */ - u32 rid:2; /* Register Identifier */ - u32 id:6; /* DMA Identifier */ - u32 action:4; /* DMA Command encoding */ - } bits; -}; - -union scc_dma_cfg { - u32 reg; - struct { - u32 res1:17; /* reserved */ - u32 agu_mode:1; /* AGU Mode */ - u32 res2:1; /* reserved */ - u32 fh_mode:1; /* Fifo Handler */ - u32 buffer_type:1; /* Defines type of mem buffers */ - u32 mci_cfg_id:1; /* MCI_CFG register selector */ - u32 packet_cfg_id:1; /* PACKET_CFG register selector */ - u32 buffer_id:8; /* DMA Buffer Identifier */ - } bits; -}; - -union scc_debug { - u32 reg; - struct { - u32 res1:20; /* reserved */ - u32 arg:8; /* SCC Debug Command Argument (#) */ - u32 cmd:4; /* SCC Debug Command Register */ - } bits; -}; - -union scc_softwareconfiguration { - u32 reg; - struct { - u32 res1:28; /* reserved */ - u32 clock_status:1; /* clock on/off */ - u32 packet_select:1; /* active SCC packet id */ - u32 enable_status:1; /* enabled [1/0] */ - u32 active_status:1; /* 1=active 0=reset */ - } bits; -}; - -/* - * System on Chip Channel ID - */ -enum scc_id { - SCC_NULL = -1, /* illegal SCC identifier */ - SCC_FE_3DCOMB_WR, /* SCC_FE_3DCOMB Write channel */ - SCC_FE_3DCOMB_RD, /* SCC_FE_3DCOMB Read channel */ - SCC_DI_TNR_WR, /* SCC_DI_TNR Write channel */ - SCC_DI_TNR_FIELD_RD, /* SCC_DI_TNR_FIELD Read channel */ - SCC_DI_TNR_FRAME_RD, /* SCC_DI_TNR_FRAME Read channel */ - SCC_DI_MVAL_WR, /* SCC_DI_MVAL Write channel */ - SCC_DI_MVAL_RD, /* SCC_DI_MVAL Read channel */ - SCC_RC_FRAME_WR, /* SCC_RC_FRAME Write channel */ - SCC_RC_FRAME0_RD, /* SCC_RC_FRAME0 Read channel */ - SCC_OPT_FIELD0_RD, /* SCC_OPT_FIELD0 Read channel */ - SCC_OPT_FIELD1_RD, /* SCC_OPT_FIELD1 Read channel */ - SCC_OPT_FIELD2_RD, /* SCC_OPT_FIELD2 Read channel */ - SCC_PIP_FRAME_WR, /* SCC_PIP_FRAME Write channel */ - SCC_PIP_FRAME_RD, /* SCC_PIP_FRAME Read channel */ - SCC_DP_AGPU_RD, /* SCC_DP_AGPU Read channel */ - SCC_EWARP_RW, /* SCC_EWARP Read/Write channel */ - SCC_DP_OSD_RD, /* SCC_DP_OSD Read channel */ - SCC_DP_GRAPHIC_RD, /* SCC_DP_GRAPHIC Read channel */ - SCC_DVP_OSD_RD, /* SCC_DVP_OSD Read channel */ - SCC_DVP_VBI_RD, /* SCC_DVP_VBI Read channel */ - SCC_TSIO_WR, /* SCC_TSIO Write channel */ - SCC_TSIO_RD, /* SCC_TSIO Read channel */ - SCC_TSD_WR, /* SCC_TSD Write channel */ - SCC_VD_UD_ST_RW, /* SCC_VD_UD_ST Read/Write channel */ - SCC_VD_FRR_RD, /* SCC_VD_FRR Read channel */ - SCC_VD_FRW_DISP_WR, /* SCC_VD_FRW_DISP Write channel */ - SCC_MR_VD_M_Y_RD, /* SCC_MR_VD_M_Y Read channel */ - SCC_MR_VD_M_C_RD, /* SCC_MR_VD_M_C Read channel */ - SCC_MR_VD_S_Y_RD, /* SCC_MR_VD_S_Y Read channel */ - SCC_MR_VD_S_C_RD, /* SCC_MR_VD_S_C Read channel */ - SCC_GA_WR, /* SCC_GA Write channel */ - SCC_GA_SRC1_RD, /* SCC_GA_SRC1 Read channel */ - SCC_GA_SRC2_RD, /* SCC_GA_SRC2 Read channel */ - SCC_AD_RD, /* SCC_AD Read channel */ - SCC_AD_WR, /* SCC_AD Write channel */ - SCC_ABP_RD, /* SCC_ABP Read channel */ - SCC_ABP_WR, /* SCC_ABP Write channel */ - SCC_EBI_RW, /* SCC_EBI Read/Write channel */ - SCC_USB_RW, /* SCC_USB Read/Write channel */ - SCC_CPU1_SPDMA_RW, /* SCC_CPU1_SPDMA Read/Write channel */ - SCC_CPU1_BRIDGE_RW, /* SCC_CPU1_BRIDGE Read/Write channel */ - SCC_MAX /* maximum limit on the SCC id */ -}; - -int scc_set_usb_address_generation_mode(u32 agu_mode); -int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs); -int scc_setup_dma(enum scc_id id, u32 buffer_tag, - u32 type, u32 fh_mode, u32 drs, u32 dma_id); -int scc_enable(enum scc_id id, u32 value); -int scc_reset(enum scc_id id, u32 value); - -#endif /* _SCC_H */ diff --git a/board/micronas/vct/smc_eeprom.c b/board/micronas/vct/smc_eeprom.c deleted file mode 100644 index b5a552134e7..00000000000 --- a/board/micronas/vct/smc_eeprom.c +++ /dev/null @@ -1,394 +0,0 @@ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Copyright 2005, Seagate Technology LLC - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#undef DEBUG - -#include <common.h> -#include <command.h> -#include <config.h> -#include <net.h> - -#include "vct.h" - -#define SMSC9118_BASE CONFIG_DRIVER_SMC911X_BASE -#define BYTE_TEST (SMSC9118_BASE + 0x64) -#define GPIO_CFG (SMSC9118_BASE + 0x88) -#define MAC_CSR_CMD (SMSC9118_BASE + 0xA4) -#define MAC_CSR_CMD_CSR_BUSY (0x80000000) -#define MAC_CSR_CMD_RNW (0x40000000) -#define MAC_RD_CMD(reg) ((reg & 0x000000FF) | \ - (MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_RNW)) -#define MAC_WR_CMD(reg) ((reg & 0x000000FF) | \ - (MAC_CSR_CMD_CSR_BUSY)) -#define MAC_CSR_DATA (SMSC9118_BASE + 0xA8) -#define E2P_CMD (SMSC9118_BASE + 0xB0) -#define E2P_CMD_EPC_BUSY_ (0x80000000UL) /* Self Clearing */ -#define E2P_CMD_EPC_CMD_ (0x70000000UL) /* R/W */ -#define E2P_CMD_EPC_CMD_READ_ (0x00000000UL) /* R/W */ -#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000UL) /* R/W */ -#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000UL) /* R/W */ -#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000UL) /* R/W */ -#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000UL) /* R/W */ -#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000UL) /* R/W */ -#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000UL) /* R/W */ -#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000UL) /* R/W */ -#define E2P_CMD_EPC_TIMEOUT_ (0x00000200UL) /* R */ -#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100UL) /* RO */ -#define E2P_CMD_EPC_ADDR_ (0x000000FFUL) /* R/W */ -#define E2P_DATA (SMSC9118_BASE + 0xB4) - -#define MAC_ADDRH (0x2) -#define MAC_ADDRL (0x3) - -#define MAC_TIMEOUT 200 - -#define HIBYTE(word) ((u8)(((u16)(word)) >> 8)) -#define LOBYTE(word) ((u8)(((u16)(word)) & 0x00FFU)) -#define HIWORD(dword) ((u16)(((u32)(dword)) >> 16)) -#define LOWORD(dword) ((u16)(((u32)(dword)) & 0x0000FFFFUL)) - -static int mac_busy(int req_to) -{ - int timeout = req_to; - - while (timeout--) { - if (!(smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)) - goto done; - } - return 1; /* Timeout */ - -done: - return 0; /* No timeout */ -} - -static ulong get_mac_reg(int reg) -{ - ulong reg_val = 0xffffffff; - - if (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) { - printf("get_mac_reg: previous command not complete\n"); - goto done; - } - - smc911x_reg_write(MAC_CSR_CMD, MAC_RD_CMD(reg)); - udelay(10000); - - if (mac_busy(MAC_TIMEOUT) == 1) { - printf("get_mac_reg: timeout waiting for response from MAC\n"); - goto done; - } - - reg_val = smc911x_reg_read(MAC_CSR_DATA); - -done: - return (reg_val); -} - -static ulong eeprom_enable_access(void) -{ - ulong gpio; - - gpio = smc911x_reg_read(GPIO_CFG); - debug("%s: gpio= 0x%08lx ---> 0x%08lx\n", __func__, gpio, - (gpio & 0xFF0FFFFFUL)); - - smc911x_reg_write(GPIO_CFG, (gpio & 0xFF0FFFFFUL)); - return gpio; -} - -static void eeprom_disable_access(ulong gpio) -{ - debug("%s: gpio= 0x%08lx\n", __func__, gpio); - smc911x_reg_write(GPIO_CFG, gpio); -} - -static int eeprom_is_mac_address_loaded(void) -{ - int ret; - - ret = smc911x_reg_read(MAC_CSR_CMD) & E2P_CMD_MAC_ADDR_LOADED_; - debug("%s: ret = %x\n", __func__, ret); - - return ret; -} - -static int eeprom_read_location(unchar address, u8 *data) -{ - ulong timeout = 100000; - ulong temp = 0; - - if ((temp = smc911x_reg_read(E2P_CMD)) & E2P_CMD_EPC_BUSY_) { - printf("%s: Busy at start, E2P_CMD=0x%08lX\n", __func__, temp); - return 0; - } - - smc911x_reg_write(E2P_CMD, - (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_ | - ((ulong) address))); - - while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { - udelay(10); - timeout--; - } - - if (timeout == 0) { - printf("Timeout\n"); - return 0; - } - (*data) = (unchar) (smc911x_reg_read(E2P_DATA)); - debug("%s: ret = %x\n", __func__, (*data)); - - return 1; -} - -static int eeprom_enable_erase_and_write(void) -{ - ulong timeout = 100000; - - if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { - printf("%s: Busy at start\n", __func__); - return 0; - } - smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_)); - - while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { - udelay(10); - timeout--; - } - - if (timeout == 0) { - printf("Timeout[1]\n"); - return 0; - } - - return 1; -} - -static int eeprom_disable_erase_and_write(void) -{ - ulong timeout = 100000; - - if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { - printf("%s: Busy at start\n", __func__); - return 0; - } - smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWDS_)); - - while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { - udelay(10); - timeout--; - } - - if (timeout == 0) { - printf("Timeout[2]\n"); - return 0; - } - - return 1; -} - -static int eeprom_write_location(unchar address, unchar data) -{ - ulong timeout = 100000; - - debug("%s: address: %x data = %x\n", __func__, address, data); - - if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { - printf("%s: Busy at start\n", __func__); - return 0; - } - - smc911x_reg_write(E2P_DATA, ((ulong) data)); - smc911x_reg_write(E2P_CMD, - (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_ | - ((ulong) address))); - - while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { - udelay(10); - timeout--; - } - - if (timeout == 0) { - printf("Timeout[3]\n"); - return 0; - } - - return 1; -} - -static int eeprom_erase_all(void) -{ - ulong timeout = 100000; - - if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { - printf("%s: Busy at start\n", __func__); - return 0; - } - - smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_ERAL_)); - - while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { - udelay(10); - timeout--; - } - - if (timeout == 0) { - printf("Timeout[4]\n"); - return 0; - } - - return 1; -} - -static int eeprom_reload(void) -{ - ulong timeout = 100000; - - if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { - printf("%s: Busy at start\n", __func__); - return -1; - } - smc911x_reg_write(E2P_CMD, - (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_)); - - while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { - udelay(10); - timeout--; - } - - if (timeout == 0) - return 0; - - return 1; -} - -static int eeprom_save_mac_address(ulong dwHi16, ulong dwLo32) -{ - int result = 0; - - debug("%s: dwHI: 0x%08lx dwLO: %08lx, \n", __func__, dwHi16, dwLo32); - - if (!eeprom_enable_erase_and_write()) - goto DONE; - if (!eeprom_erase_all()) - goto DONE; - if (!eeprom_write_location(0, 0xA5)) - goto DONE; - if (!eeprom_write_location(1, LOBYTE(LOWORD(dwLo32)))) - goto DONE; - if (!eeprom_write_location(2, HIBYTE(LOWORD(dwLo32)))) - goto DONE; - if (!eeprom_write_location(3, LOBYTE(HIWORD(dwLo32)))) - goto DONE; - if (!eeprom_write_location(4, HIBYTE(HIWORD(dwLo32)))) - goto DONE; - if (!eeprom_write_location(5, LOBYTE(LOWORD(dwHi16)))) - goto DONE; - if (!eeprom_write_location(6, HIBYTE(LOWORD(dwHi16)))) - goto DONE; - if (!eeprom_disable_erase_and_write()) - goto DONE; - - result = 1; - -DONE: - return result; -} - -static int do_eeprom_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unchar data = 0, index = 0; - ulong gpio_old_val; - - gpio_old_val = eeprom_enable_access(); - - printf("EEPROM content: \n"); - for (index = 0; index < 8; index++) { - if (eeprom_read_location(index, &data)) - printf("%02x ", data); - else - printf("FAILED"); - } - - eeprom_disable_access(gpio_old_val); - printf("\n"); - - return 0; -} - -static int do_eeprom_erase_all(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - eeprom_erase_all(); - - return 0; -} - -static int do_eeprom_save_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong hi16, lo32; - unchar ethaddr[6], i; - ulong gpio; - char *tmp, *end; - - tmp = argv[1]; - for (i = 0; i < 6; i++) { - ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end + 1 : end; - } - - hi16 = (ethaddr[5] << 8) | (ethaddr[4]); - lo32 = (ethaddr[3] << 24) | (ethaddr[2] << 16) | - (ethaddr[1] << 8) | (ethaddr[0]); - - gpio = eeprom_enable_access(); - - eeprom_save_mac_address(hi16, lo32); - - eeprom_reload(); - - /* Check new values */ - if (eeprom_is_mac_address_loaded()) { - ulong mac_hi16, mac_lo32; - - mac_hi16 = get_mac_reg(MAC_ADDRH); - mac_lo32 = get_mac_reg(MAC_ADDRL); - printf("New MAC address: %lx, %lx\n", mac_hi16, mac_lo32); - } else { - printf("Address is not reloaded \n"); - } - eeprom_disable_access(gpio); - - return 0; -} - -U_BOOT_CMD(smcee, 1, 0, do_eeprom_erase_all, - "smcee - Erase content of SMC EEPROM",); - -U_BOOT_CMD(smced, 1, 0, do_eeprom_dump, - "smced - Dump content of SMC EEPROM",); - -U_BOOT_CMD(smcew, 2, 0, do_eeprom_save_mac, - "smcew - Write MAC address to SMC EEPROM\n", - "aa:bb:cc:dd:ee:ff new mac address"); diff --git a/board/micronas/vct/top.c b/board/micronas/vct/top.c deleted file mode 100644 index fa039ee03d5..00000000000 --- a/board/micronas/vct/top.c +++ /dev/null @@ -1,275 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Copyright (C) 2006 Micronas GmbH - */ - -#include <common.h> -#include "vct.h" - -typedef union _TOP_PINMUX_t -{ - u32 reg; - struct { - u32 res : 24; /* reserved */ - u32 drive : 2; /* Driver strength */ - u32 slew : 1; /* Slew rate */ - u32 strig : 1; /* Schmitt trigger input*/ - u32 pu_pd : 2; /* Pull up/ pull down */ - u32 funsel : 2; /* Pin function */ - } Bits; -} TOP_PINMUX_t; - -#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) - -static TOP_PINMUX_t top_read_pin(int pin) -{ - TOP_PINMUX_t reg; - - switch (pin) { - case 2: - case 3: - case 6: - case 9: - reg.reg = 0xdeadbeef; - break; - case 4: - reg.reg = reg_read(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE)); - break; - case 5: - reg.reg = reg_read(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE)); - break; - case 7: - reg.reg = reg_read(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE)); - break; - case 8: - reg.reg = reg_read(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE)); - break; - case 10: - case 11: - case 12: - case 13: - case 14: - case 15: - case 16: - reg.reg = reg_read(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS + - ((pin - 10) * 4)); - break; - default: - reg.reg = reg_read(TOP_BASE + (pin * 4)); - break; - } - - return reg; -} - -static void top_write_pin(int pin, TOP_PINMUX_t reg) -{ - - switch (pin) { - case 4: - reg_write(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE), reg.reg); - break; - case 5: - reg_write(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE), reg.reg); - break; - case 7: - reg_write(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE), reg.reg); - break; - case 8: - reg_write(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE), reg.reg); - break; - case 10: - case 11: - case 12: - case 13: - case 14: - case 15: - case 16: - reg_write(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS + - ((pin - 10) * 4), reg.reg); - break; - default: - reg_write(TOP_BASE + (pin * 4), reg.reg); - break; - } -} - -int top_set_pin(int pin, int func) -{ - TOP_PINMUX_t reg; - - /* check global range */ - if ((pin < 0) || (pin > 170) || (func < 0) || (func > 3)) - return -1; /* pin number or function out of valid range */ - - /* check undefined values; */ - if ((pin == 2) || (pin == 3) || (pin == 6) || (pin == 9)) - return -1; /* pin number out of valid range */ - - reg = top_read_pin(pin); - reg.Bits.funsel = func; - top_write_pin(pin, reg); - - return 0; -} - -#endif - -#if defined(CONFIG_VCT_PLATINUMAVC) - -int top_set_pin(int pin, int func) -{ - TOP_PINMUX_t reg; - - /* check global range */ - if ((pin < 0) || (pin > 158)) - return -1; /* pin number or function out of valid range */ - - reg.reg = reg_read(TOP_BASE + (pin * 4)); - reg.Bits.funsel = func; - reg_write(TOP_BASE + (pin * 4), reg.reg); - - return 0; -} - -#endif - -void vct_pin_mux_initialize(void) -{ -#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) - top_set_pin(34, 01); /* EBI_CS0 */ - top_set_pin(33, 01); /* EBI_CS1 */ - top_set_pin(32, 01); /* EBI_CS2 */ - top_set_pin(100, 02); /* EBI_CS3 */ - top_set_pin(101, 02); /* EBI_CS4 */ - top_set_pin(102, 02); /* EBI_CS5 */ - top_set_pin(103, 02); /* EBI_CS6 */ - top_set_pin(104, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */ - top_set_pin(35, 01); /* EBI_ALE */ - top_set_pin(36, 01); /* EBI_ADDR15 */ - top_set_pin(37, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */ - top_set_pin(38, 01); /* EBI_ADDR13 */ - top_set_pin(39, 01); /* EBI_ADDR12 */ - top_set_pin(40, 01); /* EBI_ADDR11 */ - top_set_pin(41, 01); /* EBI_ADDR10 */ - top_set_pin(42, 01); /* EBI_ADDR9 */ - top_set_pin(43, 01); /* EBI_ADDR8 */ - top_set_pin(44, 01); /* EBI_ADDR7 */ - top_set_pin(45, 01); /* EBI_ADDR6 */ - top_set_pin(46, 01); /* EBI_ADDR5 */ - top_set_pin(47, 01); /* EBI_ADDR4 */ - top_set_pin(48, 01); /* EBI_ADDR3 */ - top_set_pin(49, 01); /* EBI_ADDR2 */ - top_set_pin(50, 01); /* EBI_ADDR1 */ - top_set_pin(51, 01); /* EBI_ADDR0 */ - top_set_pin(52, 01); /* EBI_DIR */ - top_set_pin(53, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */ - top_set_pin(54, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */ - top_set_pin(55, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */ - top_set_pin(56, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */ - top_set_pin(57, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */ - top_set_pin(58, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */ - top_set_pin(59, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */ - top_set_pin(60, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */ - top_set_pin(61, 01); /* EBI_DAT7 */ - top_set_pin(62, 01); /* EBI_DAT6 */ - top_set_pin(63, 01); /* EBI_DAT5 */ - top_set_pin(64, 01); /* EBI_DAT4 */ - top_set_pin(65, 01); /* EBI_DAT3 */ - top_set_pin(66, 01); /* EBI_DAT2 */ - top_set_pin(67, 01); /* EBI_DAT1 */ - top_set_pin(68, 01); /* EBI_DAT0 */ - top_set_pin(69, 01); /* EBI_IORD */ - top_set_pin(70, 01); /* EBI_IOWR */ - top_set_pin(71, 01); /* EBI_WE */ - top_set_pin(72, 01); /* EBI_OE */ - top_set_pin(73, 01); /* EBI_IORDY */ - top_set_pin(95, 02); /* EBI_EBI_DMACK*/ - top_set_pin(112, 02); /* EBI_IRQ0 */ - top_set_pin(111, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */ - top_set_pin(107, 02); /* EBI_IRQ2 */ - top_set_pin(108, 02); /* EBI_IRQ3 */ - top_set_pin(30, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */ - top_set_pin(31, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */ - top_set_pin(105, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */ - top_set_pin(106, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */ - top_set_pin(109, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */ - top_set_pin(110, 02); /* EBI_BURST_CLK */ -#endif - -#if defined(CONFIG_VCT_PLATINUMAVC) - top_set_pin(19, 01); /* EBI_CS0 */ - top_set_pin(18, 01); /* EBI_CS1 */ - top_set_pin(17, 01); /* EBI_CS2 */ - top_set_pin(92, 02); /* EBI_CS3 */ - top_set_pin(93, 02); /* EBI_CS4 */ - top_set_pin(95, 02); /* EBI_CS6 */ - top_set_pin(96, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */ - top_set_pin(20, 01); /* EBI_ALE */ - top_set_pin(21, 01); /* EBI_ADDR15 */ - top_set_pin(22, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */ - top_set_pin(23, 01); /* EBI_ADDR13 */ - top_set_pin(24, 01); /* EBI_ADDR12 */ - top_set_pin(25, 01); /* EBI_ADDR11 */ - top_set_pin(26, 01); /* EBI_ADDR10 */ - top_set_pin(27, 01); /* EBI_ADDR9 */ - top_set_pin(28, 01); /* EBI_ADDR8 */ - top_set_pin(29, 01); /* EBI_ADDR7 */ - top_set_pin(30, 01); /* EBI_ADDR6 */ - top_set_pin(31, 01); /* EBI_ADDR5 */ - top_set_pin(32, 01); /* EBI_ADDR4 */ - top_set_pin(33, 01); /* EBI_ADDR3 */ - top_set_pin(34, 01); /* EBI_ADDR2 */ - top_set_pin(35, 01); /* EBI_ADDR1 */ - top_set_pin(36, 01); /* EBI_ADDR0 */ - top_set_pin(37, 01); /* EBI_DIR */ - top_set_pin(38, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */ - top_set_pin(39, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */ - top_set_pin(40, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */ - top_set_pin(41, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */ - top_set_pin(42, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */ - top_set_pin(43, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */ - top_set_pin(44, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */ - top_set_pin(45, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */ - top_set_pin(46, 01); /* EBI_DAT7 */ - top_set_pin(47, 01); /* EBI_DAT6 */ - top_set_pin(48, 01); /* EBI_DAT5 */ - top_set_pin(49, 01); /* EBI_DAT4 */ - top_set_pin(50, 01); /* EBI_DAT3 */ - top_set_pin(51, 01); /* EBI_DAT2 */ - top_set_pin(52, 01); /* EBI_DAT1 */ - top_set_pin(53, 01); /* EBI_DAT0 */ - top_set_pin(54, 01); /* EBI_IORD */ - top_set_pin(55, 01); /* EBI_IOWR */ - top_set_pin(56, 01); /* EBI_WE */ - top_set_pin(57, 01); /* EBI_OE */ - top_set_pin(58, 01); /* EBI_IORDY */ - top_set_pin(87, 02); /* EBI_EBI_DMACK*/ - top_set_pin(106, 02); /* EBI_IRQ0 */ - top_set_pin(105, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */ - top_set_pin(101, 02); /* EBI_IRQ2 */ - top_set_pin(102, 02); /* EBI_IRQ3 */ - top_set_pin(15, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */ - top_set_pin(16, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */ - top_set_pin(99, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */ - top_set_pin(100, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */ - top_set_pin(103, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */ - top_set_pin(104, 02); /* EBI_BURST_CLK */ -#endif - - /* I2C: Configure I2C-2 as GPIO to enable soft-i2c */ - top_set_pin(0, 2); /* SCL2 on GPIO 11 */ - top_set_pin(1, 2); /* SDA2 on GPIO 10 */ - - /* UART pins */ -#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) - top_set_pin(141, 1); - top_set_pin(143, 1); -#endif -#if defined(CONFIG_VCT_PLATINUMAVC) - top_set_pin(107, 1); - top_set_pin(109, 1); -#endif -} diff --git a/board/micronas/vct/vct.c b/board/micronas/vct/vct.c deleted file mode 100644 index e73d16db3ea..00000000000 --- a/board/micronas/vct/vct.c +++ /dev/null @@ -1,119 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Copyright (C) 2006 Micronas GmbH - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <netdev.h> -#include <asm/mipsregs.h> -#include "vct.h" - -#if defined(CONFIG_VCT_PREMIUM) -#define BOARD_NAME "PremiumD" -#elif defined(CONFIG_VCT_PLATINUM) -#define BOARD_NAME "PlatinumD" -#elif defined(CONFIG_VCT_PLATINUMAVC) -#define BOARD_NAME "PlatinumAVC" -#else -#error "vct: No board variant defined!" -#endif - -#if defined(CONFIG_VCT_ONENAND) -#define BOARD_NAME_ADD " OneNAND" -#else -#define BOARD_NAME_ADD " NOR" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* - * First initialize the PIN mulitplexing - */ - vct_pin_mux_initialize(); - - /* - * Init the EBI very early so that FLASH can be accessed - */ - ebi_initialize(); - - return 0; -} - -void _machine_restart(void) -{ - reg_write(DCGU_EN_WDT_RESET(DCGU_BASE), DCGU_MAGIC_WDT); - reg_write(WDT_TORR(WDT_BASE), 0x00); - reg_write(WDT_CR(WDT_BASE), 0x1D); - - /* - * Now wait for the watchdog to trigger the reset - */ - udelay(1000000); -} - -/* - * SDRAM is already configured by the bootstrap code, only return the - * auto-detected size here - */ -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_MBYTES_SDRAM << 20); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = env_get_f("serial#", buf, sizeof(buf)); - u32 config0 = read_c0_prid(); - - if ((config0 & 0xff0000) == PRID_COMP_LEGACY - && (config0 & 0xff00) == PRID_IMP_LX4280) { - puts("Board: MDED \n"); - printf("CPU: LX4280 id: 0x%02x, rev: 0x%02x\n", - (config0 >> 8) & 0xFF, config0 & 0xFF); - } else if ((config0 & 0xff0000) == PRID_COMP_MIPS - && (config0 & 0xff00) == PRID_IMP_VGC) { - u32 jedec_id = *((u32 *) 0xBEBC71A0); - if ((((jedec_id) >> 12) & 0xFF) == 0x40) { - puts("Board: VGCA \n"); - } else if ((((jedec_id) >> 12) & 0xFF) == 0x48 - || (((jedec_id) >> 12) & 0xFF) == 0x49) { - puts("Board: VGCB \n"); - } - printf("CPU: MIPS 4K id: 0x%02x, rev: 0x%02x\n", - (config0 >> 8) & 0xFF, config0 & 0xFF); - } else if (config0 == 0x19378) { - printf("CPU: MIPS 24K id: 0x%02x, rev: 0x%02x\n", - (config0 >> 8) & 0xFF, config0 & 0xFF); - } else { - printf("Unsupported cpu %d, proc_id=0x%x\n", config0 >> 24, - config0); - } - - printf("Board: Micronas VCT " BOARD_NAME BOARD_NAME_ADD); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/micronas/vct/vct.h b/board/micronas/vct/vct.h deleted file mode 100644 index 22b35b2c5b0..00000000000 --- a/board/micronas/vct/vct.h +++ /dev/null @@ -1,92 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Copyright (C) 2006 Micronas GmbH - */ - -#include <asm/io.h> - -#include "bcu.h" -#include "dcgu.h" -#include "ebi.h" -#include "scc.h" - -#ifdef CONFIG_VCT_PREMIUM -/* Global start address of all memory mapped registers */ -#define REG_GLOBAL_START_ADDR 0xbf800000 -#define TOP_BASE 0x000c8000 - -#include "vcth/reg_ebi.h" -#include "vcth/reg_dcgu.h" -#include "vcth/reg_wdt.h" -#include "vcth/reg_gpio.h" -#include "vcth/reg_fwsram.h" -#include "vcth/reg_scc.h" -#include "vcth/reg_usbh.h" -#endif - -#ifdef CONFIG_VCT_PLATINUM -/* Global start address of all memory mapped registers */ -#define REG_GLOBAL_START_ADDR 0xbf800000 -#define TOP_BASE 0x000c8000 - -#include "vcth2/reg_ebi.h" -#include "vcth/reg_dcgu.h" -#include "vcth/reg_wdt.h" -#include "vcth/reg_gpio.h" -#include "vcth/reg_fwsram.h" -#include "vcth/reg_scc.h" -#include "vcth/reg_usbh.h" -#endif - -#ifdef CONFIG_VCT_PLATINUMAVC -/* Global start address of all memory mapped registers */ -#define REG_GLOBAL_START_ADDR 0xbdc00000 -#define TOP_BASE 0x00050000 - -#include "vctv/reg_ebi.h" -#include "vctv/reg_dcgu.h" -#include "vctv/reg_wdt.h" -#include "vctv/reg_gpio.h" -#endif - -#ifndef _VCT_H -#define _VCT_H - -/* - * Defines - */ -#define PRID_COMP_LEGACY 0x000000 -#define PRID_COMP_MIPS 0x010000 -#define PRID_IMP_LX4280 0xc200 -#define PRID_IMP_VGC 0x9000 - -/* - * Prototypes - */ -int ebi_initialize(void); -int ebi_init_nor_flash(void); -int ebi_init_onenand(void); -int ebi_init_smc911x(void); -u32 smc911x_reg_read(u32 addr); -void smc911x_reg_write(u32 addr, u32 data); -int top_set_pin(int pin, int func); -void vct_pin_mux_initialize(void); - -/* - * static inlines - */ -static inline void reg_write(u32 addr, u32 data) -{ - void *reg = (void *)(addr + REG_GLOBAL_START_ADDR); - __raw_writel(data, reg); -} - -static inline u32 reg_read(u32 addr) -{ - const void *reg = (const void *)(addr + REG_GLOBAL_START_ADDR); - return __raw_readl(reg); -} - -#endif /* _VCT_H */ diff --git a/board/micronas/vct/vcth/reg_dcgu.h b/board/micronas/vct/vcth/reg_dcgu.h deleted file mode 100644 index a598ad04bf7..00000000000 --- a/board/micronas/vct/vcth/reg_dcgu.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008-2009 Stefan Roese <sr@denx.de>, DENX Software Engineering - */ - -#define DCGU_BASE 0x00084000 - -/* Relative offsets of the register adresses */ - -#define DCGU_CLK_EN1_OFFS 0x00000010 -#define DCGU_CLK_EN1(base) ((base) + DCGU_CLK_EN1_OFFS) -#define DCGU_CLK_EN2_OFFS 0x00000014 -#define DCGU_CLK_EN2(base) ((base) + DCGU_CLK_EN2_OFFS) -#define DCGU_RESET_UNIT1_OFFS 0x00000018 -#define DCGU_RESET_UNIT1(base) ((base) + DCGU_RESET_UNIT1_OFFS) -#define DCGU_USBPHY_STAT_OFFS 0x00000054 -#define DCGU_USBPHY_STAT(base) ((base) + DCGU_USBPHY_STAT_OFFS) -#define DCGU_EN_WDT_RESET_OFFS 0x00000064 -#define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS) - -/* The magic value to write in order to activate the WDT */ -#define DCGU_MAGIC_WDT 0x1909 diff --git a/board/micronas/vct/vcth/reg_ebi.h b/board/micronas/vct/vcth/reg_ebi.h deleted file mode 100644 index a2a36489dc8..00000000000 --- a/board/micronas/vct/vcth/reg_ebi.h +++ /dev/null @@ -1,228 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Copyright (C) 2006 Micronas GmbH - */ - -#ifndef _REG_EBI_PREMIUM_H_ -#define _REG_EBI_PREMIUM_H_ - -#define EBI_BASE 0x00000000 - -/* Relative offsets of the register adresses */ - -#define EBI_CPU_IO_ACCS_OFFS 0x00000000 -#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) -#define EBI_IO_ACCS_DATA_OFFS 0x00000004 -#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) -#define EBI_CTRL_OFFS 0x00000008 -#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) -#define EBI_IRQ_MASK_OFFS 0x00000010 -#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) -#define EBI_TAG1_SYS_ID_OFFS 0x00000030 -#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) -#define EBI_TAG2_SYS_ID_OFFS 0x00000040 -#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) -#define EBI_TAG3_SYS_ID_OFFS 0x00000050 -#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) -#define EBI_TAG4_SYS_ID_OFFS 0x00000060 -#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) -#define EBI_GEN_DMA_CTRL_OFFS 0x00000070 -#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) -#define EBI_STATUS_OFFS 0x00000080 -#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) -#define EBI_STATUS_DMA_CNT_OFFS 0x00000084 -#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS) -#define EBI_SIG_LEVEL_OFFS 0x00000088 -#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS) -#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C -#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS) -#define EBI_EXT_ADDR_OFFS 0x000000A0 -#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) -#define EBI_IRQ_STATUS_OFFS 0x000000B0 -#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS) -#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100 -#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS) -#define EBI_DEV1_EXT_ACC_OFFS 0x00000104 -#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS) -#define EBI_DEV1_CONFIG1_OFFS 0x00000108 -#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS) -#define EBI_DEV1_CONFIG2_OFFS 0x0000010C -#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS) -#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110 -#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS) -#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114 -#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS) -#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118 -#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS) -#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C -#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS) -#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124 -#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS) -#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128 -#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS) -#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C -#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS) -#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130 -#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS) -#define EBI_DEV1_TIM_EXT_OFFS 0x00000134 -#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS) -#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138 -#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS) -#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C -#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS) -#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140 -#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS) -#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144 -#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS) -#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150 -#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS) -#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200 -#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS) -#define EBI_DEV2_EXT_ACC_OFFS 0x00000204 -#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS) -#define EBI_DEV2_CONFIG1_OFFS 0x00000208 -#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS) -#define EBI_DEV2_CONFIG2_OFFS 0x0000020C -#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS) -#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210 -#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS) -#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214 -#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS) -#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218 -#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS) -#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C -#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS) -#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224 -#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS) -#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228 -#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS) -#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C -#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS) -#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230 -#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS) -#define EBI_DEV2_TIM_EXT_OFFS 0x00000234 -#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS) -#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238 -#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS) -#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C -#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS) -#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240 -#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS) -#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244 -#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS) -#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250 -#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS) -#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300 -#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS) -#define EBI_DEV3_EXT_ACC_OFFS 0x00000304 -#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS) -#define EBI_DEV3_CONFIG1_OFFS 0x00000308 -#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS) -#define EBI_DEV3_CONFIG2_OFFS 0x0000030C -#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS) -#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310 -#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS) -#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314 -#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS) -#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318 -#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS) -#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C -#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS) -#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324 -#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS) -#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328 -#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS) -#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C -#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS) -#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330 -#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS) -#define EBI_DEV3_TIM_EXT_OFFS 0x00000334 -#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS) -#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338 -#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS) -#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C -#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS) -#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340 -#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS) -#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344 -#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS) -#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350 -#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS) -#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400 -#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS) -#define EBI_DEV4_EXT_ACC_OFFS 0x00000404 -#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS) -#define EBI_DEV4_CONFIG1_OFFS 0x00000408 -#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS) -#define EBI_DEV4_CONFIG2_OFFS 0x0000040C -#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS) -#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410 -#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS) -#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414 -#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS) -#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418 -#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS) -#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C -#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS) -#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424 -#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS) -#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428 -#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS) -#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C -#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS) -#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430 -#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS) -#define EBI_DEV4_TIM_EXT_OFFS 0x00000434 -#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS) -#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438 -#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS) -#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C -#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS) -#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440 -#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS) -#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444 -#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS) -#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450 -#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS) -#define EBI_CNT_FL_PROGR_OFFS 0x00000904 -#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS) -#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C -#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS) -#define EBI_CNT_WAIT_RDY_OFFS 0x00000914 -#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS) -#define EBI_CNT_ACK_OFFS 0x00000918 -#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS) -#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00 -#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS) -#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04 -#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS) -#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08 -#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS) -#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10 -#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS) -#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14 -#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS) -#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18 -#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS) -#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20 -#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS) -#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24 -#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS) -#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28 -#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS) -#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30 -#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS) -#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34 -#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS) -#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38 -#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS) -#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40 -#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS) -#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44 -#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS) -#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48 -#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS) - -#endif diff --git a/board/micronas/vct/vcth/reg_fwsram.h b/board/micronas/vct/vcth/reg_fwsram.h deleted file mode 100644 index 6dafa1b3049..00000000000 --- a/board/micronas/vct/vcth/reg_fwsram.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Copyright (C) 2006 Micronas GmbH - */ - -/* - * Premium & Platinum register addresses/definitions seem to be - * identical, so we only need to use one file for both platforms. - */ - -#ifndef _REG_FWSRAM_H_ -#define _REG_FWSRAM_H_ - -#define FWSRAM_BASE 0x00030000 - -/* Relative offsets of the register adresses */ - -#define FWSRAM_SR_ADDR_OFFSET_OFFS 0x00002000 -#define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS) -#define FWSRAM_TOP_BOOT_LOG_OFFS 0x00002004 -#define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS) -#define FWSRAM_TOP_ROM_KBIST_OFFS 0x00002008 -#define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS) -#define FWSRAM_TOP_CID1_H_OFFS 0x0000200C -#define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS) -#define FWSRAM_TOP_CID1_L_OFFS 0x00002010 -#define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS) -#define FWSRAM_TOP_CID2_H_OFFS 0x00002014 -#define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS) -#define FWSRAM_TOP_CID2_L_OFFS 0x00002018 -#define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS) -#define FWSRAM_TOP_TDO_CFG_OFFS 0x0000203C -#define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS) -#define FWSRAM_TOP_GPIO2_0_CFG_OFFS 0x00002040 -#define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS) -#define FWSRAM_TOP_GPIO2_1_CFG_OFFS 0x00002044 -#define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS) -#define FWSRAM_TOP_GPIO2_2_CFG_OFFS 0x00002048 -#define FWSRAM_TOP_GPIO2_2_CFG(base) ((base) + FWSRAM_TOP_GPIO2_2_CFG_OFFS) -#define FWSRAM_TOP_GPIO2_3_CFG_OFFS 0x0000204C -#define FWSRAM_TOP_GPIO2_3_CFG(base) ((base) + FWSRAM_TOP_GPIO2_3_CFG_OFFS) -#define FWSRAM_TOP_GPIO2_4_CFG_OFFS 0x00002050 -#define FWSRAM_TOP_GPIO2_4_CFG(base) ((base) + FWSRAM_TOP_GPIO2_4_CFG_OFFS) -#define FWSRAM_TOP_GPIO2_5_CFG_OFFS 0x00002054 -#define FWSRAM_TOP_GPIO2_5_CFG(base) ((base) + FWSRAM_TOP_GPIO2_5_CFG_OFFS) -#define FWSRAM_TOP_GPIO2_6_CFG_OFFS 0x00002058 -#define FWSRAM_TOP_GPIO2_6_CFG(base) ((base) + FWSRAM_TOP_GPIO2_6_CFG_OFFS) -#define FWSRAM_TOP_GPIO2_7_CFG_OFFS 0x0000205C -#define FWSRAM_TOP_GPIO2_7_CFG(base) ((base) + FWSRAM_TOP_GPIO2_7_CFG_OFFS) -#define FWSRAM_TOP_SCL_CFG_OFFS 0x00002060 -#define FWSRAM_TOP_SCL_CFG(base) ((base) + FWSRAM_TOP_SCL_CFG_OFFS) -#define FWSRAM_TOP_SDA_CFG_OFFS 0x00002064 -#define FWSRAM_TOP_SDA_CFG(base) ((base) + FWSRAM_TOP_SDA_CFG_OFFS) -#define FWSRAM_NO_MCM_FLASH_OFFS 0x00002068 -#define FWSRAM_NO_MCM_FLASH(base) ((base) + FWSRAM_NO_MCM_FLASH_OFFS) - -#endif diff --git a/board/micronas/vct/vcth/reg_gpio.h b/board/micronas/vct/vcth/reg_gpio.h deleted file mode 100644 index 0660200ffa5..00000000000 --- a/board/micronas/vct/vcth/reg_gpio.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - */ - -#define GPIO1_BASE 0x00088000 -#define GPIO2_BASE 0x0008c000 - -/* Instances */ -#define GPIO_INSTANCES 2 - -/* Relative offsets of the register adresses */ -#define GPIO_SWPORTA_DR_OFFS 0x00000000 -#define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS) -#define GPIO_SWPORTA_DDR_OFFS 0x00000004 -#define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS) -#define GPIO_EXT_PORTA_OFFS 0x00000050 -#define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS) diff --git a/board/micronas/vct/vcth/reg_scc.h b/board/micronas/vct/vcth/reg_scc.h deleted file mode 100644 index 928ad724342..00000000000 --- a/board/micronas/vct/vcth/reg_scc.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Copyright (C) 2006 Micronas GmbH - */ - -#ifndef _REG_SCC_PREMIUM_H_ -#define _REG_SCC_PREMIUM_H_ - -#define SCC0_BASE 0x00110000 -#define SCC1_BASE 0x00110080 -#define SCC2_BASE 0x00110100 -#define SCC3_BASE 0x00110180 -#define SCC4_BASE 0x00110200 -#define SCC5_BASE 0x00110280 -#define SCC6_BASE 0x00110300 -#define SCC7_BASE 0x00110380 -#define SCC8_BASE 0x00110400 -#define SCC9_BASE 0x00110480 -#define SCC10_BASE 0x00110500 -#define SCC11_BASE 0x00110580 -#define SCC12_BASE 0x00110600 -#define SCC13_BASE 0x00110680 -#define SCC14_BASE 0x00110700 -#define SCC15_BASE 0x00110780 -#define SCC16_BASE 0x00110800 -#define SCC17_BASE 0x00110880 -#define SCC18_BASE 0x00110900 -#define SCC19_BASE 0x00110980 -#define SCC20_BASE 0x00110a00 -#define SCC21_BASE 0x00110a80 -#define SCC22_BASE 0x00110b00 -#define SCC23_BASE 0x00110b80 -#define SCC24_BASE 0x00110c00 -#define SCC25_BASE 0x00110c80 -#define SCC26_BASE 0x00110d00 -#define SCC27_BASE 0x00110d80 -#define SCC28_BASE 0x00110e00 -#define SCC29_BASE 0x00110e80 -#define SCC30_BASE 0x00110f00 -#define SCC31_BASE 0x00110f80 -#define SCC32_BASE 0x00111000 -#define SCC33_BASE 0x00111080 -#define SCC34_BASE 0x00111100 -#define SCC35_BASE 0x00111180 -#define SCC36_BASE 0x00111200 -#define SCC37_BASE 0x00111280 -#define SCC38_BASE 0x00111300 -#define SCC39_BASE 0x00111380 -#define SCC40_BASE 0x00111400 - -/* Relative offsets of the register adresses */ - -#define SCC_ENABLE_OFFS 0x00000000 -#define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS) -#define SCC_RESET_OFFS 0x00000004 -#define SCC_RESET(base) ((base) + SCC_RESET_OFFS) -#define SCC_VCID_OFFS 0x00000008 -#define SCC_VCID(base) ((base) + SCC_VCID_OFFS) -#define SCC_MCI_CFG_OFFS 0x0000000C -#define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS) -#define SCC_PACKET_CFG1_OFFS 0x00000010 -#define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS) -#define SCC_PACKET_CFG2_OFFS 0x00000014 -#define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS) -#define SCC_PACKET_CFG3_OFFS 0x00000018 -#define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS) -#define SCC_DMA_CFG_OFFS 0x0000001C -#define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS) -#define SCC_CMD_OFFS 0x00000020 -#define SCC_CMD(base) ((base) + SCC_CMD_OFFS) -#define SCC_PRIO_OFFS 0x00000024 -#define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS) -#define SCC_DEBUG_OFFS 0x00000028 -#define SCC_DEBUG(base) ((base) + SCC_DEBUG_OFFS) -#define SCC_STATUS_OFFS 0x0000002C -#define SCC_STATUS(base) ((base) + SCC_STATUS_OFFS) -#define SCC_IMR_OFFS 0x00000030 -#define SCC_IMR(base) ((base) + SCC_IMR_OFFS) -#define SCC_ISR_OFFS 0x00000034 -#define SCC_ISR(base) ((base) + SCC_ISR_OFFS) -#define SCC_DMA_OFFSET_OFFS 0x00000038 -#define SCC_DMA_OFFSET(base) ((base) + SCC_DMA_OFFSET_OFFS) -#define SCC_RS_CTLSTS_OFFS 0x0000003C -#define SCC_RS_CTLSTS(base) ((base) + SCC_RS_CTLSTS_OFFS) - -#endif diff --git a/board/micronas/vct/vcth/reg_usbh.h b/board/micronas/vct/vcth/reg_usbh.h deleted file mode 100644 index 57f94025e70..00000000000 --- a/board/micronas/vct/vcth/reg_usbh.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering - */ - -#define USBH_BASE 0x00080000 - -/* Relative offsets of the register adresses */ - -#define USBH_CAPLENGTH_OFFS 0x00000100 -#define USBH_CAPLENGTH(base) ((base) + USBH_CAPLENGTH_OFFS) -#define USBH_USBCMD_OFFS 0x00000140 -#define USBH_USBCMD(base) ((base) + USBH_USBCMD_OFFS) -#define USBH_BURSTSIZE_OFFS 0x00000160 -#define USBH_BURSTSIZE(base) ((base) + USBH_BURSTSIZE_OFFS) -#define USBH_USBMODE_OFFS 0x000001A8 -#define USBH_USBMODE(base) ((base) + USBH_USBMODE_OFFS) -#define USBH_USBHMISC_OFFS 0x00000200 -#define USBH_USBHMISC(base) ((base) + USBH_USBHMISC_OFFS) diff --git a/board/micronas/vct/vcth/reg_wdt.h b/board/micronas/vct/vcth/reg_wdt.h deleted file mode 100644 index 84572a1c77a..00000000000 --- a/board/micronas/vct/vcth/reg_wdt.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - */ - -#define WDT_BASE 0x000b0000 -#define WDT_CR_OFFS 0x00000000 -#define WDT_CR(base) ((base) + WDT_CR_OFFS) -#define WDT_TORR_OFFS 0x00000004 -#define WDT_TORR(base) ((base) + WDT_TORR_OFFS) diff --git a/board/micronas/vct/vcth2/reg_ebi.h b/board/micronas/vct/vcth2/reg_ebi.h deleted file mode 100644 index ed9368db8b1..00000000000 --- a/board/micronas/vct/vcth2/reg_ebi.h +++ /dev/null @@ -1,276 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Copyright (C) 2006 Micronas GmbH - */ - -#ifndef _REG_EBI_PREMIUM_H_ -#define _REG_EBI_PREMIUM_H_ - -#define EBI_BASE 0x00000000 - -/* Relative offsets of the register adresses */ - -#define EBI_CPU_IO_ACCS_OFFS 0x00000000 -#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) -#define EBI_IO_ACCS_DATA_OFFS 0x00000004 -#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) -#define EBI_CPU_IO_ACCS2_OFFS 0x00000008 -#define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) -#define EBI_IO_ACCS2_DATA_OFFS 0x0000000C -#define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) -#define EBI_CTRL_OFFS 0x00000010 -#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) -#define EBI_IRQ_MASK_OFFS 0x00000018 -#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) -#define EBI_IRQ_MASK2_OFFS 0x0000001C -#define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) -#define EBI_TAG1_SYS_ID_OFFS 0x00000030 -#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) -#define EBI_TAG2_SYS_ID_OFFS 0x00000040 -#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) -#define EBI_TAG3_SYS_ID_OFFS 0x00000050 -#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) -#define EBI_TAG4_SYS_ID_OFFS 0x00000060 -#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) -#define EBI_GEN_DMA_CTRL_OFFS 0x00000070 -#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) -#define EBI_STATUS_OFFS 0x00000080 -#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) -#define EBI_STATUS_DMA_CNT_OFFS 0x00000084 -#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS) -#define EBI_SIG_LEVEL_OFFS 0x00000088 -#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS) -#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C -#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS) -#define EBI_CRC_GEN_OFFS 0x00000090 -#define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS) -#define EBI_EXT_ADDR_OFFS 0x000000A0 -#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) -#define EBI_IRQ_STATUS_OFFS 0x000000B0 -#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS) -#define EBI_IRQ_STATUS2_OFFS 0x000000B4 -#define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS) -#define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0 -#define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS) -#define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4 -#define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS) -#define EBI_ECC0_OFFS 0x000000D0 -#define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS) -#define EBI_ECC1_OFFS 0x000000D4 -#define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS) -#define EBI_ECC2_OFFS 0x000000D8 -#define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS) -#define EBI_ECC3_OFFS 0x000000DC -#define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS) -#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100 -#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS) -#define EBI_DEV1_EXT_ACC_OFFS 0x00000104 -#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS) -#define EBI_DEV1_CONFIG1_OFFS 0x00000108 -#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS) -#define EBI_DEV1_CONFIG2_OFFS 0x0000010C -#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS) -#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110 -#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS) -#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114 -#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS) -#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118 -#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS) -#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C -#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS) -#define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120 -#define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS) -#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124 -#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS) -#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128 -#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS) -#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C -#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS) -#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130 -#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS) -#define EBI_DEV1_TIM_EXT_OFFS 0x00000134 -#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS) -#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138 -#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS) -#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C -#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS) -#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140 -#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS) -#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144 -#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS) -#define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148 -#define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS) -#define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C -#define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS) -#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150 -#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS) -#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200 -#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS) -#define EBI_DEV2_EXT_ACC_OFFS 0x00000204 -#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS) -#define EBI_DEV2_CONFIG1_OFFS 0x00000208 -#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS) -#define EBI_DEV2_CONFIG2_OFFS 0x0000020C -#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS) -#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210 -#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS) -#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214 -#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS) -#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218 -#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS) -#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C -#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS) -#define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220 -#define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS) -#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224 -#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS) -#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228 -#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS) -#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C -#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS) -#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230 -#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS) -#define EBI_DEV2_TIM_EXT_OFFS 0x00000234 -#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS) -#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238 -#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS) -#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C -#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS) -#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240 -#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS) -#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244 -#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS) -#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248 -#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS) -#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C -#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS) -#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250 -#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS) -#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300 -#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS) -#define EBI_DEV3_EXT_ACC_OFFS 0x00000304 -#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS) -#define EBI_DEV3_CONFIG1_OFFS 0x00000308 -#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS) -#define EBI_DEV3_CONFIG2_OFFS 0x0000030C -#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS) -#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310 -#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS) -#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314 -#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS) -#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318 -#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS) -#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C -#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS) -#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320 -#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS) -#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324 -#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS) -#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328 -#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS) -#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C -#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS) -#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330 -#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS) -#define EBI_DEV3_TIM_EXT_OFFS 0x00000334 -#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS) -#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338 -#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS) -#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C -#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS) -#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340 -#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS) -#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344 -#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS) -#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348 -#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS) -#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C -#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS) -#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350 -#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS) -#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400 -#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS) -#define EBI_DEV4_EXT_ACC_OFFS 0x00000404 -#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS) -#define EBI_DEV4_CONFIG1_OFFS 0x00000408 -#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS) -#define EBI_DEV4_CONFIG2_OFFS 0x0000040C -#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS) -#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410 -#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS) -#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414 -#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS) -#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418 -#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS) -#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C -#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS) -#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420 -#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS) -#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424 -#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS) -#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428 -#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS) -#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C -#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS) -#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430 -#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS) -#define EBI_DEV4_TIM_EXT_OFFS 0x00000434 -#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS) -#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438 -#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS) -#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C -#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS) -#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440 -#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS) -#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444 -#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS) -#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448 -#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS) -#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C -#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS) -#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450 -#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS) -#define EBI_INTERLEAVE_CNT_OFFS 0x00000900 -#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS) -#define EBI_CNT_FL_PROGR_OFFS 0x00000904 -#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS) -#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C -#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS) -#define EBI_CNT_WAIT_RDY_OFFS 0x00000914 -#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS) -#define EBI_CNT_ACK_OFFS 0x00000918 -#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS) -#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00 -#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS) -#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04 -#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS) -#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08 -#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS) -#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10 -#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS) -#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14 -#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS) -#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18 -#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS) -#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20 -#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS) -#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24 -#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS) -#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28 -#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS) -#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30 -#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS) -#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34 -#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS) -#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38 -#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS) -#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40 -#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS) -#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44 -#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS) -#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48 -#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS) - -#endif diff --git a/board/micronas/vct/vctv/reg_dcgu.h b/board/micronas/vct/vctv/reg_dcgu.h deleted file mode 100644 index 9e5c6fd64fb..00000000000 --- a/board/micronas/vct/vctv/reg_dcgu.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - */ - -#define DCGU_BASE 0x0004c000 -#define DCGU_EN_WDT_RESET_OFFS 0x000000FC -#define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS) - -/* The magic value to write in order to activate the WDT */ -#define DCGU_MAGIC_WDT 0x1909 diff --git a/board/micronas/vct/vctv/reg_ebi.h b/board/micronas/vct/vctv/reg_ebi.h deleted file mode 100644 index d9b4770a17d..00000000000 --- a/board/micronas/vct/vctv/reg_ebi.h +++ /dev/null @@ -1,276 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - * - * Copyright (C) 2006 Micronas GmbH - */ - -#ifndef _REG_EBI_PLATINUMAVC_H_ -#define _REG_EBI_PLATINUMAVC_H_ - -#define EBI_BASE 0x00014000 - -/* Relative offsets of the register adresses */ - -#define EBI_CPU_IO_ACCS_OFFS 0x00000000 -#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) -#define EBI_IO_ACCS_DATA_OFFS 0x00000004 -#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) -#define EBI_CPU_IO_ACCS2_OFFS 0x00000008 -#define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) -#define EBI_IO_ACCS2_DATA_OFFS 0x0000000C -#define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) -#define EBI_CTRL_OFFS 0x00000010 -#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) -#define EBI_IRQ_MASK_OFFS 0x00000018 -#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) -#define EBI_IRQ_MASK2_OFFS 0x0000001C -#define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) -#define EBI_TAG1_SYS_ID_OFFS 0x00000030 -#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) -#define EBI_TAG2_SYS_ID_OFFS 0x00000040 -#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) -#define EBI_TAG3_SYS_ID_OFFS 0x00000050 -#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) -#define EBI_TAG4_SYS_ID_OFFS 0x00000060 -#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) -#define EBI_GEN_DMA_CTRL_OFFS 0x00000070 -#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) -#define EBI_STATUS_OFFS 0x00000080 -#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) -#define EBI_STATUS_DMA_CNT_OFFS 0x00000084 -#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS) -#define EBI_SIG_LEVEL_OFFS 0x00000088 -#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS) -#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C -#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS) -#define EBI_CRC_GEN_OFFS 0x00000090 -#define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS) -#define EBI_EXT_ADDR_OFFS 0x000000A0 -#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) -#define EBI_IRQ_STATUS_OFFS 0x000000B0 -#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS) -#define EBI_IRQ_STATUS2_OFFS 0x000000B4 -#define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS) -#define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0 -#define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS) -#define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4 -#define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS) -#define EBI_ECC0_OFFS 0x000000D0 -#define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS) -#define EBI_ECC1_OFFS 0x000000D4 -#define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS) -#define EBI_ECC2_OFFS 0x000000D8 -#define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS) -#define EBI_ECC3_OFFS 0x000000DC -#define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS) -#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100 -#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS) -#define EBI_DEV1_EXT_ACC_OFFS 0x00000104 -#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS) -#define EBI_DEV1_CONFIG1_OFFS 0x00000108 -#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS) -#define EBI_DEV1_CONFIG2_OFFS 0x0000010C -#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS) -#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110 -#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS) -#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114 -#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS) -#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118 -#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS) -#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C -#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS) -#define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120 -#define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS) -#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124 -#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS) -#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128 -#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS) -#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C -#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS) -#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130 -#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS) -#define EBI_DEV1_TIM_EXT_OFFS 0x00000134 -#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS) -#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138 -#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS) -#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C -#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS) -#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140 -#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS) -#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144 -#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS) -#define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148 -#define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS) -#define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C -#define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS) -#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150 -#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS) -#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200 -#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS) -#define EBI_DEV2_EXT_ACC_OFFS 0x00000204 -#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS) -#define EBI_DEV2_CONFIG1_OFFS 0x00000208 -#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS) -#define EBI_DEV2_CONFIG2_OFFS 0x0000020C -#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS) -#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210 -#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS) -#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214 -#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS) -#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218 -#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS) -#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C -#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS) -#define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220 -#define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS) -#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224 -#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS) -#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228 -#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS) -#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C -#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS) -#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230 -#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS) -#define EBI_DEV2_TIM_EXT_OFFS 0x00000234 -#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS) -#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238 -#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS) -#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C -#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS) -#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240 -#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS) -#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244 -#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS) -#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248 -#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS) -#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C -#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS) -#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250 -#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS) -#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300 -#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS) -#define EBI_DEV3_EXT_ACC_OFFS 0x00000304 -#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS) -#define EBI_DEV3_CONFIG1_OFFS 0x00000308 -#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS) -#define EBI_DEV3_CONFIG2_OFFS 0x0000030C -#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS) -#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310 -#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS) -#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314 -#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS) -#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318 -#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS) -#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C -#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS) -#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320 -#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS) -#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324 -#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS) -#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328 -#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS) -#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C -#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS) -#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330 -#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS) -#define EBI_DEV3_TIM_EXT_OFFS 0x00000334 -#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS) -#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338 -#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS) -#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C -#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS) -#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340 -#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS) -#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344 -#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS) -#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348 -#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS) -#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C -#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS) -#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350 -#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS) -#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400 -#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS) -#define EBI_DEV4_EXT_ACC_OFFS 0x00000404 -#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS) -#define EBI_DEV4_CONFIG1_OFFS 0x00000408 -#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS) -#define EBI_DEV4_CONFIG2_OFFS 0x0000040C -#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS) -#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410 -#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS) -#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414 -#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS) -#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418 -#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS) -#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C -#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS) -#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420 -#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS) -#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424 -#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS) -#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428 -#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS) -#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C -#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS) -#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430 -#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS) -#define EBI_DEV4_TIM_EXT_OFFS 0x00000434 -#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS) -#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438 -#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS) -#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C -#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS) -#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440 -#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS) -#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444 -#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS) -#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448 -#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS) -#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C -#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS) -#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450 -#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS) -#define EBI_INTERLEAVE_CNT_OFFS 0x00000900 -#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS) -#define EBI_CNT_FL_PROGR_OFFS 0x00000904 -#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS) -#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C -#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS) -#define EBI_CNT_WAIT_RDY_OFFS 0x00000914 -#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS) -#define EBI_CNT_ACK_OFFS 0x00000918 -#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS) -#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00 -#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS) -#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04 -#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS) -#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08 -#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS) -#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10 -#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS) -#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14 -#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS) -#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18 -#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS) -#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20 -#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS) -#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24 -#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS) -#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28 -#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS) -#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30 -#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS) -#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34 -#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS) -#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38 -#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS) -#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40 -#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS) -#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44 -#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS) -#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48 -#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS) - -#endif diff --git a/board/micronas/vct/vctv/reg_gpio.h b/board/micronas/vct/vctv/reg_gpio.h deleted file mode 100644 index b1859a47c4d..00000000000 --- a/board/micronas/vct/vctv/reg_gpio.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - */ - -#define GPIO1_BASE 0x00044000 -#define GPIO2_BASE 0x00048000 - -/* Instances */ -#define GPIO_INSTANCES 2 - -/* Relative offsets of the register adresses */ -#define GPIO_SWPORTA_DR_OFFS 0x00000000 -#define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS) -#define GPIO_SWPORTA_DDR_OFFS 0x00000004 -#define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS) -#define GPIO_EXT_PORTA_OFFS 0x00000050 -#define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS) diff --git a/board/micronas/vct/vctv/reg_wdt.h b/board/micronas/vct/vctv/reg_wdt.h deleted file mode 100644 index 2bad0752e8f..00000000000 --- a/board/micronas/vct/vctv/reg_wdt.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - */ - -#define WDT_BASE 0x00040000 -#define WDT_CR_OFFS 0x00000000 -#define WDT_CR(base) ((base) + WDT_CR_OFFS) -#define WDT_TORR_OFFS 0x00000004 -#define WDT_TORR(base) ((base) + WDT_TORR_OFFS) diff --git a/board/st/stm32mp1/README b/board/st/stm32mp1/README index c807e0842eb..f2069bcefaf 100644 --- a/board/st/stm32mp1/README +++ b/board/st/stm32mp1/README @@ -390,3 +390,114 @@ B/ Automatically by using FIT feature and generic DISTRO bootcmd the correct configuration => stm32mp157c-ev1-m4 => stm32mp157c-dk2-m4 + +11. DFU support +=============== + +The DFU is supported on ST board. +The env variable dfu_alt_info is automatically build, and all +the memory present on the ST boards are exported. + +The mode is started by + +STM32MP> dfu 0 + +On EV1 board: + +STM32MP> dfu 0 list + +DFU alt settings list: +dev: RAM alt: 0 name: uImage layout: RAM_ADDR +dev: RAM alt: 1 name: devicetree.dtb layout: RAM_ADDR +dev: RAM alt: 2 name: uramdisk.image.gz layout: RAM_ADDR +dev: eMMC alt: 3 name: sdcard_fsbl1 layout: RAW_ADDR +dev: eMMC alt: 4 name: sdcard_fsbl2 layout: RAW_ADDR +dev: eMMC alt: 5 name: sdcard_ssbl layout: RAW_ADDR +dev: eMMC alt: 6 name: sdcard_bootfs layout: RAW_ADDR +dev: eMMC alt: 7 name: sdcard_vendorfs layout: RAW_ADDR +dev: eMMC alt: 8 name: sdcard_rootfs layout: RAW_ADDR +dev: eMMC alt: 9 name: sdcard_userfs layout: RAW_ADDR +dev: eMMC alt: 10 name: emmc_fsbl1 layout: RAW_ADDR +dev: eMMC alt: 11 name: emmc_fsbl2 layout: RAW_ADDR +dev: eMMC alt: 12 name: emmc_ssbl layout: RAW_ADDR +dev: eMMC alt: 13 name: emmc_bootfs layout: RAW_ADDR +dev: eMMC alt: 14 name: emmc_vendorfs layout: RAW_ADDR +dev: eMMC alt: 15 name: emmc_rootfs layout: RAW_ADDR +dev: eMMC alt: 16 name: emmc_userfs layout: RAW_ADDR +dev: MTD alt: 17 name: nor_fsbl1 layout: RAW_ADDR +dev: MTD alt: 18 name: nor_fsbl2 layout: RAW_ADDR +dev: MTD alt: 19 name: nor_ssbl layout: RAW_ADDR +dev: MTD alt: 20 name: nor_env layout: RAW_ADDR +dev: MTD alt: 21 name: nand_fsbl layout: RAW_ADDR +dev: MTD alt: 22 name: nand_ssbl1 layout: RAW_ADDR +dev: MTD alt: 23 name: nand_ssbl2 layout: RAW_ADDR +dev: MTD alt: 24 name: nand_UBI layout: RAW_ADDR +dev: VIRT alt: 25 name: OTP layout: RAW_ADDR +dev: VIRT alt: 26 name: PMIC layout: RAW_ADDR + +All the supported device are exported for dfu-util tool: + +$> dfu-util -l +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=26, name="PMIC", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=25, name="OTP", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=24, name="nand_UBI", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=23, name="nand_ssbl2", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=22, name="nand_ssbl1", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=21, name="nand_fsbl", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=20, name="nor_env", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=19, name="nor_ssbl", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=18, name="nor_fsbl2", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=17, name="nor_fsbl1", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=16, name="emmc_userfs", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=15, name="emmc_rootfs", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=14, name="emmc_vendorfs", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=13, name="emmc_bootfs", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=12, name="emmc_ssbl", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=11, name="emmc_fsbl2", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=10, name="emmc_fsbl1", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=9, name="sdcard_userfs", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=8, name="sdcard_rootfs", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=7, name="sdcard_vendorfs", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=6, name="sdcard_bootfs", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=5, name="sdcard_ssbl", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=4, name="sdcard_fsbl2", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=3, name="sdcard_fsbl1", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=2, name="uramdisk.image.gz", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=1, name="devicetree.dtb", serial="002700333338511934383330" +Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=0, name="uImage", serial="002700333338511934383330" + +You can update the boot device: + +#SDCARD +$> dfu-util -d 0483:5720 -a 3 -D tf-a-stm32mp157c-ev1-trusted.stm32 +$> dfu-util -d 0483:5720 -a 4 -D tf-a-stm32mp157c-ev1-trusted.stm32 +$> dfu-util -d 0483:5720 -a 5 -D u-boot-stm32mp157c-ev1-trusted.img +$> dfu-util -d 0483:5720 -a 6 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4 +$> dfu-util -d 0483:5720 -a 7 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4 +$> dfu-util -d 0483:5720 -a 8 -D st-image-weston-openstlinux-weston-stm32mp1.ext4 +$> dfu-util -d 0483:5720 -a 9 -D st-image-userfs-openstlinux-weston-stm32mp1.ext4 + +#EMMC +$> dfu-util -d 0483:5720 -a 10 -D tf-a-stm32mp157c-ev1-trusted.stm32 +$> dfu-util -d 0483:5720 -a 11 -D tf-a-stm32mp157c-ev1-trusted.stm32 +$> dfu-util -d 0483:5720 -a 12 -D u-boot-stm32mp157c-ev1-trusted.img +$> dfu-util -d 0483:5720 -a 13 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4 +$> dfu-util -d 0483:5720 -a 14 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4 +$> dfu-util -d 0483:5720 -a 15 -D st-image-weston-openstlinux-weston-stm32mp1.ext4 +$> dfu-util -d 0483:5720 -a 16 -D st-image-userfs-openstlinux-weston-stm32mp1.ext4 + +#NOR +$> dfu-util -d 0483:5720 -a 17 -D tf-a-stm32mp157c-ev1-trusted.stm32 +$> dfu-util -d 0483:5720 -a 18 -D tf-a-stm32mp157c-ev1-trusted.stm32 +$> dfu-util -d 0483:5720 -a 19 -D u-boot-stm32mp157c-ev1-trusted.img + +#NAND (UBI partition used for NAND only boot or NOR + NAND boot) +$> dfu-util -d 0483:5720 -a 21 -D tf-a-stm32mp157c-ev1-trusted.stm32 +$> dfu-util -d 0483:5720 -a 22 -D u-boot-stm32mp157c-ev1-trusted.img +$> dfu-util -d 0483:5720 -a 23 -D u-boot-stm32mp157c-ev1-trusted.img +$> dfu-util -d 0483:5720 -a 24 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi + +And you can also dump the OTP and the PMIC NVM with: + +$> dfu-util -d 0483:5720 -a 25 -U otp.bin +$> dfu-util -d 0483:5720 -a 26 -U pmic.bin diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 126af301732..4ed2d888496 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -14,6 +14,7 @@ #include <generic-phy.h> #include <i2c.h> #include <led.h> +#include <memalign.h> #include <misc.h> #include <mtd.h> #include <mtd_node.h> @@ -878,8 +879,9 @@ static void board_get_mtdparts(const char *dev, void board_mtdparts_default(const char **mtdids, const char **mtdparts) { + struct mtd_info *mtd; struct udevice *dev; - static char parts[2 * MTDPARTS_LEN + 1]; + static char parts[3 * MTDPARTS_LEN + 1]; static char ids[MTDIDS_LEN + 1]; static bool mtd_initialized; @@ -892,8 +894,24 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) memset(parts, 0, sizeof(parts)); memset(ids, 0, sizeof(ids)); - if (!uclass_get_device(UCLASS_MTD, 0, &dev)) + /* probe all MTD devices */ + for (uclass_first_device(UCLASS_MTD, &dev); + dev; + uclass_next_device(&dev)) { + pr_debug("mtd device = %s\n", dev->name); + } + + mtd = get_mtd_device_nm("nand0"); + if (!IS_ERR_OR_NULL(mtd)) { board_get_mtdparts("nand0", ids, parts); + put_mtd_device(mtd); + } + + mtd = get_mtd_device_nm("spi-nand0"); + if (!IS_ERR_OR_NULL(mtd)) { + board_get_mtdparts("spi-nand0", ids, parts); + put_mtd_device(mtd); + } if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) board_get_mtdparts("nor0", ids, parts); @@ -920,6 +938,148 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif +#ifdef CONFIG_SET_DFU_ALT_INFO +#define DFU_ALT_BUF_LEN SZ_1K + +static void board_get_alt_info(const char *dev, char *buff) +{ + char var_name[32] = "dfu_alt_info_"; + int ret; + + ALLOC_CACHE_ALIGN_BUFFER(char, tmp_alt, DFU_ALT_BUF_LEN); + + /* name of env variable to read = dfu_alt_info_<dev> */ + strcat(var_name, dev); + ret = env_get_f(var_name, tmp_alt, DFU_ALT_BUF_LEN); + if (ret) { + if (buff[0] != '\0') + strcat(buff, "&"); + strncat(buff, tmp_alt, DFU_ALT_BUF_LEN); + } +} + +void set_dfu_alt_info(char *interface, char *devstr) +{ + struct udevice *dev; + struct mtd_info *mtd; + + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + + if (env_get("dfu_alt_info")) + return; + + memset(buf, 0, sizeof(buf)); + + /* probe all MTD devices */ + mtd_probe_devices(); + + board_get_alt_info("ram", buf); + + if (!uclass_get_device(UCLASS_MMC, 0, &dev)) + board_get_alt_info("mmc0", buf); + + if (!uclass_get_device(UCLASS_MMC, 1, &dev)) + board_get_alt_info("mmc1", buf); + + if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) + board_get_alt_info("nor0", buf); + + mtd = get_mtd_device_nm("nand0"); + if (!IS_ERR_OR_NULL(mtd)) + board_get_alt_info("nand0", buf); + + mtd = get_mtd_device_nm("spi-nand0"); + if (!IS_ERR_OR_NULL(mtd)) + board_get_alt_info("spi-nand0", buf); + +#ifdef CONFIG_DFU_VIRT + strncat(buf, "&virt 0=OTP", DFU_ALT_BUF_LEN); + + if (IS_ENABLED(CONFIG_PMIC_STPMIC1)) + strncat(buf, "&virt 1=PMIC", DFU_ALT_BUF_LEN); +#endif + + env_set("dfu_alt_info", buf); + puts("DFU alt info setting: done\n"); +} + +#if CONFIG_IS_ENABLED(DFU_VIRT) +#include <dfu.h> +#include <power/stpmic1.h> + +int dfu_otp_read(u64 offset, u8 *buffer, long *size) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stm32mp_bsec), + &dev); + if (ret) + return ret; + + ret = misc_read(dev, offset + STM32_BSEC_OTP_OFFSET, buffer, *size); + if (ret >= 0) { + *size = ret; + ret = 0; + } + + return 0; +} + +int dfu_pmic_read(u64 offset, u8 *buffer, long *size) +{ + int ret; +#ifdef CONFIG_PMIC_STPMIC1 + struct udevice *dev; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stpmic1_nvm), + &dev); + if (ret) + return ret; + + ret = misc_read(dev, 0xF8 + offset, buffer, *size); + if (ret >= 0) { + *size = ret; + ret = 0; + } + if (ret == -EACCES) { + *size = 0; + ret = 0; + } +#else + pr_err("PMIC update not supported"); + ret = -EOPNOTSUPP; +#endif + + return ret; +} + +int dfu_read_medium_virt(struct dfu_entity *dfu, u64 offset, + void *buf, long *len) +{ + switch (dfu->data.virt.dev_num) { + case 0x0: + return dfu_otp_read(offset, buf, len); + case 0x1: + return dfu_pmic_read(offset, buf, len); + } + *len = 0; + return 0; +} + +int __weak dfu_get_medium_size_virt(struct dfu_entity *dfu, u64 *size) +{ + *size = SZ_1K; + + return 0; +} + +#endif + +#endif + static void board_copro_image_process(ulong fw_image, size_t fw_size) { int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */ diff --git a/common/usb_kbd.c b/common/usb_kbd.c index d178af248af..a6221ef7164 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -75,13 +75,12 @@ static const unsigned char usb_kbd_num_keypad[] = { '.', 0, 0, 0, '=' }; -/* - * map arrow keys to ^F/^B ^N/^P, can't really use the proper - * ANSI sequence for arrow keys because the queuing code breaks - * when a single keypress expands to 3 queue elements - */ -static const unsigned char usb_kbd_arrow[] = { - 0x6, 0x2, 0xe, 0x10 +static const u8 usb_special_keys[] = { +#ifdef CONFIG_USB_KEYBOARD_FN_KEYS + '2', 'H', '5', '3', 'F', '6', 'C', 'D', 'B', 'A' +#else + 'C', 'D', 'B', 'A' +#endif }; /* @@ -96,12 +95,6 @@ static const unsigned char usb_kbd_arrow[] = { #define USB_KBD_LEDMASK \ (USB_KBD_NUMLOCK | USB_KBD_CAPSLOCK | USB_KBD_SCROLLLOCK) -/* - * USB Keyboard reports are 8 bytes in boot protocol. - * Appendix B of HID Device Class Definition 1.11 - */ -#define USB_KBD_BOOT_REPORT_SIZE 8 - struct usb_kbd_pdata { unsigned long intpipe; int intpktsize; @@ -127,7 +120,7 @@ extern int __maybe_unused net_busy_flag; static unsigned long __maybe_unused kbd_testc_tms; /* Puts character in the queue and sets up the in and out pointer. */ -static void usb_kbd_put_queue(struct usb_kbd_pdata *data, char c) +static void usb_kbd_put_queue(struct usb_kbd_pdata *data, u8 c) { if (data->usb_in_pointer == USB_KBD_BUFFER_LEN - 1) { /* Check for buffer full. */ @@ -146,12 +139,6 @@ static void usb_kbd_put_queue(struct usb_kbd_pdata *data, char c) data->usb_kbd_buffer[data->usb_in_pointer] = c; } -static void usb_kbd_put_sequence(struct usb_kbd_pdata *data, char *s) -{ - for (; *s; s++) - usb_kbd_put_queue(data, *s); -} - /* * Set the LEDs. Since this is used in the irq routine, the control job is * issued with a timeout of 0. This means, that the job is queued without @@ -214,10 +201,6 @@ static int usb_kbd_translate(struct usb_kbd_pdata *data, unsigned char scancode, keycode = usb_kbd_numkey[scancode - 0x1e]; } - /* Arrow keys */ - if ((scancode >= 0x4f) && (scancode <= 0x52)) - keycode = usb_kbd_arrow[scancode - 0x4f]; - /* Numeric keypad */ if ((scancode >= 0x54) && (scancode <= 0x67)) keycode = usb_kbd_num_keypad[scancode - 0x54]; @@ -242,28 +225,58 @@ static int usb_kbd_translate(struct usb_kbd_pdata *data, unsigned char scancode, } /* Report keycode if any */ - if (keycode) + if (keycode) { debug("%c", keycode); - - switch (keycode) { - case 0x0e: /* Down arrow key */ - usb_kbd_put_sequence(data, "\e[B"); - break; - case 0x10: /* Up arrow key */ - usb_kbd_put_sequence(data, "\e[A"); - break; - case 0x06: /* Right arrow key */ - usb_kbd_put_sequence(data, "\e[C"); - break; - case 0x02: /* Left arrow key */ - usb_kbd_put_sequence(data, "\e[D"); - break; - default: usb_kbd_put_queue(data, keycode); - break; + return 0; } +#ifdef CONFIG_USB_KEYBOARD_FN_KEYS + if (scancode < 0x3a || scancode > 0x52 || + scancode == 0x46 || scancode == 0x47) + return 1; + + usb_kbd_put_queue(data, 0x1b); + if (scancode < 0x3e) { + /* F1 - F4 */ + usb_kbd_put_queue(data, 0x4f); + usb_kbd_put_queue(data, scancode - 0x3a + 'P'); + return 0; + } + usb_kbd_put_queue(data, '['); + if (scancode < 0x42) { + /* F5 - F8 */ + usb_kbd_put_queue(data, '1'); + if (scancode == 0x3e) + --scancode; + keycode = scancode - 0x3f + '7'; + } else if (scancode < 0x49) { + /* F9 - F12 */ + usb_kbd_put_queue(data, '2'); + if (scancode > 0x43) + ++scancode; + keycode = scancode - 0x42 + '0'; + } else { + /* + * INSERT, HOME, PAGE UP, DELETE, END, PAGE DOWN, + * RIGHT, LEFT, DOWN, UP + */ + keycode = usb_special_keys[scancode - 0x49]; + } + usb_kbd_put_queue(data, keycode); + if (scancode < 0x4f && scancode != 0x4a && scancode != 0x4d) + usb_kbd_put_queue(data, '~'); return 0; +#else + /* Left, Right, Up, Down */ + if (scancode > 0x4e && scancode < 0x53) { + usb_kbd_put_queue(data, 0x1b); + usb_kbd_put_queue(data, '['); + usb_kbd_put_queue(data, usb_special_keys[scancode - 0x4f]); + return 0; + } + return 1; +#endif /* CONFIG_USB_KEYBOARD_FN_KEYS */ } static uint32_t usb_kbd_service_key(struct usb_device *dev, int i, int up) @@ -339,7 +352,7 @@ static inline void usb_kbd_poll_for_event(struct usb_device *dev) #if defined(CONFIG_SYS_USB_EVENT_POLL) struct usb_kbd_pdata *data = dev->privptr; - /* Submit a interrupt transfer request */ + /* Submit an interrupt transfer request */ if (usb_int_msg(dev, data->intpipe, &data->new[0], data->intpktsize, data->intinterval, true) >= 0) usb_kbd_irq_worker(dev); diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index c5fad3ebc2f..ded611a8127 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -72,3 +72,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 4230a494993..0d8f6dae30f 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -67,3 +67,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 888f9e98fbd..0cb63510108 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -69,3 +69,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 454a7991b1d..d52b32da1f5 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -56,3 +56,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 1bf070971bd..3afb74a69e3 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -71,3 +71,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 601c7dccb09..b5093c2d35d 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -66,3 +66,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index c9de7bc56c6..1e59e8e5fda 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -68,3 +68,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 605c9257cc9..1b9afe817df 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -55,3 +55,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 8cebc3ce8f0..8546089e58c 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -75,3 +75,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 2bd17ec3265..96031736371 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -70,3 +70,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index a5255a3a96f..9a30cbce03f 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -72,3 +72,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index ea3e26cf4fb..3d286dc389e 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -59,3 +59,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 8d54a0f0c1d..de69b1de059 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -77,3 +77,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 770e497d511..a3a18497673 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -72,3 +72,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 3e9a841828d..aa1077bbf39 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -74,3 +74,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 243f4e108af..dfecbb649fd 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -61,3 +61,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index c4050b8da72..7fcac7219bc 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -76,3 +76,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 94458c9d14d..007b9b6b86d 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -71,3 +71,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 19807d45f48..047ec6966b7 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -73,3 +73,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index ebd6d76d8ff..af4e017307a 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -60,3 +60,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 889cc60fe0b..503ce939717 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -56,3 +56,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index a09a0b8aa1c..bb0cdf77a31 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -55,3 +55,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 9dc89848e11..59244133bcd 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -56,3 +56,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index b51a1204826..7867e0bee6e 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -54,3 +54,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index 04c6a11e9a3..550faba5657 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -56,3 +56,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index 32c85d38e06..5dc299b4d4f 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -55,3 +55,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index c3752a60ee4..fa92627487d 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -56,3 +56,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index 0757ece1522..2c4fd559df4 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -54,3 +54,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index e8209fab6c5..806708b0b28 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -55,3 +55,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index 2d0cb461453..c15238a7f40 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -56,3 +56,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index 801f56026a0..11449054295 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -54,3 +54,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index 465fc371f5c..45311f5eff0 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -57,3 +57,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index 711d97221c0..349f7f0fac7 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -56,3 +56,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 2b96bca1a9e..7dd0e9a67b1 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -57,3 +57,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index bb9e5d86a14..4707e4b5252 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -55,3 +55,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index d9fe82acadc..5830c9213af 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -78,3 +78,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 8412eb1bece..bd346eaf9a1 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -75,3 +75,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index cbb992cb2fa..743d66c060a 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -78,3 +78,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 2b40f5d1c09..05a048a4147 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -63,3 +63,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 5ea869abf7e..30c87410e0f 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -78,3 +78,4 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_DM_MMC=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 4dca49cb39a..e07a045984a 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -75,3 +75,4 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_DM_MMC=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 4aeb63eac1e..3edc58c5907 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -78,3 +78,4 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_DM_MMC=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index ad976961a99..02cb88f0907 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -63,3 +63,4 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_CFB_CONSOLE_ANSI=y +CONFIG_DM_MMC=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 3d4e0eb397f..c0ce18101f3 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -74,3 +74,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 1a3a6a37334..dd1179796fa 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -71,3 +71,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 01723c63d00..bfc97993721 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -74,3 +74,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 71a95599d11..dd9c63abe57 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -59,3 +59,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index b5d30617104..46530523550 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -65,3 +65,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 0e926df4fad..37b459e809d 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -53,3 +53,4 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 716096abc54..be1e103cf41 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -181,6 +181,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EMUL=y CONFIG_USB_KEYBOARD=y +CONFIG_USB_KEYBOARD_FN_KEYS=y CONFIG_DM_VIDEO=y CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index a8144436ebd..eda595fca96 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -203,6 +203,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EMUL=y CONFIG_USB_KEYBOARD=y +CONFIG_USB_KEYBOARD_FN_KEYS=y CONFIG_DM_VIDEO=y CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 774c278bce8..02969f95f10 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -163,6 +163,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EMUL=y CONFIG_USB_KEYBOARD=y +CONFIG_USB_KEYBOARD_FN_KEYS=y CONFIG_DM_VIDEO=y CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 02702fa7a55..3b0f15de88e 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -183,6 +183,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EMUL=y CONFIG_USB_KEYBOARD=y +CONFIG_USB_KEYBOARD_FN_KEYS=y CONFIG_DM_VIDEO=y CONFIG_CONSOLE_ROTATION=y CONFIG_CONSOLE_TRUETYPE=y diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 3c159ce39dd..0b189710873 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -33,6 +33,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_STI=y +CONFIG_DM_ETH=y CONFIG_PHY=y CONFIG_STI_USB_PHY=y CONFIG_PINCTRL=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index db653daac01..ae3ee5a9b54 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -64,6 +65,10 @@ CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_STM32_ADC=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_MTD=y +CONFIG_DFU_VIRT=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 CONFIG_FASTBOOT_BUF_SIZE=0x02000000 @@ -84,6 +89,7 @@ CONFIG_STM32_SDMMC2=y CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_STM32_FMC2=y +CONFIG_MTD_SPI_NAND=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/stm32mp15_optee_defconfig b/configs/stm32mp15_optee_defconfig index 8f4199d24d6..e8620d6bc78 100644 --- a/configs/stm32mp15_optee_defconfig +++ b/configs/stm32mp15_optee_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -51,6 +52,10 @@ CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_STM32_ADC=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_MTD=y +CONFIG_DFU_VIRT=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 CONFIG_FASTBOOT_BUF_SIZE=0x02000000 @@ -71,6 +76,7 @@ CONFIG_STM32_SDMMC2=y CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_STM32_FMC2=y +CONFIG_MTD_SPI_NAND=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 5e5528f37bc..2d937e65fbf 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -50,6 +51,10 @@ CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_STM32_ADC=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_MTD=y +CONFIG_DFU_VIRT=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 CONFIG_FASTBOOT_BUF_SIZE=0x02000000 @@ -70,6 +75,7 @@ CONFIG_STM32_SDMMC2=y CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_STM32_FMC2=y +CONFIG_MTD_SPI_NAND=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/vct_platinum_defconfig b/configs/vct_platinum_defconfig deleted file mode 100644 index ecb3358c292..00000000000 --- a/configs/vct_platinum_defconfig +++ /dev/null @@ -1,32 +0,0 @@ -CONFIG_MIPS=y -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_TARGET_VCT=y -CONFIG_VCT_PLATINUM=y -CONFIG_BOOTDELAY=5 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="$ " -CONFIG_CMD_IMLS=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xB0040000 -CONFIG_ENV_ADDR_REDUND=0xB0050000 -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x00000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/vct_platinum_onenand_defconfig b/configs/vct_platinum_onenand_defconfig deleted file mode 100644 index 2788dca4ad9..00000000000 --- a/configs/vct_platinum_onenand_defconfig +++ /dev/null @@ -1,35 +0,0 @@ -CONFIG_MIPS=y -CONFIG_ENV_SIZE=0x20000 -CONFIG_TARGET_VCT=y -CONFIG_VCT_PLATINUM=y -CONFIG_VCT_ONENAND=y -CONFIG_BOOTDELAY=5 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="$ " -CONFIG_CMD_EEPROM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_ONENAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="onenand0=onenand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_ENV_IS_IN_ONENAND=y -CONFIG_ENV_ADDR=0x20000 -CONFIG_MTD_DEVICE=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x00000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/vct_platinum_onenand_small_defconfig b/configs/vct_platinum_onenand_small_defconfig deleted file mode 100644 index 56be171e769..00000000000 --- a/configs/vct_platinum_onenand_small_defconfig +++ /dev/null @@ -1,35 +0,0 @@ -CONFIG_MIPS=y -CONFIG_ENV_SIZE=0x20000 -CONFIG_TARGET_VCT=y -CONFIG_VCT_PLATINUM=y -CONFIG_VCT_ONENAND=y -CONFIG_VCT_SMALL_IMAGE=y -CONFIG_BOOTDELAY=5 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_SYS_LONGHELP is not set -CONFIG_SYS_PROMPT="$ " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_ONENAND=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MISC is not set -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="onenand0=onenand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_ENV_IS_IN_ONENAND=y -CONFIG_ENV_ADDR=0x20000 -# CONFIG_NET is not set -CONFIG_MTD_DEVICE=y -CONFIG_SYS_NS16550=y diff --git a/configs/vct_platinum_small_defconfig b/configs/vct_platinum_small_defconfig deleted file mode 100644 index 4a0d53e555b..00000000000 --- a/configs/vct_platinum_small_defconfig +++ /dev/null @@ -1,32 +0,0 @@ -CONFIG_MIPS=y -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_TARGET_VCT=y -CONFIG_VCT_PLATINUM=y -CONFIG_VCT_SMALL_IMAGE=y -CONFIG_BOOTDELAY=5 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_SYS_LONGHELP is not set -CONFIG_SYS_PROMPT="$ " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_ELF is not set -CONFIG_CMD_IMLS=y -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MISC is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xB0040000 -CONFIG_ENV_ADDR_REDUND=0xB0050000 -# CONFIG_NET is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_NS16550=y diff --git a/configs/vct_platinumavc_defconfig b/configs/vct_platinumavc_defconfig deleted file mode 100644 index 03ab55de703..00000000000 --- a/configs/vct_platinumavc_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_MIPS=y -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_TARGET_VCT=y -CONFIG_VCT_PLATINUMAVC=y -CONFIG_BOOTDELAY=5 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="VCT# " -CONFIG_CMD_IMLS=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xB0040000 -CONFIG_ENV_ADDR_REDUND=0xB0050000 -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_NS16550=y -# CONFIG_REGEX is not set diff --git a/configs/vct_platinumavc_onenand_defconfig b/configs/vct_platinumavc_onenand_defconfig deleted file mode 100644 index 8fd81dd51e2..00000000000 --- a/configs/vct_platinumavc_onenand_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_MIPS=y -CONFIG_ENV_SIZE=0x20000 -CONFIG_TARGET_VCT=y -CONFIG_VCT_PLATINUMAVC=y -CONFIG_VCT_ONENAND=y -CONFIG_BOOTDELAY=5 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="$ " -CONFIG_CMD_EEPROM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_ONENAND=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="onenand0=onenand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_ENV_IS_IN_ONENAND=y -CONFIG_ENV_ADDR=0x20000 -CONFIG_MTD_DEVICE=y -CONFIG_SYS_NS16550=y -# CONFIG_REGEX is not set diff --git a/configs/vct_platinumavc_onenand_small_defconfig b/configs/vct_platinumavc_onenand_small_defconfig deleted file mode 100644 index fa2c91f0635..00000000000 --- a/configs/vct_platinumavc_onenand_small_defconfig +++ /dev/null @@ -1,35 +0,0 @@ -CONFIG_MIPS=y -CONFIG_ENV_SIZE=0x20000 -CONFIG_TARGET_VCT=y -CONFIG_VCT_PLATINUMAVC=y -CONFIG_VCT_ONENAND=y -CONFIG_VCT_SMALL_IMAGE=y -CONFIG_BOOTDELAY=5 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_SYS_LONGHELP is not set -CONFIG_SYS_PROMPT="$ " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_ONENAND=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MISC is not set -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="onenand0=onenand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_ENV_IS_IN_ONENAND=y -CONFIG_ENV_ADDR=0x20000 -# CONFIG_NET is not set -CONFIG_MTD_DEVICE=y -CONFIG_SYS_NS16550=y diff --git a/configs/vct_platinumavc_small_defconfig b/configs/vct_platinumavc_small_defconfig deleted file mode 100644 index 5f897a89ec9..00000000000 --- a/configs/vct_platinumavc_small_defconfig +++ /dev/null @@ -1,32 +0,0 @@ -CONFIG_MIPS=y -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_TARGET_VCT=y -CONFIG_VCT_PLATINUMAVC=y -CONFIG_VCT_SMALL_IMAGE=y -CONFIG_BOOTDELAY=5 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_SYS_LONGHELP is not set -CONFIG_SYS_PROMPT="$ " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_ELF is not set -CONFIG_CMD_IMLS=y -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MISC is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xB0040000 -CONFIG_ENV_ADDR_REDUND=0xB0050000 -# CONFIG_NET is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_NS16550=y diff --git a/configs/vct_premium_defconfig b/configs/vct_premium_defconfig deleted file mode 100644 index 0762194e333..00000000000 --- a/configs/vct_premium_defconfig +++ /dev/null @@ -1,32 +0,0 @@ -CONFIG_MIPS=y -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_TARGET_VCT=y -CONFIG_VCT_PREMIUM=y -CONFIG_BOOTDELAY=5 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="$ " -CONFIG_CMD_IMLS=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xB0040000 -CONFIG_ENV_ADDR_REDUND=0xB0050000 -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x00000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/vct_premium_onenand_defconfig b/configs/vct_premium_onenand_defconfig deleted file mode 100644 index a6851d9eb8f..00000000000 --- a/configs/vct_premium_onenand_defconfig +++ /dev/null @@ -1,35 +0,0 @@ -CONFIG_MIPS=y -CONFIG_ENV_SIZE=0x20000 -CONFIG_TARGET_VCT=y -CONFIG_VCT_PREMIUM=y -CONFIG_VCT_ONENAND=y -CONFIG_BOOTDELAY=5 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="$ " -CONFIG_CMD_EEPROM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_ONENAND=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="onenand0=onenand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_ENV_IS_IN_ONENAND=y -CONFIG_ENV_ADDR=0x20000 -CONFIG_MTD_DEVICE=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x00000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/vct_premium_onenand_small_defconfig b/configs/vct_premium_onenand_small_defconfig deleted file mode 100644 index 7dd68887d70..00000000000 --- a/configs/vct_premium_onenand_small_defconfig +++ /dev/null @@ -1,35 +0,0 @@ -CONFIG_MIPS=y -CONFIG_ENV_SIZE=0x20000 -CONFIG_TARGET_VCT=y -CONFIG_VCT_PREMIUM=y -CONFIG_VCT_ONENAND=y -CONFIG_VCT_SMALL_IMAGE=y -CONFIG_BOOTDELAY=5 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_SYS_LONGHELP is not set -CONFIG_SYS_PROMPT="$ " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_ONENAND=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MISC is not set -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="onenand0=onenand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_ENV_IS_IN_ONENAND=y -CONFIG_ENV_ADDR=0x20000 -# CONFIG_NET is not set -CONFIG_MTD_DEVICE=y -CONFIG_SYS_NS16550=y diff --git a/configs/vct_premium_small_defconfig b/configs/vct_premium_small_defconfig deleted file mode 100644 index b19d3a60778..00000000000 --- a/configs/vct_premium_small_defconfig +++ /dev/null @@ -1,32 +0,0 @@ -CONFIG_MIPS=y -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_TARGET_VCT=y -CONFIG_VCT_PREMIUM=y -CONFIG_VCT_SMALL_IMAGE=y -CONFIG_BOOTDELAY=5 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_SYS_LONGHELP is not set -CONFIG_SYS_PROMPT="$ " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_ELF is not set -CONFIG_CMD_IMLS=y -# CONFIG_CMD_CRC32 is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MISC is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xB0040000 -CONFIG_ENV_ADDR_REDUND=0xB0050000 -# CONFIG_NET is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_NS16550=y diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 8ff84aa3a8d..09cb773fe9c 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -12,7 +12,6 @@ #include <config.h> #include <common.h> #include <command.h> -#include <clk.h> #include <errno.h> #include <hwconfig.h> #include <mmc.h> @@ -81,7 +80,6 @@ struct fsl_esdhc_plat { struct fsl_esdhc_priv { struct fsl_esdhc *esdhc_regs; unsigned int sdhc_clk; - struct clk per_clk; unsigned int clock; #if !CONFIG_IS_ENABLED(DM_MMC) struct mmc *mmc; @@ -831,9 +829,6 @@ int fsl_esdhc_mmc_init(bd_t *bis) return fsl_esdhc_initialize(bis, cfg); } #else /* DM_MMC */ -#ifndef CONFIG_PPC -#include <asm/arch/clock.h> -#endif static int fsl_esdhc_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); @@ -841,7 +836,6 @@ static int fsl_esdhc_probe(struct udevice *dev) struct fsl_esdhc_priv *priv = dev_get_priv(dev); fdt_addr_t addr; struct mmc *mmc; - int ret; addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) @@ -853,30 +847,10 @@ static int fsl_esdhc_probe(struct udevice *dev) #endif priv->dev = dev; - if (IS_ENABLED(CONFIG_CLK)) { - /* Assigned clock already set clock */ - ret = clk_get_by_name(dev, "per", &priv->per_clk); - if (ret) { - printf("Failed to get per_clk\n"); - return ret; - } - ret = clk_enable(&priv->per_clk); - if (ret) { - printf("Failed to enable per_clk\n"); - return ret; - } - - priv->sdhc_clk = clk_get_rate(&priv->per_clk); - } else { -#ifndef CONFIG_PPC - priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); -#else - priv->sdhc_clk = gd->arch.sdhc_clk; -#endif - if (priv->sdhc_clk <= 0) { - dev_err(dev, "Unable to get clk for %s\n", dev->name); - return -EINVAL; - } + priv->sdhc_clk = gd->arch.sdhc_clk; + if (priv->sdhc_clk <= 0) { + dev_err(dev, "Unable to get clk for %s\n", dev->name); + return -EINVAL; } fsl_esdhc_get_cfg_common(priv, &plat->cfg); diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 0cb65b480d3..e01ac310e9f 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -34,7 +34,12 @@ #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0) #define RENESAS_SDHI_SCC_RVSREQ 0x814 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2) +#define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) +#define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) #define RENESAS_SDHI_SCC_SMPCMP 0x818 +#define RENESAS_SDHI_SCC_SMPCMP_CMD_ERR (BIT(24) | BIT(8)) +#define RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) +#define RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) #define RENESAS_SDHI_SCC_TMPPORT2 0x81c #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31) #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) @@ -58,6 +63,49 @@ #define RENESAS_SDHI_MAX_TAP 3 +#define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1) + +static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = { + { 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 5, 5, 6, 6, 7, 11, + 15, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 21 }, + { 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 15, + 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 } +}; + +static const u8 r8a7796_rev1_calib_table[2][CALIB_TABLE_MAX] = { + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 9, + 15, 15, 15, 16, 16, 16, 16, 16, 17, 18, 19, 20, 21, 21, 22, 22 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, + 2, 9, 16, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 23, 24} +}; + +static const u8 r8a7796_rev3_calib_table[2][CALIB_TABLE_MAX] = { + { 0, 0, 0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 9, 10, + 11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 }, + { 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24 } +}; + +static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = { + { 0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, + 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 29 }, + { 0, 1, 2, 2, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 15, + 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31 } +}; + +static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = { + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 5, 6, 7, 8, 10, 11, + 12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 } +}; + +static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv) +{ + /* On R-Car Gen3, MMC0 is at 0xee140000 */ + return (uintptr_t)(priv->regbase) == 0xee140000; +} + static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr) { /* read mode */ @@ -87,6 +135,102 @@ static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val) tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4); } +static bool renesas_sdhi_check_scc_error(struct udevice *dev) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); + unsigned long new_tap = priv->tap_set; + unsigned long error_tap = priv->tap_set; + u32 reg, smpcmp; + + if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) && + (mmc->selected_mode != UHS_SDR104) && + (mmc->selected_mode != MMC_HS_200) && + (mmc->selected_mode != MMC_HS_400) && + (priv->nrtaps != 4)) + return false; + + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); + /* Handle automatic tuning correction */ + if (reg & RENESAS_SDHI_SCC_RVSCNTL_RVSEN) { + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ); + if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) { + tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ); + return true; + } + + return false; + } + + /* Handle manual tuning correction */ + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ); + if (!reg) /* No error */ + return false; + + tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ); + + if (mmc->selected_mode == MMC_HS_400) { + /* + * Correction Error Status contains CMD and DAT signal status. + * In HS400, DAT signal based on DS signal, not CLK. + * Therefore, use only CMD status. + */ + smpcmp = tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP) & + RENESAS_SDHI_SCC_SMPCMP_CMD_ERR; + + switch (smpcmp) { + case 0: + return false; /* No error in CMD signal */ + case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP: + new_tap = (priv->tap_set + + priv->tap_num + 1) % priv->tap_num; + error_tap = (priv->tap_set + + priv->tap_num - 1) % priv->tap_num; + break; + case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN: + new_tap = (priv->tap_set + + priv->tap_num - 1) % priv->tap_num; + error_tap = (priv->tap_set + + priv->tap_num + 1) % priv->tap_num; + break; + default: + return true; /* Need re-tune */ + } + + if (priv->hs400_bad_tap & BIT(new_tap)) { + /* + * New tap is bad tap (cannot change). + * Compare with HS200 tuning result. + * In HS200 tuning, when smpcmp[error_tap] + * is OK, retune is executed. + */ + if (priv->smpcmp & BIT(error_tap)) + return true; /* Need retune */ + + return false; /* cannot change */ + } + + priv->tap_set = new_tap; + } else { + if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) + return true; /* Need re-tune */ + else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPUP) + priv->tap_set = (priv->tap_set + + priv->tap_num + 1) % priv->tap_num; + else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN) + priv->tap_set = (priv->tap_set + + priv->tap_num - 1) % priv->tap_num; + else + return false; + } + + /* Set TAP position */ + tmio_sd_writel(priv, priv->tap_set >> ((priv->nrtaps == 4) ? 1 : 0), + RENESAS_SDHI_SCC_TAPSET); + + return false; +} + static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv) { u32 calib_code; @@ -97,28 +241,30 @@ static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv) if (!priv->needs_adjust_hs400) return; + if (!priv->adjust_hs400_calib_table) + return; + /* * Enabled Manual adjust HS400 mode * * 1) Disabled Write Protect * W(addr=0x00, WP_DISABLE_CODE) - * 2) Read Calibration code and adjust - * R(addr=0x26) - adjust value - * 3) Enabled Manual Calibration + * + * 2) Read Calibration code + * read_value = R(addr=0x26) + * 3) Refer to calibration table + * Calibration code = table[read_value] + * 4) Enabled Manual Calibration * W(addr=0x22, manual mode | Calibration code) - * 4) Set Offset value to TMPPORT3 Reg + * 5) Set Offset value to TMPPORT3 Reg */ sd_scc_tmpport_write32(priv, 0x00, RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); calib_code = sd_scc_tmpport_read32(priv, 0x26); calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; - if (calib_code > priv->adjust_hs400_calibrate) - calib_code -= priv->adjust_hs400_calibrate; - else - calib_code = 0; sd_scc_tmpport_write32(priv, 0x22, RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE | - calib_code); + priv->adjust_hs400_calib_table[calib_code]); tmio_sd_writel(priv, priv->adjust_hs400_offset, RENESAS_SDHI_SCC_TMPPORT3); @@ -220,6 +366,7 @@ static int renesas_sdhi_hs400(struct udevice *dev) struct mmc *mmc = mmc_get_mmc_dev(dev); bool hs400 = (mmc->selected_mode == MMC_HS_400); int ret, taps = hs400 ? priv->nrtaps : 8; + unsigned long new_tap; u32 reg; if (taps == 4) /* HS400 on 4tap SoC needs different clock */ @@ -229,7 +376,9 @@ static int renesas_sdhi_hs400(struct udevice *dev) if (ret < 0) return ret; - tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ); + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); + reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN; + tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2); if (hs400) { @@ -250,24 +399,38 @@ static int renesas_sdhi_hs400(struct udevice *dev) RENESAS_SDHI_SCC_DTCNTL_TAPEN, RENESAS_SDHI_SCC_DTCNTL); + /* Avoid bad TAP */ + if (priv->hs400_bad_tap & BIT(priv->tap_set)) { + new_tap = (priv->tap_set + + priv->tap_num + 1) % priv->tap_num; + + if (priv->hs400_bad_tap & BIT(new_tap)) + new_tap = (priv->tap_set + + priv->tap_num - 1) % priv->tap_num; + + if (priv->hs400_bad_tap & BIT(new_tap)) { + new_tap = priv->tap_set; + debug("Three consecutive bad tap is prohibited\n"); + } + + priv->tap_set = new_tap; + tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET); + } + if (taps == 4) { tmio_sd_writel(priv, priv->tap_set >> 1, RENESAS_SDHI_SCC_TAPSET); + tmio_sd_writel(priv, hs400 ? 0x100 : 0x300, + RENESAS_SDHI_SCC_DT2FF); } else { tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET); + tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF); } - tmio_sd_writel(priv, hs400 ? 0x704 : 0x300, - RENESAS_SDHI_SCC_DT2FF); - reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL); reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL; tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL); - reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); - reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN; - tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); - /* Execute adjust hs400 offset after setting to HS400 mode */ if (hs400) priv->needs_adjust_hs400 = true; @@ -289,8 +452,7 @@ static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv) } static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, - unsigned int tap_num, unsigned int taps, - unsigned int smpcmp) + unsigned int taps) { unsigned long tap_cnt; /* counter of tuning success */ unsigned long tap_start;/* start position of tuning success */ @@ -307,14 +469,14 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ); /* Merge the results */ - for (i = 0; i < tap_num * 2; i++) { + for (i = 0; i < priv->tap_num * 2; i++) { if (!(taps & BIT(i))) { - taps &= ~BIT(i % tap_num); - taps &= ~BIT((i % tap_num) + tap_num); + taps &= ~BIT(i % priv->tap_num); + taps &= ~BIT((i % priv->tap_num) + priv->tap_num); } - if (!(smpcmp & BIT(i))) { - smpcmp &= ~BIT(i % tap_num); - smpcmp &= ~BIT((i % tap_num) + tap_num); + if (!(priv->smpcmp & BIT(i))) { + priv->smpcmp &= ~BIT(i % priv->tap_num); + priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num); } } @@ -327,7 +489,7 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, ntap = 0; tap_start = 0; tap_end = 0; - for (i = 0; i < tap_num * 2; i++) { + for (i = 0; i < priv->tap_num * 2; i++) { if (taps & BIT(i)) ntap++; else { @@ -350,13 +512,13 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, * If all of the TAP is OK, the sampling clock position is selected by * identifying the change point of data. */ - if (tap_cnt == tap_num * 2) { + if (tap_cnt == priv->tap_num * 2) { match_cnt = 0; ntap = 0; tap_start = 0; tap_end = 0; - for (i = 0; i < tap_num * 2; i++) { - if (smpcmp & BIT(i)) + for (i = 0; i < priv->tap_num * 2; i++) { + if (priv->smpcmp & BIT(i)) ntap++; else { if (ntap > match_cnt) { @@ -378,7 +540,7 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, select = true; if (select) - priv->tap_set = ((tap_start + tap_end) / 2) % tap_num; + priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num; else return -EIO; @@ -399,7 +561,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct mmc *mmc = upriv->mmc; unsigned int tap_num; - unsigned int taps = 0, smpcmp = 0; + unsigned int taps = 0; int i, ret = 0; u32 caps; @@ -419,15 +581,19 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) /* Tuning is not supported */ goto out; - if (tap_num * 2 >= sizeof(taps) * 8) { + priv->tap_num = tap_num; + + if (priv->tap_num * 2 >= sizeof(taps) * 8) { dev_err(dev, "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n"); goto out; } + priv->smpcmp = 0; + /* Issue CMD19 twice for each tap */ - for (i = 0; i < 2 * tap_num; i++) { - renesas_sdhi_prepare_tuning(priv, i % tap_num); + for (i = 0; i < 2 * priv->tap_num; i++) { + renesas_sdhi_prepare_tuning(priv, i % priv->tap_num); /* Force PIO for the tuning */ caps = priv->caps; @@ -442,12 +608,12 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) ret = renesas_sdhi_compare_scc_data(priv); if (ret == 0) - smpcmp |= BIT(i); + priv->smpcmp |= BIT(i); mdelay(1); } - ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp); + ret = renesas_sdhi_select_tuning(priv, taps); out: if (ret < 0) { @@ -535,6 +701,8 @@ static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) struct tmio_sd_priv *priv = dev_get_priv(dev); + renesas_sdhi_check_scc_error(dev); + if (cmd->cmdidx == MMC_CMD_SEND_STATUS) renesas_sdhi_adjust_hs400_mode_enable(priv); #endif @@ -582,50 +750,89 @@ static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv) static void renesas_sdhi_filter_caps(struct udevice *dev) { - struct tmio_sd_plat *plat = dev_get_platdata(dev); struct tmio_sd_priv *priv = dev_get_priv(dev); if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3)) return; - /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1,ES1.2 */ +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + struct tmio_sd_plat *plat = dev_get_platdata(dev); + + /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */ if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && (rmobile_get_cpu_rev_integer() <= 1)) || ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && (rmobile_get_cpu_rev_integer() == 1) && - (rmobile_get_cpu_rev_fraction() <= 2))) + (rmobile_get_cpu_rev_fraction() < 2))) plat->cfg.host_caps &= ~MMC_MODE_HS400; - /* M3W ES1.x for x>2 can use HS400 with manual adjustment */ + /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */ + if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && + (rmobile_get_cpu_rev_integer() >= 2)) || + ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && + (rmobile_get_cpu_rev_integer() == 1) && + (rmobile_get_cpu_rev_fraction() == 2)) || + (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965)) + priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7); + + /* H3 ES3.0 can use HS400 with manual adjustment */ + if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && + (rmobile_get_cpu_rev_integer() >= 3)) { + priv->adjust_hs400_enable = true; + priv->adjust_hs400_offset = 0; + priv->adjust_hs400_calib_table = + r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)]; + } + + /* M3W ES1.2 can use HS400 with manual adjustment */ + if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && + (rmobile_get_cpu_rev_integer() == 1) && + (rmobile_get_cpu_rev_fraction() == 2)) { + priv->adjust_hs400_enable = true; + priv->adjust_hs400_offset = 3; + priv->adjust_hs400_calib_table = + r8a7796_rev1_calib_table[!rmobile_is_gen3_mmc0(priv)]; + } + + /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */ if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && (rmobile_get_cpu_rev_integer() == 1) && (rmobile_get_cpu_rev_fraction() > 2)) { priv->adjust_hs400_enable = true; priv->adjust_hs400_offset = 0; - priv->adjust_hs400_calibrate = 0x9; + priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7); + priv->adjust_hs400_calib_table = + r8a7796_rev3_calib_table[!rmobile_is_gen3_mmc0(priv)]; } /* M3N can use HS400 with manual adjustment */ if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) { priv->adjust_hs400_enable = true; - priv->adjust_hs400_offset = 0; - priv->adjust_hs400_calibrate = 0x0; + priv->adjust_hs400_offset = 3; + priv->adjust_hs400_calib_table = + r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)]; } /* E3 can use HS400 with manual adjustment */ if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) { priv->adjust_hs400_enable = true; - priv->adjust_hs400_offset = 0; - priv->adjust_hs400_calibrate = 0x2; + priv->adjust_hs400_offset = 3; + priv->adjust_hs400_calib_table = + r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)]; } - /* H3 ES2.0 uses 4 tuning taps */ - if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && - (rmobile_get_cpu_rev_integer() == 2)) + /* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */ + if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && + (rmobile_get_cpu_rev_integer() <= 2)) || + ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && + (rmobile_get_cpu_rev_integer() == 1) && + (rmobile_get_cpu_rev_fraction() <= 2))) priv->nrtaps = 4; else priv->nrtaps = 8; - +#endif /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */ if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && (rmobile_get_cpu_rev_integer() <= 1)) || diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index fbc576fd726..32e83db8e09 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -660,7 +660,7 @@ int sdhci_probe(struct udevice *dev) return sdhci_init(mmc); } -int sdhci_get_cd(struct udevice *dev) +static int sdhci_get_cd(struct udevice *dev) { struct mmc *mmc = mmc_get_mmc_dev(dev); struct sdhci_host *host = mmc->priv; diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h index 51607de1426..047458849bd 100644 --- a/drivers/mmc/tmio-common.h +++ b/drivers/mmc/tmio-common.h @@ -137,12 +137,16 @@ struct tmio_sd_priv { struct clk clk; #endif #if CONFIG_IS_ENABLED(RENESAS_SDHI) + unsigned int smpcmp; u8 tap_set; + u8 tap_num; u8 nrtaps; bool needs_adjust_hs400; bool adjust_hs400_enable; u8 adjust_hs400_offset; u8 adjust_hs400_calibrate; + u8 hs400_bad_tap; + const u8 *adjust_hs400_calib_table; #endif ulong (*clk_get_rate)(struct tmio_sd_priv *); }; diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 9af78e88226..bea4a92b61f 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -100,6 +100,12 @@ config USB_KEYBOARD if USB_KEYBOARD +config USB_KEYBOARD_FN_KEYS + bool "USB keyboard function key support" + help + Say Y here if you want support for keys F1 - F12, INS, HOME, DELETE, + END, PAGE UP, and PAGE DOWN. + choice prompt "USB keyboard polling" default SYS_USB_EVENT_POLL diff --git a/drivers/usb/emul/sandbox_keyb.c b/drivers/usb/emul/sandbox_keyb.c index dc43880d27e..32bc9a16983 100644 --- a/drivers/usb/emul/sandbox_keyb.c +++ b/drivers/usb/emul/sandbox_keyb.c @@ -155,14 +155,20 @@ static void *keyb_desc_list[] = { NULL, }; -int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str) +/** + * sandbox_usb_keyb_add_string() - provide a USB scancode buffer + * + * @dev: the keyboard emulation device + * @scancode: scancode buffer with USB_KBD_BOOT_REPORT_SIZE bytes + */ +int sandbox_usb_keyb_add_string(struct udevice *dev, + const char scancode[USB_KBD_BOOT_REPORT_SIZE]) { struct sandbox_keyb_priv *priv = dev_get_priv(dev); - int len, ret; + int ret; - len = strlen(str); - ret = membuff_put(&priv->in, str, len); - if (ret != len) + ret = membuff_put(&priv->in, scancode, USB_KBD_BOOT_REPORT_SIZE); + if (ret != USB_KBD_BOOT_REPORT_SIZE) return -ENOSPC; return 0; @@ -183,12 +189,12 @@ static int sandbox_keyb_interrupt(struct udevice *dev, struct usb_device *udev, { struct sandbox_keyb_priv *priv = dev_get_priv(dev); uint8_t *data = buffer; - int ch; memset(data, '\0', length); - ch = membuff_getbyte(&priv->in); - if (ch != -1) - data[2] = 4 + ch - 'a'; + if (length < USB_KBD_BOOT_REPORT_SIZE) + return 0; + + membuff_get(&priv->in, buffer, USB_KBD_BOOT_REPORT_SIZE); return 0; } @@ -213,7 +219,8 @@ static int sandbox_keyb_probe(struct udevice *dev) { struct sandbox_keyb_priv *priv = dev_get_priv(dev); - return membuff_new(&priv->in, 256); + /* Provide an 80 character keyboard buffer */ + return membuff_new(&priv->in, 80 * USB_KBD_BOOT_REPORT_SIZE); } static const struct dm_usb_ops sandbox_usb_keyb_ops = { diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 988992b336e..d42a7860bea 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -83,6 +83,8 @@ #define CONFIG_SYS_MTDPARTS_RUNTIME #endif +#define CONFIG_SET_DFU_ALT_INFO + #ifdef CONFIG_DM_VIDEO #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_BMP_16BPP @@ -129,12 +131,15 @@ /* with OPTEE: define specific MTD partitions = teeh, teed, teex */ #define STM32MP_MTDPARTS \ "mtdparts_nor0=256k(fsbl1),256k(fsbl2),2m(ssbl),256k(u-boot-env),256k(teeh),256k(teed),256k(teex),-(nor_user)\0" \ - "mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),512k(teeh),512k(teed),512k(teex),-(UBI)\0" + "mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),512k(teeh),512k(teed),512k(teex),-(UBI)\0" \ + "mtdparts_spi-nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),"\ + "512k(teeh),512k(teed),512k(teex),-(UBI)\0" #else /* CONFIG_STM32MP1_OPTEE */ #define STM32MP_MTDPARTS \ "mtdparts_nor0=256k(fsbl1),256k(fsbl2),2m(ssbl),256k(u-boot-env),-(nor_user)\0" \ - "mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),-(UBI)\0" + "mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),-(UBI)\0" \ + "mtdparts_spi-nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),-(UBI)\0" #endif /* CONFIG_STM32MP1_OPTEE */ @@ -143,6 +148,37 @@ #define STM32MP_MTDPARTS #endif +#define STM32MP_DFU_ALT_RAM \ + "dfu_alt_info_ram=ram 0=" \ + "uImage ram ${kernel_addr_r} 0x2000000;" \ + "devicetree.dtb ram ${fdt_addr_r} 0x100000;" \ + "uramdisk.image.gz ram ${ramdisk_addr_r} 0x10000000\0" + +#ifdef CONFIG_SET_DFU_ALT_INFO +#define STM32MP_DFU_ALT_INFO \ + "dfu_alt_info_nor0=mtd nor0=" \ + "nor_fsbl1 part 1;nor_fsbl2 part 2;" \ + "nor_ssbl part 3;nor_env part 4\0" \ + "dfu_alt_info_nand0=mtd nand0="\ + "nand_fsbl part 1;nand_ssbl1 part 2;" \ + "nand_ssbl2 part 3;nand_UBI partubi 4\0" \ + "dfu_alt_info_spi-nand0=mtd spi-nand0="\ + "spi-nand_fsbl part 1;spi-nand_ssbl1 part 2;" \ + "spi-nand_ssbl2 part 3;spi-nand_UBI partubi 4\0" \ + "dfu_alt_info_mmc0=mmc 0=" \ + "sdcard_fsbl1 part 0 1;sdcard_fsbl2 part 0 2;" \ + "sdcard_ssbl part 0 3;sdcard_bootfs part 0 4;" \ + "sdcard_vendorfs part 0 5;sdcard_rootfs part 0 6;" \ + "sdcard_userfs part 0 7\0" \ + "dfu_alt_info_mmc1=mmc 1=" \ + "emmc_fsbl1 raw 0x0 0x200 mmcpart 1;" \ + "emmc_fsbl2 raw 0x0 0x200 mmcpart 2;emmc_ssbl part 1 1;" \ + "emmc_bootfs part 1 2;emmc_vendorfs part 1 3;" \ + "emmc_rootfs part 1 4;emmc_userfs part 1 5\0" +#else +#define STM32MP_DFU_ALT_INFO +#endif + /* * memory layout for 32M uncompressed/compressed kernel, * 1M fdt, 1M script, 1M pxe and 1M for splashimage @@ -164,6 +200,8 @@ " then env set env_default 0;env save;fi\0" \ STM32MP_BOOTCMD \ STM32MP_MTDPARTS \ + STM32MP_DFU_ALT_RAM \ + STM32MP_DFU_ALT_INFO \ BOOTENV \ "boot_net_usb_start=true\0" diff --git a/include/configs/vct.h b/include/configs/vct.h deleted file mode 100644 index 284d2682593..00000000000 --- a/include/configs/vct.h +++ /dev/null @@ -1,194 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering - */ - -/* - * This file contains the configuration parameters for the VCT board - * family: - * - * vct_premium - * vct_premium_small - * vct_premium_onenand - * vct_premium_onenand_small - * vct_platinum - * vct_platinum_small - * vct_platinum_onenand - * vct_platinum_onenand_small - * vct_platinumavc - * vct_platinumavc_small - * vct_platinumavc_onenand - * vct_platinumavc_onenand_small - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */ -#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) - -#define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (1 << 20) -#define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10) -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND) -#define CONFIG_VCT_NOR -#endif - -/* - * UART - */ -#ifdef CONFIG_VCT_PLATINUMAVC -#define UART_1_BASE 0xBDC30000 -#else -#define UART_1_BASE 0xBF89C000 -#endif - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 UART_1_BASE -#define CONFIG_SYS_NS16550_CLK 921600 - -/* - * SDRAM - */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_MBYTES_SDRAM 128 -#define CONFIG_SYS_MEMTEST_START 0x80200000 -#define CONFIG_SYS_MEMTEST_END 0x80400000 -#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */ - -#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) -#define CONFIG_NET_RETRY_COUNT 20 -#endif - -/* - * Commands - */ -#if defined(CONFIG_CMD_USB) - -/* - * USB/EHCI - */ -#define CONFIG_USB_EHCI_VCT /* on VCT platform */ -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_IS_TDI -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */ -#endif /* CONFIG_CMD_USB */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * FLASH and environment organization - */ -#if defined(CONFIG_VCT_NOR) -#define CONFIG_FLASH_NOT_MEM_MAPPED - -/* - * We need special accessor functions for the CFI FLASH driver. This - * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option. - */ -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS - -/* - * For the non-memory-mapped NOR FLASH, we need to define the - * NOR FLASH area. This can't be detected via the addr2info() - * function, since we check for flash access in the very early - * U-Boot code, before the NOR FLASH is detected. - */ -#define CONFIG_FLASH_BASE 0xb0000000 -#define CONFIG_FLASH_END 0xbfffffff - -/* - * CFI driver settings - */ -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ - -#define CONFIG_SYS_FLASH_BASE 0xb0000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#ifdef CONFIG_ENV_IS_IN_FLASH -/* Address and size of Redundant Environment Sector */ -#endif /* CONFIG_ENV_IS_IN_FLASH */ -#endif /* CONFIG_VCT_NOR */ - -#if defined(CONFIG_VCT_ONENAND) -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SYS_ONENAND_BASE 0x00000000 /* this is not real address */ -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#endif /* CONFIG_VCT_ONENAND */ - -/* - * I2C/EEPROM - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7f - -/* - * Software (bit-bang) I2C driver configuration - */ -#define CONFIG_SYS_GPIO_I2C_SCL 11 -#define CONFIG_SYS_GPIO_I2C_SDA 10 - -#ifndef __ASSEMBLY__ -int vct_gpio_dir(int pin, int dir); -void vct_gpio_set(int pin, int val); -int vct_gpio_get(int pin); -#endif - -#define I2C_INIT vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1) -#define I2C_ACTIVE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1) -#define I2C_TRISTATE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0) -#define I2C_READ vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA) -#define I2C_SDA(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit) -#define I2C_SCL(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit) -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -/* CAT24WC32 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_BOOTCOMMAND "run test3" - -/* - * UBI configuration - */ - -/* - * We need a small, stripped down image to fit into the first 128k OneNAND - * erase block (gzipped). This image only needs basic commands for FLASH - * (NOR/OneNAND) usage and Linux kernel booting. - */ -#if defined(CONFIG_VCT_SMALL_IMAGE) -#undef CONFIG_SYS_I2C_SOFT -#undef CONFIG_SOURCE -#undef CONFIG_TIMESTAMP -#endif /* CONFIG_VCT_SMALL_IMAGE */ - -#endif /* __CONFIG_H */ diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h index 58d8b515be5..1cc89c54857 100644 --- a/include/dt-bindings/clock/stm32fx-clock.h +++ b/include/dt-bindings/clock/stm32fx-clock.h @@ -1,9 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * stm32fx-clock.h * * Copyright (C) 2016 STMicroelectronics * Author: Gabriel Fernandez for STMicroelectronics. - * License terms: GNU General Public License (GPL), version 2 */ /* @@ -54,7 +54,10 @@ #define CLK_I2C3 28 #define CLK_I2C4 29 #define CLK_LPTIMER 30 - -#define END_PRIMARY_CLK_F7 31 +#define CLK_PLL_SRC 31 +#define CLK_DFSDM1 32 +#define CLK_ADFSDM1 33 +#define CLK_F769_DSI 34 +#define END_PRIMARY_CLK_F7 35 #endif diff --git a/include/dt-bindings/mfd/st,stpmic1.h b/include/dt-bindings/mfd/st,stpmic1.h index b2d6c83462a..321cd08797d 100644 --- a/include/dt-bindings/mfd/st,stpmic1.h +++ b/include/dt-bindings/mfd/st,stpmic1.h @@ -43,4 +43,8 @@ #define IT_SWIN_F 30 #define IT_SWIN_R 31 +/* BUCK MODES definitions */ +#define STPMIC1_BUCK_MODE_NORMAL 0 +#define STPMIC1_BUCK_MODE_LP 2 + #endif /* __DT_BINDINGS_STPMIC1_H__ */ diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h index c9087f5f3da..ba5cb7456ee 100644 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ b/include/dt-bindings/mfd/stm32f7-rcc.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for the STM32F7 RCC IP */ diff --git a/include/dt-bindings/mfd/stm32h7-rcc.h b/include/dt-bindings/mfd/stm32h7-rcc.h index b96b3c3ac1a..06e8476bf08 100644 --- a/include/dt-bindings/mfd/stm32h7-rcc.h +++ b/include/dt-bindings/mfd/stm32h7-rcc.h @@ -12,6 +12,7 @@ #define STM32H7_RCC_AHB3_FMC 12 #define STM32H7_RCC_AHB3_QUADSPI 14 #define STM32H7_RCC_AHB3_SDMMC1 16 +#define STM32H7_RCC_AHB3_CPU 31 #define STM32H7_RCC_AHB3_CPU1 31 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) @@ -56,7 +57,6 @@ #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) - /* APB3 */ #define STM32H7_RCC_APB3_LTDC 3 #define STM32H7_RCC_APB3_DSI 4 diff --git a/include/usb.h b/include/usb.h index bcad552f85f..efb67ea33ff 100644 --- a/include/usb.h +++ b/include/usb.h @@ -242,6 +242,12 @@ int usb_host_eth_scan(int mode); #ifdef CONFIG_USB_KEYBOARD +/* + * USB Keyboard reports are 8 bytes in boot protocol. + * Appendix B of HID Device Class Definition 1.11 + */ +#define USB_KBD_BOOT_REPORT_SIZE 8 + int drv_usb_kbd_init(void); int usb_kbd_deregister(int force); diff --git a/test/dm/usb.c b/test/dm/usb.c index ef454b0ae58..e396c2a0ea1 100644 --- a/test/dm/usb.c +++ b/test/dm/usb.c @@ -15,6 +15,12 @@ #include <dm/uclass-internal.h> #include <test/ut.h> +struct keyboard_test_data { + const char modifiers; + const char scancode; + const char result[6]; +}; + /* Test that sandbox USB works correctly */ static int dm_test_usb_base(struct unit_test_state *uts) { @@ -115,9 +121,263 @@ static int dm_test_usb_stop(struct unit_test_state *uts) } DM_TEST(dm_test_usb_stop, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); +/** + * dm_test_usb_keyb() - test USB keyboard driver + * + * This test copies USB keyboard scan codes into the key buffer of the USB + * keyboard emulation driver. These are picked up during emulated interrupts + * by the USB keyboard driver and converted to characters and escape sequences. + * The test then reads and verifies these characters and escape sequences from + * the standard input. + * + * TODO: The following features are not yet tested: + * + * * LED status + * * caps-lock + * * num-lock + * * numerical pad keys + * + * TODO: The following features are not yet implemented by the USB keyboard + * driver and therefore not tested: + * + * * modifiers for non-alpha-numeric keys, e.g. <SHIFT><TAB> and <ALT><F4> + * * some special keys, e.g. <PRINT> + * * some modifiers, e.g. <ALT> and <META> + * * alternative keyboard layouts + * + * @uts: unit test state + * Return: 0 on success + */ static int dm_test_usb_keyb(struct unit_test_state *uts) { struct udevice *dev; + const struct keyboard_test_data *pos; + const struct keyboard_test_data kbd_test_data[] = { + /* <A> */ + {0x00, 0x04, "a"}, + /* <B> */ + {0x00, 0x05, "b"}, + /* <C> */ + {0x00, 0x06, "c"}, + /* <D> */ + {0x00, 0x07, "d"}, + /* <E> */ + {0x00, 0x08, "e"}, + /* <F> */ + {0x00, 0x09, "f"}, + /* <G> */ + {0x00, 0x0a, "g"}, + /* <H> */ + {0x00, 0x0b, "h"}, + /* <I> */ + {0x00, 0x0c, "i"}, + /* <J> */ + {0x00, 0x0d, "j"}, + /* <K> */ + {0x00, 0x0e, "k"}, + /* <L> */ + {0x00, 0x0f, "l"}, + /* <M> */ + {0x00, 0x10, "m"}, + /* <N> */ + {0x00, 0x11, "n"}, + /* <O> */ + {0x00, 0x12, "o"}, + /* <P> */ + {0x00, 0x13, "p"}, + /* <Q> */ + {0x00, 0x14, "q"}, + /* <R> */ + {0x00, 0x15, "r"}, + /* <S> */ + {0x00, 0x16, "s"}, + /* <T> */ + {0x00, 0x17, "t"}, + /* <U> */ + {0x00, 0x18, "u"}, + /* <V> */ + {0x00, 0x19, "v"}, + /* <W> */ + {0x00, 0x1a, "w"}, + /* <X> */ + {0x00, 0x1b, "x"}, + /* <Y> */ + {0x00, 0x1c, "y"}, + /* <Z> */ + {0x00, 0x1d, "z"}, + + /* <LEFT-SHIFT><A> */ + {0x02, 0x04, "A"}, + /* <RIGHT-SHIFT><Z> */ + {0x20, 0x1d, "Z"}, + + /* <LEFT-CONTROL><A> */ + {0x01, 0x04, "\x01"}, + /* <RIGHT-CONTROL><Z> */ + {0x10, 0x1d, "\x1a"}, + + /* <1> */ + {0x00, 0x1e, "1"}, + /* <2> */ + {0x00, 0x1f, "2"}, + /* <3> */ + {0x00, 0x20, "3"}, + /* <4> */ + {0x00, 0x21, "4"}, + /* <5> */ + {0x00, 0x22, "5"}, + /* <6> */ + {0x00, 0x23, "6"}, + /* <7> */ + {0x00, 0x24, "7"}, + /* <8> */ + {0x00, 0x25, "8"}, + /* <9> */ + {0x00, 0x26, "9"}, + /* <0> */ + {0x00, 0x27, "0"}, + + /* <LEFT-SHIFT><1> */ + {0x02, 0x1e, "!"}, + /* <RIGHT-SHIFT><2> */ + {0x20, 0x1f, "@"}, + /* <LEFT-SHIFT><3> */ + {0x02, 0x20, "#"}, + /* <RIGHT-SHIFT><4> */ + {0x20, 0x21, "$"}, + /* <LEFT-SHIFT><5> */ + {0x02, 0x22, "%"}, + /* <RIGHT-SHIFT><6> */ + {0x20, 0x23, "^"}, + /* <LEFT-SHIFT><7> */ + {0x02, 0x24, "&"}, + /* <RIGHT-SHIFT><8> */ + {0x20, 0x25, "*"}, + /* <LEFT-SHIFT><9> */ + {0x02, 0x26, "("}, + /* <RIGHT-SHIFT><0> */ + {0x20, 0x27, ")"}, + + /* <ENTER> */ + {0x00, 0x28, "\r"}, + /* <ESCAPE> */ + {0x00, 0x29, "\x1b"}, + /* <BACKSPACE> */ + {0x00, 0x2a, "\x08"}, + /* <TAB> */ + {0x00, 0x2b, "\x09"}, + /* <SPACE> */ + {0x00, 0x2c, " "}, + /* <MINUS> */ + {0x00, 0x2d, "-"}, + /* <EQUAL> */ + {0x00, 0x2e, "="}, + /* <LEFT BRACE> */ + {0x00, 0x2f, "["}, + /* <RIGHT BRACE> */ + {0x00, 0x30, "]"}, + /* <BACKSLASH> */ + {0x00, 0x31, "\\"}, + /* <HASH-TILDE> */ + {0x00, 0x32, "#"}, + /* <SEMICOLON> */ + {0x00, 0x33, ";"}, + /* <APOSTROPHE> */ + {0x00, 0x34, "'"}, + /* <GRAVE> */ + {0x00, 0x35, "`"}, + /* <COMMA> */ + {0x00, 0x36, ","}, + /* <DOT> */ + {0x00, 0x37, "."}, + /* <SLASH> */ + {0x00, 0x38, "/"}, + + /* <LEFT-SHIFT><ENTER> */ + {0x02, 0x28, "\r"}, + /* <RIGHT-SHIFT><ESCAPE> */ + {0x20, 0x29, "\x1b"}, + /* <LEFT-SHIFT><BACKSPACE> */ + {0x02, 0x2a, "\x08"}, + /* <RIGHT-SHIFT><TAB> */ + {0x20, 0x2b, "\x09"}, + /* <LEFT-SHIFT><SPACE> */ + {0x02, 0x2c, " "}, + /* <MINUS> */ + {0x20, 0x2d, "_"}, + /* <LEFT-SHIFT><EQUAL> */ + {0x02, 0x2e, "+"}, + /* <RIGHT-SHIFT><LEFT BRACE> */ + {0x20, 0x2f, "{"}, + /* <LEFT-SHIFT><RIGHT BRACE> */ + {0x02, 0x30, "}"}, + /* <RIGHT-SHIFT><BACKSLASH> */ + {0x20, 0x31, "|"}, + /* <LEFT-SHIFT><HASH-TILDE> */ + {0x02, 0x32, "~"}, + /* <RIGHT-SHIFT><SEMICOLON> */ + {0x20, 0x33, ":"}, + /* <LEFT-SHIFT><APOSTROPHE> */ + {0x02, 0x34, "\""}, + /* <RIGHT-SHIFT><GRAVE> */ + {0x20, 0x35, "~"}, + /* <LEFT-SHIFT><COMMA> */ + {0x02, 0x36, "<"}, + /* <RIGHT-SHIFT><DOT> */ + {0x20, 0x37, ">"}, + /* <LEFT-SHIFT><SLASH> */ + {0x02, 0x38, "?"}, +#ifdef CONFIG_USB_KEYBOARD_FN_KEYS + /* <F1> */ + {0x00, 0x3a, "\x1bOP"}, + /* <F2> */ + {0x00, 0x3b, "\x1bOQ"}, + /* <F3> */ + {0x00, 0x3c, "\x1bOR"}, + /* <F4> */ + {0x00, 0x3d, "\x1bOS"}, + /* <F5> */ + {0x00, 0x3e, "\x1b[15~"}, + /* <F6> */ + {0x00, 0x3f, "\x1b[17~"}, + /* <F7> */ + {0x00, 0x40, "\x1b[18~"}, + /* <F8> */ + {0x00, 0x41, "\x1b[19~"}, + /* <F9> */ + {0x00, 0x42, "\x1b[20~"}, + /* <F10> */ + {0x00, 0x43, "\x1b[21~"}, + /* <F11> */ + {0x00, 0x44, "\x1b[23~"}, + /* <F12> */ + {0x00, 0x45, "\x1b[24~"}, + /* <INSERT> */ + {0x00, 0x49, "\x1b[2~"}, + /* <HOME> */ + {0x00, 0x4a, "\x1b[H"}, + /* <PAGE UP> */ + {0x00, 0x4b, "\x1b[5~"}, + /* <DELETE> */ + {0x00, 0x4c, "\x1b[3~"}, + /* <END> */ + {0x00, 0x4d, "\x1b[F"}, + /* <PAGE DOWN> */ + {0x00, 0x4e, "\x1b[6~"}, + /* <RIGHT> */ + {0x00, 0x4f, "\x1b[C"}, + /* <LEFT> */ + {0x00, 0x50, "\x1b[D"}, + /* <DOWN> */ + {0x00, 0x51, "\x1b[B"}, + /* <UP> */ + {0x00, 0x52, "\x1b[A"}, +#endif /* CONFIG_USB_KEYBOARD_FN_KEYS */ + + /* End of list */ + {0x00, 0x00, "\0"} + }; + state_set_skip_delays(true); ut_assertok(usb_init()); @@ -129,16 +389,24 @@ static int dm_test_usb_keyb(struct unit_test_state *uts) &dev)); /* - * Add a string to the USB keyboard buffer - it should appear in - * stdin + * Add scan codes to the USB keyboard buffer. They should appear as + * corresponding characters and escape sequences in stdin. */ - ut_assertok(sandbox_usb_keyb_add_string(dev, "ab")); - ut_asserteq(1, tstc()); - ut_asserteq('a', getc()); - ut_asserteq(1, tstc()); - ut_asserteq('b', getc()); - ut_asserteq(0, tstc()); + for (pos = kbd_test_data; pos->scancode; ++pos) { + const char *c; + char scancodes[USB_KBD_BOOT_REPORT_SIZE] = {0}; + + scancodes[0] = pos->modifiers; + scancodes[2] = pos->scancode; + ut_assertok(sandbox_usb_keyb_add_string(dev, scancodes)); + + for (c = pos->result; *c; ++c) { + ut_asserteq(1, tstc()); + ut_asserteq(*c, getc()); + } + ut_asserteq(0, tstc()); + } ut_assertok(usb_stop()); return 0; |