diff options
| -rw-r--r-- | arch/riscv/config.mk | 3 | ||||
| -rw-r--r-- | arch/riscv/cpu/ax25/cache.c | 22 | ||||
| -rw-r--r-- | arch/riscv/lib/cache.c | 14 | ||||
| -rw-r--r-- | arch/riscv/lib/interrupts.c | 3 | ||||
| -rw-r--r-- | examples/standalone/riscv.lds | 40 | ||||
| -rw-r--r-- | examples/standalone/stubs.c | 21 | ||||
| -rw-r--r-- | include/configs/qemu-riscv.h | 2 |
7 files changed, 49 insertions, 56 deletions
diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index ff4fe64001..84654eb3ed 100644 --- a/arch/riscv/config.mk +++ b/arch/riscv/config.mk @@ -23,8 +23,7 @@ PLATFORM_LDFLAGS += -m $(64bit-emul) EFI_LDS := elf_riscv64_efi.lds endif -CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 -LDFLAGS_STANDALONE += -T $(srctree)/examples/standalone/riscv.lds +CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 PLATFORM_CPPFLAGS += -ffixed-gp -fpic PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections \ diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 8d6ae170b8..228fc55f56 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -6,6 +6,28 @@ #include <common.h> +void flush_dcache_all(void) +{ + /* + * Andes' AX25 does not have a coherence agent. U-Boot must use data + * cache flush and invalidate functions to keep data in the system + * coherent. + * The implementation of the fence instruction in the AX25 flushes the + * data cache and is used for this purpose. + */ + asm volatile ("fence" ::: "memory"); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + void icache_enable(void) { #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index ae5c60716f..5437a122a1 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -11,13 +11,12 @@ void invalidate_icache_all(void) asm volatile ("fence.i" ::: "memory"); } -void flush_dcache_all(void) +__weak void flush_dcache_all(void) { - asm volatile ("fence" :::"memory"); } -void flush_dcache_range(unsigned long start, unsigned long end) + +__weak void flush_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); } void invalidate_icache_range(unsigned long start, unsigned long end) @@ -29,9 +28,8 @@ void invalidate_icache_range(unsigned long start, unsigned long end) invalidate_icache_all(); } -void invalidate_dcache_range(unsigned long start, unsigned long end) +__weak void invalidate_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); } void cache_flush(void) @@ -42,8 +40,8 @@ void cache_flush(void) void flush_cache(unsigned long addr, unsigned long size) { - invalidate_icache_all(); - flush_dcache_all(); + invalidate_icache_range(addr, addr + size); + flush_dcache_range(addr, addr + size); } __weak void icache_enable(void) diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index e185933b01..74c1e561c7 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -37,7 +37,8 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) printf("exception code: %ld , %s , epc %lx , ra %lx\n", code, exception_code[code], epc, regs->ra); } else { - printf("Reserved\n"); + printf("reserved exception code: %ld , epc %lx , ra %lx\n", + code, epc, regs->ra); } hang(); diff --git a/examples/standalone/riscv.lds b/examples/standalone/riscv.lds deleted file mode 100644 index 9a25861052..0000000000 --- a/examples/standalone/riscv.lds +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation <rick@andestech.com> - */ - -OUTPUT_ARCH(riscv) -ENTRY(_start) -SECTIONS -{ - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .data : { - __global_pointer$ = . + 0x800; - *(.data) - } - - . = ALIGN(4); - - .got : { - __got_start = .; - *(.got) - __got_end = .; - } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - __bss_end = .; - - . = ALIGN(4); - .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } - - _end = .; -} diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index fadde669fa..0827bde35e 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -174,16 +174,27 @@ gd_t *global_data; : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "$r16"); #elif defined(CONFIG_RISCV) /* - * t7 holds the pointer to the global_data. gp is call clobbered. + * gp holds the pointer to the global_data. t0 is call clobbered. */ +#ifdef CONFIG_ARCH_RV64I #define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ -" lw x19, %0(gp)\n" \ -" lw x19, %1(x19)\n" \ -" jr x19\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "x19"); +" ld t0, %0(gp)\n" \ +" ld t0, %1(t0)\n" \ +" jr t0\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t0"); +#else +#define EXPORT_FUNC(f, a, x, ...) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" lw t0, %0(gp)\n" \ +" lw t0, %1(t0)\n" \ +" jr t0\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t0"); +#endif #elif defined(CONFIG_ARC) /* * r25 holds the pointer to the global_data. r10 is call clobbered. diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index b29d155d09..2588c5a0b2 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -17,6 +17,8 @@ #define CONFIG_SYS_BOOTM_LEN SZ_16M +#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 + /* Environment options */ #define CONFIG_ENV_SIZE SZ_4K |