diff options
| -rw-r--r-- | arch/arm/Kconfig | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 13 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap3/omap.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/omap3/board.c | 10 |
4 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0a05662e7ce..6f4c8ac8684 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -43,6 +43,9 @@ config ARM_ERRATA_621766 config ARM_ERRATA_716044 bool +config ARM_ERRATA_725233 + bool + config ARM_ERRATA_742230 bool @@ -638,6 +641,7 @@ config OMAP34XX select ARM_ERRATA_430973 select ARM_ERRATA_454179 select ARM_ERRATA_621766 + select ARM_ERRATA_725233 select USE_TINY_PRINTF imply SPL_EXT_SUPPORT imply SPL_FAT_SUPPORT diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7eee54ba700..1a6aee94424 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -270,6 +270,19 @@ skip_errata_430973: skip_errata_621766: #endif +#ifdef CONFIG_ARM_ERRATA_725233 + cmp r2, #0x21 @ Only on < r2p1 (Cortex A8) + bge skip_errata_725233 + + mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR + orr r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_l2aux_ctrl + pop {r1-r5} @ Restore the cpu info - fall through + +skip_errata_725233: +#endif + mov pc, r5 @ back to my caller ENDPROC(cpu_init_cp15) diff --git a/arch/arm/include/asm/arch-omap3/omap.h b/arch/arm/include/asm/arch-omap3/omap.h index 91d73c2f1d6..db763e49a32 100644 --- a/arch/arm/include/asm/arch-omap3/omap.h +++ b/arch/arm/include/asm/arch-omap3/omap.h @@ -243,6 +243,7 @@ struct gpio { * ROM code API related flags */ #define OMAP3_GP_ROMCODE_API_L2_INVAL 1 +#define OMAP3_GP_ROMCODE_API_WRITE_L2ACR 2 #define OMAP3_GP_ROMCODE_API_WRITE_ACR 3 /* diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index a727226563c..f1436fbf519 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -364,6 +364,16 @@ void __weak omap3_set_aux_cr_secure(u32 acr) (u32 *)&emu_romcode_params); } +void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, + u32 cpu_rev_comb, u32 cpu_variant, + u32 cpu_rev) +{ + if (get_device_type() == GP_DEVICE) + omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl); + + /* L2 Cache Auxiliary Control Register is not banked */ +} + void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, u32 cpu_variant, u32 cpu_rev) { |