diff options
159 files changed, 4798 insertions, 2790 deletions
diff --git a/arch/arm/cpu/armv7/vf610/Kconfig b/arch/arm/cpu/armv7/vf610/Kconfig index 13905b5281f..5d485a3ce24 100644 --- a/arch/arm/cpu/armv7/vf610/Kconfig +++ b/arch/arm/cpu/armv7/vf610/Kconfig @@ -23,6 +23,7 @@ config TARGET_BK4R1 bool "BK4r1" select SYS_FSL_ERRATUM_ESDHC135 select SYS_FSL_ERRATUM_ESDHC_A001 + select BOARD_LATE_INIT endchoice diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index cbd3391918c..90fa695e98e 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -252,7 +252,7 @@ U_BOOT_CMD( ); #ifdef CONFIG_FEC_MXC -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +__weak void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; struct fuse_bank *bank = &ocotp->bank[4]; @@ -375,3 +375,25 @@ void enable_caches(void) mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option); } #endif + +#ifdef CONFIG_SYS_I2C_MXC +/* i2c_num can be from 0 - 3 */ +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + + switch (i2c_num) { + case 0: + clrsetbits_le32(&ccm->ccgr4, CCM_CCGR4_I2C0_CTRL_MASK, + CCM_CCGR4_I2C0_CTRL_MASK); + case 2: + clrsetbits_le32(&ccm->ccgr10, CCM_CCGR10_I2C2_CTRL_MASK, + CCM_CCGR10_I2C2_CTRL_MASK); + break; + default: + return -EINVAL; + } + + return 0; +} +#endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8167cdb4e85..0aee8dfde00 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -492,16 +492,20 @@ dtb-$(CONFIG_MACH_SUN9I) += \ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ vf610-colibri.dtb \ vf610-twr.dtb \ - pcm052.dtb \ - bk4r1.dtb + vf610-pcm052.dtb \ + vf610-bk4r1.dtb dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \ imx53-kp.dtb dtb-$(CONFIG_MX6Q) += \ + imx6-apalis.dtb \ imx6q-display5.dtb \ imx6q-logicpd.dtb +dtb-$(CONFIG_TARGET_TBS2910) += \ + imx6q-tbs2910.dtb + dtb-$(CONFIG_MX6QDL) += \ imx6dl-icore.dtb \ imx6dl-icore-mipi.dtb \ @@ -518,6 +522,9 @@ dtb-$(CONFIG_MX6QDL) += \ imx6qp-sabreauto.dtb \ imx6qp-sabresd.dtb +dtb-$(CONFIG_TARGET_WANDBOARD) += \ + imx6dl-wandboard-revb1.dtb + dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb @@ -543,6 +550,9 @@ dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ imx6ull-colibri.dtb \ +dtb-$(CONFIG_ARCH_MX6) += \ + imx6-colibri.dtb + dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ imx7d-sdb-qspi.dtb \ imx7-colibri-emmc.dtb \ @@ -699,6 +709,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623n-bananapi-bpi-r2.dtb \ mt7629-rfb.dtb +dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb +dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/arm/dts/bk4r1.dts b/arch/arm/dts/bk4r1.dts deleted file mode 100644 index 16c60268fba..00000000000 --- a/arch/arm/dts/bk4r1.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2016 Toradex AG - */ - -/dts-v1/; -#include "vf.dtsi" - -/ { - model = "Phytec phyCORE-Vybrid"; - compatible = "phytec,pcm052", "fsl,vf610"; - - chosen { - stdout-path = &uart1; - }; - - aliases { - spi0 = &qspi0; - }; - -}; - -&uart1 { - status = "okay"; -}; - -&qspi0 { - bus-num = <0>; - num-cs = <2>; - status = "okay"; - - qflash0: spi_flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <108000000>; - reg = <0>; - }; - - qflash1: spi_flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <66000000>; - reg = <1>; - }; -}; diff --git a/arch/arm/dts/imx53-ppd.dts b/arch/arm/dts/imx53-ppd.dts new file mode 100644 index 00000000000..f89d6f4672b --- /dev/null +++ b/arch/arm/dts/imx53-ppd.dts @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR X11 */ +/* + * Copyright 2018 General Electric Company + * Based on imx53-ppd.dts from kernel 4.20.5. + */ + +/dts-v1/; + +#include "imx53.dtsi" + +/ { + model = "General Electric CS ONE"; + compatible = "ge,imx53-cpuvo", "fsl,imx53"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_esdhc3: esdhc3grp { + fsl,pins = < + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 + MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 + MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 + MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 + MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 + >; + }; +}; + +/* eMMC */ +&esdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3>; + compatible = "fsl,esdhc"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi index e13009c8708..0fd4acc6f53 100644 --- a/arch/arm/dts/imx53.dtsi +++ b/arch/arm/dts/imx53.dtsi @@ -33,6 +33,8 @@ i2c2 = &i2c3; mmc0 = &esdhc1; mmc1 = &esdhc2; + mmc2 = &esdhc3; + mmc3 = &esdhc4; }; tzic: tz-interrupt-controller@fffc000 { @@ -86,6 +88,30 @@ bus-width = <4>; status = "disabled"; }; + + esdhc3: esdhc@50020000 { + compatible = "fsl,imx53-esdhc"; + reg = <0x50020000 0x4000>; + interrupts = <3>; + clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC3_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + esdhc4: esdhc@50024000 { + compatible = "fsl,imx53-esdhc"; + reg = <0x50024000 0x4000>; + interrupts = <4>; + clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, + <&clks IMX5_CLK_DUMMY>, + <&clks IMX5_CLK_ESDHC4_PER_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; }; iomuxc: iomuxc@53fa8000 { diff --git a/arch/arm/dts/imx6-apalis.dts b/arch/arm/dts/imx6-apalis.dts new file mode 100644 index 00000000000..b2fdfa1af42 --- /dev/null +++ b/arch/arm/dts/imx6-apalis.dts @@ -0,0 +1,730 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex AG + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "imx6q.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D"; + compatible = "toradex,apalis_imx6q", "fsl,imx6q"; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; + + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc1; + mmc2 = &usdhc2; + usb0 = &usbotg; /* required for ums */ + }; + + chosen { + stdout-path = &uart1; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* USBO1_EN */ + enable-active-high; + }; + + /* on-module USB hub */ + reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; + regulator-name = "usb_host_vbus_hub"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + enable-active-high; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; + regulator-name = "usb_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* USBH_EN */ + enable-active-high; + vin-supply = <®_usb_host_vbus_hub>; + }; +}; + +/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +/* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +/* + * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier + * board) + */ +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_recovery>; + scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +/* Apalis Serial ATA */ +&sata { + status = "okay"; +}; + +/* Apalis UART1 */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; + fsl,dte-mode; + uart-has-rtscts; + status = "okay"; +}; + +/* Apalis UART2 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_dte>; + fsl,dte-mode; + uart-has-rtscts; + status = "okay"; +}; + +/* Apalis UART3 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_dte>; + fsl,dte-mode; + status = "okay"; +}; + +/* Apalis UART4 */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_dte>; + fsl,dte-mode; + status = "okay"; +}; + +/* Apalis USBH[2|3|4] */ +&usbh1 { + dr_mode = "host"; + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Apalis USBO1 */ +&usbotg { + dr_mode = "host"; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>; + cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; /* MMC1_CD */ + disable-wp; + no-1-8-v; + status = "okay"; +}; + +/* Apalis SD1 */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* SD1_CD */ + disable-wp; + no-1-8-v; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vqmmc-supply = <®_module_3v3>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_apalis_gpio1: gpio2io04grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 + >; + }; + + pinctrl_apalis_gpio2: gpio2io05grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 + >; + }; + + pinctrl_apalis_gpio3: gpio2io06grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0 + >; + }; + + pinctrl_apalis_gpio4: gpio2io07grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 + >; + }; + + pinctrl_apalis_gpio5: gpio6io10grp { + fsl,pins = < + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0 + >; + }; + + pinctrl_apalis_gpio6: gpio6io09grp { + fsl,pins = < + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0 + >; + }; + + pinctrl_apalis_gpio7: gpio1io02grp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 + >; + }; + + pinctrl_apalis_gpio8: gpio1io06grp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_cam_mclk: cammclkgrp { + fsl,pins = < + /* CAM sys_mclk */ + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 + /* SPI1 cs */ + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + /* SPI2 cs */ + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + /* Ethernet PHY reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 + /* Ethernet PHY interrupt */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio_bl_on: gpioblon { + fsl,pins = < + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpio1io04grp { + fsl,pins = < + /* Power button */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hdmi_ddc: hdmiddcgrp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_recovery: i2c3recoverygrp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1 + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1 + >; + }; + + pinctrl_ipu1_lcdif: ipu1lcdifgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 + /* DE */ + MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 + /* HSync */ + MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 + /* VSync */ + MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 + MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 + MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 + MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 + MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 + MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 + MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 + MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 + MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 + MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 + MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 + MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 + MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 + MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 + MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 + MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 + MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 + MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 + MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 + MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 + MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 + MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 + MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 + MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 + MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 + >; + }; + + pinctrl_ipu2_vdac: ipu2vdacgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1 + MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1 + MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1 + MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1 + MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9 + MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9 + MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9 + MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9 + MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9 + MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9 + MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9 + MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9 + MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9 + MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9 + MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9 + MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9 + MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9 + MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9 + MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9 + MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9 + >; + }; + + pinctrl_mmc_cd: gpiommccdgrp { + fsl,pins = < + /* MMC1 CD */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { + fsl,pins = < + /* USBH_EN */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058 + >; + }; + + pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp { + fsl,pins = < + /* USBH_HUB_EN */ + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058 + >; + }; + + pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp { + fsl,pins = < + /* USBO1 power en */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058 + >; + }; + + pinctrl_reset_moci: gpioresetmocigrp { + fsl,pins = < + /* RESET_MOCI control */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058 + >; + }; + + pinctrl_sd_cd: gpiosdcdgrp { + fsl,pins = < + /* SD1 CD */ + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 + MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_touch_int: gpiotouchintgrp { + fsl,pins = < + /* STMPE811 interrupt */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + pinctrl_uart1_dce: uart1dcegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + /* DTE mode */ + pinctrl_uart1_dte: uart1dtegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 + >; + }; + + /* Additional DTR, DSR, DCD */ + pinctrl_uart1_ctrl: uart1ctrlgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 + >; + }; + + pinctrl_uart2_dce: uart2dcegrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + + /* DTE mode */ + pinctrl_uart2_dte: uart2dtegrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4_dce: uart4dcegrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + /* DTE mode */ + pinctrl_uart4_dte: uart4dtegrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5_dce: uart5dcegrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + /* DTE mode */ + pinctrl_uart5_dte: uart5dtegrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1_4bit: usdhc1grp_4bit { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + >; + }; + + pinctrl_usdhc1_8bit: usdhc1grp_8bit { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 + MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 + MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 + MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + /* eMMC reset */ + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 + >; + }; +}; diff --git a/arch/arm/dts/imx6-colibri.dts b/arch/arm/dts/imx6-colibri.dts new file mode 100644 index 00000000000..5c9f1f0d2be --- /dev/null +++ b/arch/arm/dts/imx6-colibri.dts @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex AG + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "imx6dl.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S"; + compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; + + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; + + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc1; + usb0 = &usbotg; /* required for ums */ + }; + + chosen { + stdout-path = &uart1; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; + regulator-name = "usb_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; /* USBH_PEN */ + }; +}; + +/* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + /* vgen1: unused */ + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vgen3: unused */ + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +/* + * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) + */ +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_recovery>; + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; + fsl,dte-mode; + uart-has-rtscts; + status = "okay"; +}; + +/* Colibri UART_B */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_dte>; + fsl,dte-mode; + uart-has-rtscts; + status = "okay"; +}; + +/* Colibri UART_C */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_dte>; + fsl,dte-mode; + status = "okay"; +}; + +/* Colibri USBH */ +&usbh1 { + dr_mode = "host"; + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Colibri USBC */ +&usbotg { + dr_mode = "host"; + status = "okay"; +}; + +/* Colibri MMC */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ + disable-wp; + vqmmc-supply = <®_module_3v3>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vqmmc-supply = <®_module_3v3>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + /* SPI CS */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) + >; + }; + + pinctrl_gpio_bl_on: gpioblon { + fsl,pins = < + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 + >; + }; + + pinctrl_hdmi_ddc: hdmiddcgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3_recovery: i2c3recoverygrp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 + >; + }; + + pinctrl_ipu1_lcdif: ipu1lcdifgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 + >; + }; + + pinctrl_mmc_cd: gpiommccd { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { + fsl,pins = < + /* SODIMM 129 USBH_PEN */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 + >; + }; + + pinctrl_uart1_dce: uart1dcegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + /* DTE mode */ + pinctrl_uart1_dte: uart1dtegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 + >; + }; + + /* Additional DTR, DSR, DCD */ + pinctrl_uart1_ctrl: uart1ctrlgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 + >; + }; + + pinctrl_uart2_dte: uart2dtegrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3_dte: uart3dtegrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + /* eMMC reset */ + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-wandboard-revb1.dts b/arch/arm/dts/imx6dl-wandboard-revb1.dts new file mode 100644 index 00000000000..738db4fc770 --- /dev/null +++ b/arch/arm/dts/imx6dl-wandboard-revb1.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-wandboard-revb1.dtsi" + +/ { + model = "Wandboard i.MX6 Dual Lite Board rev B1"; + compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; + + memory@10000000 { + reg = <0x10000000 0x40000000>; + }; +}; diff --git a/arch/arm/dts/imx6q-bx50v3.dts b/arch/arm/dts/imx6q-bx50v3.dts new file mode 100644 index 00000000000..deaec635093 --- /dev/null +++ b/arch/arm/dts/imx6q-bx50v3.dts @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR X11 */ +/* + * Copyright 2015 Timesys Corporation. + * Copyright 2018 General Electric Company + * Based on imx6q-ba16.dtsi and imx6q-bx50v3.dtsi from kernel 4.20.5. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "General Electric Bx50v3"; + compatible = "ge,imx6q-bx50v3", "advantech,imx6q-ba16", "fsl,imx6q"; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* SPI1 CS */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_reset: usdhc3grp-reset { + fsl,pins = < + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9 + >; + }; +}; + +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc4 { + status = "disabled"; +}; + +/* SPI NOR */ +&ecspi1 { + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: n25q032@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; diff --git a/arch/arm/dts/imx6q-tbs2910.dts b/arch/arm/dts/imx6q-tbs2910.dts new file mode 100644 index 00000000000..21e62c0cabb --- /dev/null +++ b/arch/arm/dts/imx6q-tbs2910.dts @@ -0,0 +1,394 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2014-2019 Soeren Moch <smoch@web.de> + +/dts-v1/; + +#include "imx6q.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "TBS2910 Matrix ARM mini PC"; + compatible = "tbs,imx6q-tbs2910", "fsl,imx6q"; + + chosen { + stdout-path = &uart1; + }; + + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc3; + mmc2 = &usdhc4; + usb0 = &usbotg; + }; + + memory@10000000 { + reg = <0x10000000 0x80000000>; + }; + + fan { + compatible = "gpio-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_fan>; + gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 3000 1>; + }; + + ir_recv { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + blue { + label = "blue_status_led"; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + sound-sgtl5000 { + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + compatible = "fsl,imx-audio-sgtl5000"; + model = "On-board Codec"; + mux-ext-port = <3>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "On-board SPDIF"; + spdif-controller = <&spdif>; + spdif-out; + }; +}; + +&audmux { + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: sgtl5000@a { + clocks = <&clks IMX6QDL_CLK_CKO>; + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + rtc: ds1307@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sata { + fsl,transmit-level-mV = <1104>; + fsl,transmit-boost-mdB = <3330>; + fsl,transmit-atten-16ths = <16>; + fsl,receive-eq-mdB = <3000>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_5p0v>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_5p0v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + voltage-ranges = <3300 3300>; + no-1-8-v; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + voltage-ranges = <3300 3300>; + no-1-8-v; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + voltage-ranges = <3300 3300>; + non-removable; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059 + >; + }; + + pinctrl_gpio_fan: gpiofangrp { + fsl,pins = < + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ir: irgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/dts/imx6qdl-wandboard-revb1.dtsi new file mode 100644 index 00000000000..855dc6f9df7 --- /dev/null +++ b/arch/arm/dts/imx6qdl-wandboard-revb1.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include "imx6qdl-wandboard.dtsi" + +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; + + imx6qdl-wandboard { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x0f0b0 /* WL_REF_ON */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x0f0b0 /* WL_RST_N */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */ + >; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6qdl-wandboard.dtsi b/arch/arm/dts/imx6qdl-wandboard.dtsi new file mode 100644 index 00000000000..4d03d49fde9 --- /dev/null +++ b/arch/arm/dts/imx6qdl-wandboard.dtsi @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + sound { + compatible = "fsl,imx6-wandboard-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6-wandboard-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotgvbus>; + gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c1>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: sgtl5000@a { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mclk>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks IMX6QDL_CLK_CKO>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + lrclk-strength = <3>; + }; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx6qdl-wandboard { + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_mclk: mclkgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usbotgvbus: usbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi index e4daf150881..c0a94780087 100644 --- a/arch/arm/dts/imx6qdl.dtsi +++ b/arch/arm/dts/imx6qdl.dtsi @@ -145,6 +145,7 @@ compatible = "simple-bus"; interrupt-parent = <&gpc>; ranges; + u-boot,dm-pre-reloc; dma_apbh: dma-apbh@110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; @@ -1261,6 +1262,7 @@ <&clks IMX6QDL_CLK_IPU1_DI1>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; + u-boot,dm-pre-reloc; ipu1_csi0: port@0 { reg = <0>; diff --git a/arch/arm/dts/vf-colibri-u-boot.dtsi b/arch/arm/dts/vf-colibri-u-boot.dtsi new file mode 100644 index 00000000000..db86739805d --- /dev/null +++ b/arch/arm/dts/vf-colibri-u-boot.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 + +/ { + soc { + u-boot,dm-pre-reloc; + }; +}; + +&aips0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_ddr { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart0 { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/vf-colibri.dtsi b/arch/arm/dts/vf-colibri.dtsi index 923dc2451cd..5ce17076e9c 100644 --- a/arch/arm/dts/vf-colibri.dtsi +++ b/arch/arm/dts/vf-colibri.dtsi @@ -1,18 +1,37 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Copyright 2014 Toradex AG + * Copyright 2014-2019 Toradex AG */ + +/dts-v1/; #include "vf.dtsi" +#include "vf610-pinfunc.h" / { chosen { stdout-path = &uart0; }; + + aliases { + usb0 = &ehci0; /* required for ums */ + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN */ + }; }; &dspi1 { - status = "okay"; bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; + status = "okay"; spi_cmd: sspi@0 { reg = <0>; @@ -29,8 +48,183 @@ &ehci1 { dr_mode = "host"; status = "okay"; + vbus-supply = <®_usbh_vbus>; +}; + +&esdhc1 { + bus-width = <4>; + cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc: m41t0m6@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ddr>; + + pinctrl_ddr: ddrgrp { + fsl,pins = < + VF610_PAD_DDR_A15__DDR_A_15 0x180 + VF610_PAD_DDR_A14__DDR_A_14 0x180 + VF610_PAD_DDR_A13__DDR_A_13 0x180 + VF610_PAD_DDR_A12__DDR_A_12 0x180 + VF610_PAD_DDR_A11__DDR_A_11 0x180 + VF610_PAD_DDR_A10__DDR_A_10 0x180 + VF610_PAD_DDR_A9__DDR_A_9 0x180 + VF610_PAD_DDR_A8__DDR_A_8 0x180 + VF610_PAD_DDR_A7__DDR_A_7 0x180 + VF610_PAD_DDR_A6__DDR_A_6 0x180 + VF610_PAD_DDR_A5__DDR_A_5 0x180 + VF610_PAD_DDR_A4__DDR_A_4 0x180 + VF610_PAD_DDR_A3__DDR_A_3 0x180 + VF610_PAD_DDR_A2__DDR_A_2 0x180 + VF610_PAD_DDR_A1__DDR_A_1 0x180 + VF610_PAD_DDR_A0__DDR_A_0 0x180 + VF610_PAD_DDR_BA2__DDR_BA_2 0x180 + VF610_PAD_DDR_BA1__DDR_BA_1 0x180 + VF610_PAD_DDR_BA0__DDR_BA_0 0x180 + VF610_PAD_DDR_CAS__DDR_CAS_B 0x180 + VF610_PAD_DDR_CKE__DDR_CKE_0 0x180 + VF610_PAD_DDR_CLK__DDR_CLK_0 0x180 + VF610_PAD_DDR_CS__DDR_CS_B_0 0x180 + VF610_PAD_DDR_D15__DDR_D_15 0x10180 + VF610_PAD_DDR_D14__DDR_D_14 0x10180 + VF610_PAD_DDR_D13__DDR_D_13 0x10180 + VF610_PAD_DDR_D12__DDR_D_12 0x10180 + VF610_PAD_DDR_D11__DDR_D_11 0x10180 + VF610_PAD_DDR_D10__DDR_D_10 0x10180 + VF610_PAD_DDR_D9__DDR_D_9 0x10180 + VF610_PAD_DDR_D8__DDR_D_8 0x10180 + VF610_PAD_DDR_D7__DDR_D_7 0x10180 + VF610_PAD_DDR_D6__DDR_D_6 0x10180 + VF610_PAD_DDR_D5__DDR_D_5 0x10180 + VF610_PAD_DDR_D4__DDR_D_4 0x10180 + VF610_PAD_DDR_D3__DDR_D_3 0x10180 + VF610_PAD_DDR_D2__DDR_D_2 0x10180 + VF610_PAD_DDR_D1__DDR_D_1 0x10180 + VF610_PAD_DDR_D0__DDR_D_0 0x10180 + VF610_PAD_DDR_DQM1__DDR_DQM_1 0x10180 + VF610_PAD_DDR_DQM0__DDR_DQM_0 0x10180 + VF610_PAD_DDR_DQS1__DDR_DQS_1 0x10180 + VF610_PAD_DDR_DQS0__DDR_DQS_0 0x10180 + VF610_PAD_DDR_RAS__DDR_RAS_B 0x180 + VF610_PAD_DDR_WE__DDR_WE_B 0x180 + VF610_PAD_DDR_ODT1__DDR_ODT_0 0x180 + VF610_PAD_DDR_ODT0__DDR_ODT_1 0x180 + VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x180 + VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x180 + VF610_PAD_DDR_RESETB 0x180 + >; + }; + + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x33e2 + VF610_PAD_PTD6__DSPI1_SIN 0x33e1 + VF610_PAD_PTD7__DSPI1_SOUT 0x33e2 + VF610_PAD_PTD8__DSPI1_SCK 0x33e2 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTB20__GPIO_42 0x219d + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKOUT 0x30df + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30df + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30df + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30df + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30df + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30df + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30df + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30df + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30df + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30df + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + VF610_PAD_PTD23__NF_IO7 0x28df + VF610_PAD_PTD22__NF_IO6 0x28df + VF610_PAD_PTD21__NF_IO5 0x28df + VF610_PAD_PTD20__NF_IO4 0x28df + VF610_PAD_PTD19__NF_IO3 0x28df + VF610_PAD_PTD18__NF_IO2 0x28df + VF610_PAD_PTD17__NF_IO1 0x28df + VF610_PAD_PTD16__NF_IO0 0x28df + VF610_PAD_PTB24__NF_WE_B 0x28c2 + VF610_PAD_PTB25__NF_CE0_B 0x28c2 + VF610_PAD_PTB27__NF_RE_B 0x28c2 + VF610_PAD_PTC26__NF_RB_B 0x283d + VF610_PAD_PTC27__NF_ALE 0x28c2 + VF610_PAD_PTC28__NF_CLE 0x28c2 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x11af + VF610_PAD_PTB11__UART0_RX 0x11af + VF610_PAD_PTB12__UART0_RTS 0x11af + VF610_PAD_PTB13__UART0_CTS 0x11af + >; + }; + + pinctrl_usbh1_reg: gpio_usb_vbus { + fsl,pins = < + VF610_PAD_PTD4__GPIO_83 0x22ed + >; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + status = "okay"; }; &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; status = "okay"; }; diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi index ad30059b9ab..5e3b2c5b9dc 100644 --- a/arch/arm/dts/vf.dtsi +++ b/arch/arm/dts/vf.dtsi @@ -22,6 +22,10 @@ spi1 = &dspi1; ehci0 = &ehci0; ehci1 = &ehci1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; }; soc { @@ -89,6 +93,22 @@ status = "disabled"; }; + i2c0: i2c@40066000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x40066000 0x1000>; + status = "disabled"; + }; + + i2c1: i2c@40067000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x40067000 0x1000>; + status = "disabled"; + }; + iomuxc: iomuxc@40048000 { compatible = "fsl,vf610-iomuxc"; reg = <0x40048000 0x1000>; @@ -156,6 +176,48 @@ reg = <0x400b4000 0x800>; status = "disabled"; }; + + esdhc1: esdhc@400b2000 { + compatible = "fsl,esdhc"; + reg = <0x400b2000 0x1000>; + status = "disabled"; + }; + + fec0: fec@400d0000 { + compatible = "fsl,mvf600-fec"; + reg = <0x400d0000 0x1000>; + status = "disabled"; + }; + + fec1: fec@400d1000 { + compatible = "fsl,mvf600-fec"; + reg = <0x400d1000 0x1000>; + status = "disabled"; + }; + + nfc: nand@400e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-nfc"; + reg = <0x400e0000 0x4000>; + status = "disabled"; + }; + + i2c2: i2c@400e6000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x400e6000 0x1000>; + status = "disabled"; + }; + + i2c3: i2c@400e7000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x400e7000 0x1000>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/dts/vf500-colibri.dts b/arch/arm/dts/vf500-colibri.dts index 3f33d970e0e..c83a16fdcb8 100644 --- a/arch/arm/dts/vf500-colibri.dts +++ b/arch/arm/dts/vf500-colibri.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "vf-colibri.dtsi" +#include "vf-colibri-u-boot.dtsi" / { model = "Toradex Colibri VF50"; diff --git a/arch/arm/dts/vf610-bk4r1-u-boot.dtsi b/arch/arm/dts/vf610-bk4r1-u-boot.dtsi new file mode 100644 index 00000000000..088926bde2c --- /dev/null +++ b/arch/arm/dts/vf610-bk4r1-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/ { + soc { + u-boot,dm-pre-reloc; + }; +}; + +&aips0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_ddr { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/vf610-bk4r1.dts b/arch/arm/dts/vf610-bk4r1.dts new file mode 100644 index 00000000000..55cd53384a3 --- /dev/null +++ b/arch/arm/dts/vf610-bk4r1.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * (C) Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de. + * + * Copyright 2016 Toradex AG + */ + +/dts-v1/; +#include "vf610-pcm052.dtsi" +#include "vf610-pinfunc.h" + +/ { + model = "Liebherr (LVF) BK4 Vybrid Board"; + compatible = "lvf,bk4", "fsl,vf610"; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + compatible = "gpio-leds"; + + /* PTE15 PORT3[24] H6 green */ + led@0 { + label = "0"; + gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + /* PTA12 PORT0[5] H5 green */ + led@1 { + label = "1"; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + /* PTE20 PORT3[39] H4 green */ + led@2 { + label = "2"; + gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + /* PTE12 PORT3[21] H3 green */ + led@3 { + label = "3"; + gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + /* LED6 is now PRESET ETH -> PTA16 PORT0[6] H6 red */ + /* PTE9 PORT3[18] H5 red */ + led@4 { + label = "5"; + gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + /* PTE23 PORT4[0] H4 red */ + led@5 { + label = "6"; + gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + /* PTE16 PORT3[25] H3 red */ + led@6 { + label = "7"; + gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_ddr &pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* ETH control pins */ + VF610_PAD_PTE17__GPIO_122 0x1183 + VF610_PAD_PTA16__GPIO_6 0x1183 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + /* LEDS */ + VF610_PAD_PTE15__GPIO_120 0x1183 + VF610_PAD_PTA12__GPIO_5 0x1183 + VF610_PAD_PTE9__GPIO_114 0x1183 + VF610_PAD_PTE20__GPIO_125 0x1183 + VF610_PAD_PTE23__GPIO_128 0x1183 + VF610_PAD_PTE16__GPIO_121 0x1183 + >; + }; +}; diff --git a/arch/arm/dts/vf610-colibri.dts b/arch/arm/dts/vf610-colibri.dts index 0a6b937feea..7275fec279f 100644 --- a/arch/arm/dts/vf610-colibri.dts +++ b/arch/arm/dts/vf610-colibri.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "vf-colibri.dtsi" +#include "vf-colibri-u-boot.dtsi" / { model = "Toradex Colibri VF61"; diff --git a/arch/arm/dts/pcm052.dts b/arch/arm/dts/vf610-pcm052.dts index 6489fdc6f41..22026024eab 100644 --- a/arch/arm/dts/pcm052.dts +++ b/arch/arm/dts/vf610-pcm052.dts @@ -4,7 +4,7 @@ */ /dts-v1/; -#include "vf.dtsi" +#include "vf610-pcm052.dtsi" / { model = "Phytec phyCORE-Vybrid"; @@ -15,7 +15,3 @@ }; }; - -&uart1 { - status = "okay"; -}; diff --git a/arch/arm/dts/vf610-pcm052.dtsi b/arch/arm/dts/vf610-pcm052.dtsi new file mode 100644 index 00000000000..1383d03c227 --- /dev/null +++ b/arch/arm/dts/vf610-pcm052.dtsi @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * (C) Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de. + * + */ + +/dts-v1/; +#include "vf.dtsi" +#include "vf610-pinfunc.h" + +/ { + chosen { + stdout-path = &uart1; + }; + + aliases { + spi0 = &qspi0; + mmc0 = &esdhc1; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth>; + + phy-mode = "rmii"; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth1>; + + phy-mode = "rmii"; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + u-boot,i2c-offset-len = <2>; + }; + + m41t62: rtc@68 { + compatible = "st,m41t62"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ddr>; + + pinctrl_ddr: ddrgrp { + fsl,pins = < + VF610_PAD_DDR_A15__DDR_A_15 0x1c0 + VF610_PAD_DDR_A14__DDR_A_14 0x1c0 + VF610_PAD_DDR_A13__DDR_A_13 0x1c0 + VF610_PAD_DDR_A12__DDR_A_12 0x1c0 + VF610_PAD_DDR_A11__DDR_A_11 0x1c0 + VF610_PAD_DDR_A10__DDR_A_10 0x1c0 + VF610_PAD_DDR_A9__DDR_A_9 0x1c0 + VF610_PAD_DDR_A8__DDR_A_8 0x1c0 + VF610_PAD_DDR_A7__DDR_A_7 0x1c0 + VF610_PAD_DDR_A6__DDR_A_6 0x1c0 + VF610_PAD_DDR_A5__DDR_A_5 0x1c0 + VF610_PAD_DDR_A4__DDR_A_4 0x1c0 + VF610_PAD_DDR_A3__DDR_A_3 0x1c0 + VF610_PAD_DDR_A2__DDR_A_2 0x1c0 + VF610_PAD_DDR_A1__DDR_A_1 0x1c0 + VF610_PAD_DDR_A0__DDR_A_0 0x1c0 + VF610_PAD_DDR_BA2__DDR_BA_2 0x1c0 + VF610_PAD_DDR_BA1__DDR_BA_1 0x1c0 + VF610_PAD_DDR_BA0__DDR_BA_0 0x1c0 + VF610_PAD_DDR_CAS__DDR_CAS_B 0x1c0 + VF610_PAD_DDR_CKE__DDR_CKE_0 0x1c0 + VF610_PAD_DDR_CLK__DDR_CLK_0 0x101c0 + VF610_PAD_DDR_CS__DDR_CS_B_0 0x1c0 + VF610_PAD_DDR_D15__DDR_D_15 0x1c0 + VF610_PAD_DDR_D14__DDR_D_14 0x1c0 + VF610_PAD_DDR_D13__DDR_D_13 0x1c0 + VF610_PAD_DDR_D12__DDR_D_12 0x1c0 + VF610_PAD_DDR_D11__DDR_D_11 0x1c0 + VF610_PAD_DDR_D10__DDR_D_10 0x1c0 + VF610_PAD_DDR_D9__DDR_D_9 0x1c0 + VF610_PAD_DDR_D8__DDR_D_8 0x1c0 + VF610_PAD_DDR_D7__DDR_D_7 0x1c0 + VF610_PAD_DDR_D6__DDR_D_6 0x1c0 + VF610_PAD_DDR_D5__DDR_D_5 0x1c0 + VF610_PAD_DDR_D4__DDR_D_4 0x1c0 + VF610_PAD_DDR_D3__DDR_D_3 0x1c0 + VF610_PAD_DDR_D2__DDR_D_2 0x1c0 + VF610_PAD_DDR_D1__DDR_D_1 0x1c0 + VF610_PAD_DDR_D0__DDR_D_0 0x1c0 + VF610_PAD_DDR_DQM1__DDR_DQM_1 0x1c0 + VF610_PAD_DDR_DQM0__DDR_DQM_0 0x1c0 + VF610_PAD_DDR_DQS1__DDR_DQS_1 0x101c0 + VF610_PAD_DDR_DQS0__DDR_DQS_0 0x101c0 + VF610_PAD_DDR_RAS__DDR_RAS_B 0x1c0 + VF610_PAD_DDR_WE__DDR_WE_B 0x1c0 + VF610_PAD_DDR_ODT1__DDR_ODT_0 0x1c0 + VF610_PAD_DDR_ODT0__DDR_ODT_1 0x1c0 + VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x1c0 + VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x1c0 + VF610_PAD_DDR_RESETB 0x1006c + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_eth: ethgrp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30dd + VF610_PAD_PTC0__ENET_RMII0_MDC 0x30de + VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df + VF610_PAD_PTC2__ENET_RMII0_CRS 0x30dd + VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd + VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd + VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd + VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de + VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de + VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de + >; + }; + + pinctrl_eth1: eth1grp { + fsl,pins = < + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30de + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30df + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30dd + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30dd + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30dd + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30dd + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30de + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30de + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30de + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + VF610_PAD_PTA22__I2C2_SCL 0x34df + VF610_PAD_PTA23__I2C2_SDA 0x34df + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + VF610_PAD_PTD31__NF_IO15 0x28df + VF610_PAD_PTD30__NF_IO14 0x28df + VF610_PAD_PTD29__NF_IO13 0x28df + VF610_PAD_PTD28__NF_IO12 0x28df + VF610_PAD_PTD27__NF_IO11 0x28df + VF610_PAD_PTD26__NF_IO10 0x28df + VF610_PAD_PTD25__NF_IO9 0x28df + VF610_PAD_PTD24__NF_IO8 0x28df + VF610_PAD_PTD23__NF_IO7 0x28df + VF610_PAD_PTD22__NF_IO6 0x28df + VF610_PAD_PTD21__NF_IO5 0x28df + VF610_PAD_PTD20__NF_IO4 0x28df + VF610_PAD_PTD19__NF_IO3 0x28df + VF610_PAD_PTD18__NF_IO2 0x28df + VF610_PAD_PTD17__NF_IO1 0x28df + VF610_PAD_PTD16__NF_IO0 0x28df + VF610_PAD_PTB24__NF_WE_B 0x28c2 + VF610_PAD_PTB25__NF_CE0_B 0x28c2 + VF610_PAD_PTB27__NF_RE_B 0x28c2 + VF610_PAD_PTC26__NF_RB_B 0x283d + VF610_PAD_PTC27__NF_ALE 0x28c2 + VF610_PAD_PTC28__NF_CLE 0x28c2 + >; + }; + + pinctrl_qspi0: qspi0grp { + fsl,pins = < + VF610_PAD_PTD0__QSPI0_A_QSCK 0x397f + VF610_PAD_PTD1__QSPI0_A_CS0 0x397f + VF610_PAD_PTD2__QSPI0_A_DATA3 0x397f + VF610_PAD_PTD3__QSPI0_A_DATA2 0x397f + VF610_PAD_PTD4__QSPI0_A_DATA1 0x397f + VF610_PAD_PTD5__QSPI0_A_DATA0 0x397f + VF610_PAD_PTD7__QSPI0_B_QSCK 0x397f + VF610_PAD_PTD8__QSPI0_B_CS0 0x397f + VF610_PAD_PTD11__QSPI0_B_DATA1 0x397f + VF610_PAD_PTD12__QSPI0_B_DATA0 0x397f + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB4__UART1_TX 0x21a2 + VF610_PAD_PTB5__UART1_RX 0x21a1 + >; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + + status = "okay"; +}; + +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0>; + + bus-num = <0>; + num-cs = <2>; + status = "okay"; + + qflash0: spi_flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <108000000>; + reg = <0>; + }; + + qflash1: spi_flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <66000000>; + reg = <1>; + }; +}; diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h index fcad7132c87..94567190746 100644 --- a/arch/arm/dts/vf610-pinfunc.h +++ b/arch/arm/dts/vf610-pinfunc.h @@ -807,4 +807,54 @@ #define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 #define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1 +#define VF610_PAD_DDR_RESETB 0x21c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A15__DDR_A_15 0x220 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A14__DDR_A_14 0x224 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A13__DDR_A_13 0x228 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A12__DDR_A_12 0x22c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A11__DDR_A_11 0x230 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A10__DDR_A_10 0x234 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A9__DDR_A_9 0x238 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A8__DDR_A_8 0x23c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A7__DDR_A_7 0x240 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A6__DDR_A_6 0x244 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A5__DDR_A_5 0x248 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A4__DDR_A_4 0x24c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A3__DDR_A_3 0x250 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A2__DDR_A_2 0x254 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A1__DDR_A_1 0x258 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A0__DDR_A_0 0x25c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_BA2__DDR_BA_2 0x260 0x000 ALT0 0x0 +#define VF610_PAD_DDR_BA1__DDR_BA_1 0x264 0x000 ALT0 0x0 +#define VF610_PAD_DDR_BA0__DDR_BA_0 0x268 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CAS__DDR_CAS_B 0x26c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CKE__DDR_CKE_0 0x270 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CLK__DDR_CLK_0 0x274 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CS__DDR_CS_B_0 0x278 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D15__DDR_D_15 0x27c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D14__DDR_D_14 0x280 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D13__DDR_D_13 0x284 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D12__DDR_D_12 0x288 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D11__DDR_D_11 0x28c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D10__DDR_D_10 0x290 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D9__DDR_D_9 0x294 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D8__DDR_D_8 0x298 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D7__DDR_D_7 0x29c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D6__DDR_D_6 0x2a0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D5__DDR_D_5 0x2a4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D4__DDR_D_4 0x2a8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D3__DDR_D_3 0x2ac 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D2__DDR_D_2 0x2b0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D1__DDR_D_1 0x2b4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D0__DDR_D_0 0x2b8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQM1__DDR_DQM_1 0x2bc 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQM0__DDR_DQM_0 0x2c0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQS1__DDR_DQS_1 0x2c4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQS0__DDR_DQS_0 0x2c8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_RAS__DDR_RAS_B 0x2cc 0x000 ALT0 0x0 +#define VF610_PAD_DDR_WE__DDR_WE_B 0x2d0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_ODT1__DDR_ODT_0 0x2d4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x2d8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x2dc 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x2e0 0x000 ALT0 0x0 #endif diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h index 3bd73a01f3b..72184fd6083 100644 --- a/arch/arm/include/asm/arch-vf610/clock.h +++ b/arch/arm/include/asm/arch-vf610/clock.h @@ -22,6 +22,9 @@ enum mxc_clock { void enable_ocotp_clk(unsigned char enable); unsigned int mxc_get_clock(enum mxc_clock clk); u32 get_lpuart_clk(void); +#ifdef CONFIG_SYS_I2C_MXC +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); +#endif #define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 9fce49ddc64..0c9ed529338 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -200,6 +200,7 @@ struct anadig_reg { #define CCM_REG_CTRL_MASK 0xffffffff #define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) +#define CCM_CCGR0_UART2_CTRL_MASK (0x3 << 18) #define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24) #define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26) #define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8) diff --git a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h index c7da2b8a5e3..03e3cecb95a 100644 --- a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h +++ b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h @@ -10,6 +10,8 @@ #ifndef __ASM_ARCH_VF610_DDRMC_H #define __ASM_ARCH_VF610_DDRMC_H +#include <asm/arch/iomux-vf610.h> + struct ddr3_jedec_timings { u8 tinit; u32 trst_pwron; diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 5d1f63c98bf..ae0a187c4db 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -289,6 +289,8 @@ #define SRC_SRSR_WDOG_M4 (0x1 << 4) #define SRC_SRSR_WDOG_A5 (0x1 << 3) #define SRC_SRSR_POR_RST (0x1 << 0) +#define SRC_SBMR1_BOOTCFG1_SDMMC BIT(6) +#define SRC_SBMR1_BOOTCFG1_MMC BIT(4) #define SRC_SBMR2_BMOD_MASK (0x3 << 24) #define SRC_SBMR2_BMOD_SHIFT 24 #define SRC_SBMR2_BMOD_FUSES 0x0 diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 01bc2998b81..8ba03e5a17f 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -132,10 +132,14 @@ enum { VF610_PAD_PTD24__GPIO_70 = IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD23__NF_IO7 = IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD0__UART2_TX = IOMUX_PAD(0x013c, 0x013c, 2, 0x38c, 2, VF610_UART_PAD_CTRL), VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD1__UART2_RX = IOMUX_PAD(0x0140, 0x0140, 2, 0x388, 2, VF610_UART_PAD_CTRL), VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD2__GPIO_81 = IOMUX_PAD(0x0144, 0x0144, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD3__QSPI0_A_DATA2 = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD4__GPIO_83 = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD3__GPIO_82 = IOMUX_PAD(0x0148, 0x0148, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD4__GPIO_83 = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD4__QSPI0_A_DATA1 = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD5__QSPI0_A_DATA0 = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), diff --git a/arch/arm/include/asm/mach-imx/video.h b/arch/arm/include/asm/mach-imx/video.h index 812e6f85e43..d1a14ad7d34 100644 --- a/arch/arm/include/asm/mach-imx/video.h +++ b/arch/arm/include/asm/mach-imx/video.h @@ -26,4 +26,5 @@ extern size_t display_count; #endif int ipu_set_ldb_clock(int rate); +int ipu_displays_init(void); #endif diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 8631fbd481e..ec09ef240fe 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -23,7 +23,7 @@ config IMX_RDC config IMX_BOOTAUX bool "Support boot auxiliary core" - depends on ARCH_MX7 || ARCH_MX6 + depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 help bootaux [addr] to boot auxiliary core. diff --git a/arch/arm/mach-imx/video.c b/arch/arm/mach-imx/video.c index 953fe53cb49..22a371a212d 100644 --- a/arch/arm/mach-imx/video.c +++ b/arch/arm/mach-imx/video.c @@ -4,6 +4,17 @@ #include <linux/errno.h> #include <asm/mach-imx/video.h> +#ifdef CONFIG_IMX_HDMI +#include <asm/arch/mxc_hdmi.h> +#include <asm/io.h> + +int detect_hdmi(struct display_info_t const *dev) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; +} +#endif + int board_video_skip(void) { int i; @@ -42,6 +53,11 @@ int board_video_skip(void) displays[i].mode.name, displays[i].mode.xres, displays[i].mode.yres); + +#ifdef CONFIG_IMX_HDMI + if (!strcmp(displays[i].mode.name, "HDMI")) + imx_enable_hdmi_phy(); +#endif } else printf("LCD %s cannot be configured: %d\n", displays[i].mode.name, ret); @@ -53,12 +69,7 @@ int board_video_skip(void) return ret; } -#ifdef CONFIG_IMX_HDMI -#include <asm/arch/mxc_hdmi.h> -#include <asm/io.h> -int detect_hdmi(struct display_info_t const *dev) +int ipu_displays_init(void) { - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; + return board_video_skip(); } -#endif diff --git a/board/aristainetos/aristainetos-v2.c b/board/aristainetos/aristainetos-v2.c index b33a75c82cd..63b10575534 100644 --- a/board/aristainetos/aristainetos-v2.c +++ b/board/aristainetos/aristainetos-v2.c @@ -33,7 +33,7 @@ #include <micrel.h> #include <spi.h> #include <video.h> -#include <../drivers/video/ipu.h> +#include <../drivers/video/imx/ipu.h> #if defined(CONFIG_VIDEO_BMP_LOGO) #include <bmp_logo.h> #endif diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c index a4c587a3908..63cd605b6ab 100644 --- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c +++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c @@ -112,7 +112,7 @@ void build_info(void) sc_misc_build_info(-1, &sc_build, &sc_commit); if (!sc_build) { printf("SCFW does not support build info\n"); - sc_commit = 0; /* Display 0 when the build info is not supported*/ + sc_commit = 0; /* Display 0 when the build info is not supported */ } printf("Build: SCFW %x\n", sc_commit); } diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 079d302fbec..f42d2ceb79d 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -10,6 +10,7 @@ #include <asm/arch/iomux.h> #include <asm/arch/mx6-pins.h> #include <linux/errno.h> +#include <linux/libfdt.h> #include <asm/gpio.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/iomux-v3.h> @@ -27,6 +28,7 @@ #include <i2c.h> #include <input.h> #include <pwm.h> +#include <version.h> #include <stdlib.h> #include "../common/ge_common.h" #include "../common/vpd_reader.h" @@ -44,10 +46,6 @@ static struct vpd_cache vpd; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) @@ -57,9 +55,6 @@ static struct vpd_cache vpd; #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) @@ -110,58 +105,13 @@ static void setup_iomux_enet(void) imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); /* Reset AR8033 PHY */ + gpio_request(IMX_GPIO_NR(1, 28), "fec_rst"); gpio_direction_output(IMX_GPIO_NR(1, 28), 0); mdelay(10); gpio_set_value(IMX_GPIO_NR(1, 28), 1); mdelay(1); } -static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const ecspi1_pads[] = { - MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, @@ -201,18 +151,6 @@ static struct i2c_pads_info i2c_pad_info3 = { } }; -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1; -} - -static void setup_spi(void) -{ - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); -} -#endif - static iomux_v3_cfg_t const pcie_pads[] = { MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -229,76 +167,6 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); } -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg[3] = { - {USDHC2_BASE_ADDR}, - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) -#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = 1; /* eMMC is always present */ - break; - case USDHC4_BASE_ADDR: - ret = !gpio_get_value(USDHC4_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - int i; - - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - gpio_direction_input(USDHC4_CD_GPIO); - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers\n" - "(%d) then supported by the board (%d)\n", - i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} -#endif - static int mx6_rgmii_rework(struct phy_device *phydev) { /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */ @@ -533,8 +401,8 @@ static void setup_display_bx50v3(void) /* backlights off until needed */ imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); + gpio_request(LVDS_POWER_GP, "lvds_power"); gpio_direction_input(LVDS_POWER_GP); - gpio_direction_input(LVDS_BACKLIGHT_GP); } #endif /* CONFIG_VIDEO_IPUV3 */ @@ -687,20 +555,25 @@ int board_init(void) set_confidx(&vpd); } + gpio_request(SUS_S3_OUT, "sus_s3_out"); gpio_direction_output(SUS_S3_OUT, 1); + + gpio_request(WIFI_EN, "wifi_en"); gpio_direction_output(WIFI_EN, 1); + #if defined(CONFIG_VIDEO_IPUV3) if (is_b850v3()) setup_display_b850v3(); else setup_display_bx50v3(); + + gpio_request(LVDS_BACKLIGHT_GP, "lvds_backlight"); + gpio_direction_input(LVDS_BACKLIGHT_GP); #endif + /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif return 0; } @@ -818,6 +691,15 @@ int checkboard(void) return 0; } +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + fdt_setprop(blob, 0, "ge,boot-ver", version_string, + strlen(version_string) + 1); + return 0; +} +#endif + static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { #ifdef CONFIG_VIDEO_IPUV3 diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index 23bfe555417..5411e422acd 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -17,6 +17,7 @@ #include <asm/arch/iomux-mx53.h> #include <asm/arch/clock.h> #include <linux/errno.h> +#include <linux/libfdt.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/mx5_video.h> #include <environment.h> @@ -30,6 +31,7 @@ #include <fsl_pmic.h> #include <linux/fb.h> #include <ipu_pixfmt.h> +#include <version.h> #include <watchdog.h> #include "ppd_gpio.h" #include <stdlib.h> @@ -122,79 +124,6 @@ static void setup_iomux_fec(void) imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC3_BASE_ADDR}, - {MMC_SDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) - -int board_mmc_init(bd_t *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), - MX53_PAD_EIM_DA11__GPIO3_11, - }; - - static const iomux_v3_cfg_t sd2_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), - MX53_PAD_EIM_DA13__GPIO3_13, - }; - - u32 index; - int ret; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads(sd1_pads, - ARRAY_SIZE(sd1_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads(sd2_pads, - ARRAY_SIZE(sd2_pads)); - break; - default: - printf("Warning: you configured more ESDHC controller (%d) as supported by the board(2)\n", - CONFIG_SYS_FSL_ESDHC_NUM); - return -EINVAL; - } - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} -#endif - #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) @@ -380,3 +309,12 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + fdt_setprop(blob, 0, "ge,boot-ver", version_string, + strlen(version_string) + 1); + return 0; +} +#endif diff --git a/board/ge/mx53ppd/ppd_gpio.h b/board/ge/mx53ppd/ppd_gpio.h index e3b84c7a710..ba2d1baf37b 100644 --- a/board/ge/mx53ppd/ppd_gpio.h +++ b/board/ge/mx53ppd/ppd_gpio.h @@ -36,6 +36,8 @@ static const iomux_v3_cfg_t ppd_pads[] = { MX53_PAD_KEY_COL2__GPIO4_10, MX53_PAD_KEY_ROW2__GPIO4_11, MX53_PAD_KEY_COL3__GPIO4_12, + + MX53_PAD_PATA_DATA7__GPIO2_7, /* BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N */ }; struct gpio_cfg { @@ -61,6 +63,7 @@ struct gpio_cfg { #define ECSPI1_CS1 IMX_GPIO_NR(4, 10) #define ECSPI1_CS2 IMX_GPIO_NR(4, 11) #define ECSPI1_CS3 IMX_GPIO_NR(4, 12) +#define BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N IMX_GPIO_NR(2, 7) static const struct gpio_cfg ppd_gpios[] = { /* FEC */ @@ -90,6 +93,7 @@ static const struct gpio_cfg ppd_gpios[] = { { ECSPI1_CS1, 1 }, { ECSPI1_CS2, 1 }, { ECSPI1_CS3, 1 }, + { BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N, 1 }, }; #endif /* __PPD_GPIO_H_ */ diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index f988af2abc0..c30df5df9dc 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * (C) Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de. + * * Copyright 2013 Freescale Semiconductor, Inc. */ @@ -10,79 +13,12 @@ #include <asm/arch/ddrmc-vf610.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> -#include <mmc.h> -#include <fsl_esdhc.h> +#include <led.h> +#include <environment.h> #include <miiphy.h> -#include <netdev.h> -#include <i2c.h> DECLARE_GLOBAL_DATA_PTR; -/* - * Default DDR pad settings in arch/arm/include/asm/arch-vf610/iomux-vf610.h - * do not match our settings. Let us (re)define our own settings here. - */ - -#define PCM052_VF610_DDR_PAD_CTRL PAD_CTL_DSE_20ohm -#define PCM052_VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_20ohm | \ - PAD_CTL_INPUT_DIFFERENTIAL) -#define PCM052_VF610_DDR_RESET_PAD_CTL (PAD_CTL_DSE_150ohm | \ - PAD_CTL_PUS_100K_UP | \ - PAD_CTL_INPUT_DIFFERENTIAL) - -enum { - PCM052_VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_RESET_PAD_CTL), - PCM052_VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), - PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), - PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), - PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), - PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 = IOMUX_PAD(0x02e0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), -}; - static struct ddrmc_cr_setting pcm052_cr_settings[] = { /* not in the datasheets, but in the original code */ { 0x00002000, 105 }, @@ -151,59 +87,6 @@ static struct ddrmc_phy_setting pcm052_phy_settings[] = { int dram_init(void) { - static const iomux_v3_cfg_t pcm052_pads[] = { - PCM052_VF610_PAD_DDR_A15__DDR_A_15, - PCM052_VF610_PAD_DDR_A14__DDR_A_14, - PCM052_VF610_PAD_DDR_A13__DDR_A_13, - PCM052_VF610_PAD_DDR_A12__DDR_A_12, - PCM052_VF610_PAD_DDR_A11__DDR_A_11, - PCM052_VF610_PAD_DDR_A10__DDR_A_10, - PCM052_VF610_PAD_DDR_A9__DDR_A_9, - PCM052_VF610_PAD_DDR_A8__DDR_A_8, - PCM052_VF610_PAD_DDR_A7__DDR_A_7, - PCM052_VF610_PAD_DDR_A6__DDR_A_6, - PCM052_VF610_PAD_DDR_A5__DDR_A_5, - PCM052_VF610_PAD_DDR_A4__DDR_A_4, - PCM052_VF610_PAD_DDR_A3__DDR_A_3, - PCM052_VF610_PAD_DDR_A2__DDR_A_2, - PCM052_VF610_PAD_DDR_A1__DDR_A_1, - PCM052_VF610_PAD_DDR_A0__DDR_A_0, - PCM052_VF610_PAD_DDR_BA2__DDR_BA_2, - PCM052_VF610_PAD_DDR_BA1__DDR_BA_1, - PCM052_VF610_PAD_DDR_BA0__DDR_BA_0, - PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B, - PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0, - PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0, - PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0, - PCM052_VF610_PAD_DDR_D15__DDR_D_15, - PCM052_VF610_PAD_DDR_D14__DDR_D_14, - PCM052_VF610_PAD_DDR_D13__DDR_D_13, - PCM052_VF610_PAD_DDR_D12__DDR_D_12, - PCM052_VF610_PAD_DDR_D11__DDR_D_11, - PCM052_VF610_PAD_DDR_D10__DDR_D_10, - PCM052_VF610_PAD_DDR_D9__DDR_D_9, - PCM052_VF610_PAD_DDR_D8__DDR_D_8, - PCM052_VF610_PAD_DDR_D7__DDR_D_7, - PCM052_VF610_PAD_DDR_D6__DDR_D_6, - PCM052_VF610_PAD_DDR_D5__DDR_D_5, - PCM052_VF610_PAD_DDR_D4__DDR_D_4, - PCM052_VF610_PAD_DDR_D3__DDR_D_3, - PCM052_VF610_PAD_DDR_D2__DDR_D_2, - PCM052_VF610_PAD_DDR_D1__DDR_D_1, - PCM052_VF610_PAD_DDR_D0__DDR_D_0, - PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1, - PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0, - PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1, - PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0, - PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B, - PCM052_VF610_PAD_DDR_WE__DDR_WE_B, - PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0, - PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1, - PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1, - PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0, - PCM052_VF610_PAD_DDR_RESETB, - }; - #if defined(CONFIG_TARGET_PCM052) static const struct ddr3_jedec_timings pcm052_ddr_timings = { @@ -320,8 +203,6 @@ int dram_init(void) #endif - imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); - ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, pcm052_phy_settings, 1, row_diff); @@ -330,135 +211,6 @@ int dram_init(void) return 0; } -static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart1_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, VF610_UART_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, VF610_UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) - -static void setup_iomux_enet(void) -{ - static const iomux_v3_cfg_t enet0_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); -} - -/* - * I2C2 is the only I2C used, on pads PTA22/PTA23. - */ - -static void setup_iomux_i2c(void) -{ - static const iomux_v3_cfg_t i2c_pads[] = { - VF610_PAD_PTA22__I2C2_SCL, - VF610_PAD_PTA23__I2C2_SDA, - }; - - imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); -} - -#ifdef CONFIG_NAND_VF610_NFC -static void setup_iomux_nfc(void) -{ - static const iomux_v3_cfg_t nfc_pads[] = { - VF610_PAD_PTD31__NF_IO15, - VF610_PAD_PTD30__NF_IO14, - VF610_PAD_PTD29__NF_IO13, - VF610_PAD_PTD28__NF_IO12, - VF610_PAD_PTD27__NF_IO11, - VF610_PAD_PTD26__NF_IO10, - VF610_PAD_PTD25__NF_IO9, - VF610_PAD_PTD24__NF_IO8, - VF610_PAD_PTD23__NF_IO7, - VF610_PAD_PTD22__NF_IO6, - VF610_PAD_PTD21__NF_IO5, - VF610_PAD_PTD20__NF_IO4, - VF610_PAD_PTD19__NF_IO3, - VF610_PAD_PTD18__NF_IO2, - VF610_PAD_PTD17__NF_IO1, - VF610_PAD_PTD16__NF_IO0, - VF610_PAD_PTB24__NF_WE_B, - VF610_PAD_PTB25__NF_CE0_B, - VF610_PAD_PTB27__NF_RE_B, - VF610_PAD_PTC26__NF_RB_B, - VF610_PAD_PTC27__NF_ALE, - VF610_PAD_PTC28__NF_CLE - }; - - imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); -} -#endif - -static void setup_iomux_qspi(void) -{ - static const iomux_v3_cfg_t qspi0_pads[] = { - VF610_PAD_PTD0__QSPI0_A_QSCK, - VF610_PAD_PTD1__QSPI0_A_CS0, - VF610_PAD_PTD2__QSPI0_A_DATA3, - VF610_PAD_PTD3__QSPI0_A_DATA2, - VF610_PAD_PTD4__QSPI0_A_DATA1, - VF610_PAD_PTD5__QSPI0_A_DATA0, - VF610_PAD_PTD7__QSPI0_B_QSCK, - VF610_PAD_PTD8__QSPI0_B_CS0, - VF610_PAD_PTD9__QSPI0_B_DATA3, - VF610_PAD_PTD10__QSPI0_B_DATA2, - VF610_PAD_PTD11__QSPI0_B_DATA1, - VF610_PAD_PTD12__QSPI0_B_DATA0, - }; - - imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); -} - -#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) - -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {ESDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - /* eSDHC1 is always present */ - return 1; -} - -int board_mmc_init(bd_t *bis) -{ - static const iomux_v3_cfg_t esdhc1_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), - }; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - imx_iomux_v3_setup_multiple_pads( - esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); - - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} - static void clock_init(void) { struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; @@ -485,7 +237,7 @@ static void clock_init(void) clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, - CCM_CCGR10_NFC_CTRL_MASK | CCM_CCGR10_I2C2_CTRL_MASK); + CCM_CCGR10_NFC_CTRL_MASK); clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); @@ -531,23 +283,10 @@ static void mscm_init(void) writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); } -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - int board_early_init_f(void) { clock_init(); mscm_init(); - setup_iomux_uart(); - setup_iomux_enet(); - setup_iomux_i2c(); - setup_iomux_qspi(); - setup_iomux_nfc(); return 0; } @@ -571,47 +310,102 @@ int board_init(void) return 0; } -int checkboard(void) +#ifdef CONFIG_TARGET_BK4R1 +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { - puts("Board: PCM-052\n"); + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[4]; + struct fuse_bank4_regs *fuse = + (struct fuse_bank4_regs *)bank->fuse_regs; + u32 value; - return 0; + /* + * BK4 has different layout of stored MAC address + * than one used in imx_get_mac_from_fuse() @ generic.c + */ + + switch (dev_id) { + case 0: + value = readl(&fuse->mac_addr1); + + mac[0] = value >> 8; + mac[1] = value; + + value = readl(&fuse->mac_addr0); + mac[2] = value >> 24; + mac[3] = value >> 16; + mac[4] = value >> 8; + mac[5] = value; + break; + case 1: + value = readl(&fuse->mac_addr2); + + mac[0] = value >> 24; + mac[1] = value >> 16; + mac[2] = value >> 8; + mac[3] = value; + + value = readl(&fuse->mac_addr1); + mac[4] = value >> 24; + mac[5] = value >> 16; + break; + } } -static int do_m4go(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) +int board_late_init(void) { - ulong addr; + struct src *psrc = (struct src *)SRC_BASE_ADDR; + u32 reg; - /* Consume 'm4go' */ - argc--; argv++; + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); /* - * Parse provided address - default to load_addr in case not provided. + * BK4r1 handle emergency/service SD card boot + * Checking the SBMR1 register BOOTCFG1 byte: + * NAND: + * bit [2] - NAND data width - 16 + * bit [5] - NAND fast boot + * bit [7] = 1 - NAND as a source of booting + * SD card (0x64): + * bit [4] = 0 - SD card source + * bit [6] = 1 - SD/MMC source */ - if (argc) - addr = simple_strtoul(argv[0], NULL, 16); - else - addr = load_addr; + reg = readl(&psrc->sbmr1); + if ((reg & SRC_SBMR1_BOOTCFG1_SDMMC) && + !(reg & SRC_SBMR1_BOOTCFG1_MMC)) { + printf("------ SD card boot -------\n"); + set_default_env("!LVFBootloader", 0); + env_set("bootcmd", + "run prepare_install_bk4r1_envs; run install_bk4r1rs"); + } - /* - * Write boot address in PERSISTENT_ENTRY1[31:0] aka SRC_GPR2[31:0] - */ - writel(addr + 0x401, 0x4006E028); + return 0; +} - /* - * Start secondary processor by enabling its clock - */ - writel(0x15a5a, 0x4006B08C); +/** + * KSZ8081 + */ +#define MII_KSZ8081_REFERENCE_CLOCK_SELECT 0x1f +#define RMII_50MHz_CLOCK 0x8180 - return 1; +int board_phy_config(struct phy_device *phydev) +{ + /* Set 50 MHz reference clock */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT, + RMII_50MHz_CLOCK); + + return genphy_config(phydev); } +#endif /* CONFIG_TARGET_BK4R1 */ -U_BOOT_CMD( - m4go, 2 /* one arg max */, 1 /* repeatable */, do_m4go, - "start the secondary Cortex-M4 from scatter file image", - "[<addr>]\n" - " - start secondary Cortex-M4 core using a scatter file image\n" - "The argument needs to be a scatter file\n" -); +int checkboard(void) +{ +#ifdef CONFIG_TARGET_BK4R1 + puts("Board: BK4r1 (L333)\n"); +#else + puts("Board: PCM-052\n"); +#endif + return 0; +} diff --git a/board/tbs/tbs2910/MAINTAINERS b/board/tbs/tbs2910/MAINTAINERS index bf176553d24..a3ad2f712a2 100644 --- a/board/tbs/tbs2910/MAINTAINERS +++ b/board/tbs/tbs2910/MAINTAINERS @@ -1,6 +1,7 @@ TBS2910 BOARD M: Soeren Moch <smoch@web.de> S: Maintained +F: arch/arm/dts/imx6q-tbs2910.dts F: board/tbs/tbs2910/ F: configs/tbs2910_defconfig F: include/configs/tbs2910.h diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c index ecb45f208d0..fb0e773afc9 100644 --- a/board/tbs/tbs2910/tbs2910.c +++ b/board/tbs/tbs2910/tbs2910.c @@ -9,9 +9,7 @@ #include <asm/arch/mx6-pins.h> #include <linux/errno.h> #include <asm/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/sata.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/video.h> #include <mmc.h> @@ -22,7 +20,6 @@ #include <asm/arch/crm_regs.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> -#include <i2c.h> DECLARE_GLOBAL_DATA_PTR; #define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \ @@ -33,63 +30,9 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) - -#ifdef CONFIG_SYS_I2C -/* I2C1, SGTL5000 */ -static struct i2c_pads_info i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD, - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD, - .gp = IMX_GPIO_NR(5, 26) - } -}; - -/* I2C2 HDMI */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -/* I2C3, CON11, DS1307, PCIe_SMB */ -static struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD, - .gp = IMX_GPIO_NR(1, 6) - } -}; -#endif /* CONFIG_SYS_I2C */ - static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), @@ -138,6 +81,7 @@ static void setup_iomux_enet(void) imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); /* Reset AR8035 PHY */ + gpio_request(IMX_GPIO_NR(1, 25), "ETH_PHY_RESET"); gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); udelay(500); gpio_set_value(IMX_GPIO_NR(1, 25), 1); @@ -155,108 +99,6 @@ static void setup_iomux_uart(void) } #ifdef CONFIG_FSL_ESDHC -static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -static iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[3] = { - {USDHC2_BASE_ADDR}, - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) -#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = !gpio_get_value(USDHC3_CD_GPIO); - break; - case USDHC4_BASE_ADDR: - ret = 1; /* eMMC/uSDHC4 is always present */ - break; - } - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - /* - * (U-Boot device node) (Physical Port) - * mmc0 SD2 - * mmc1 SD3 - * mmc2 eMMC - */ - int i, ret; - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - gpio_direction_input(USDHC3_CD_GPIO); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - return 0; -} - /* set environment device to boot device when booting from SD */ int board_mmc_get_env_dev(int devno) { @@ -415,12 +257,6 @@ static const struct boot_mode board_boot_modes[] = { }; #endif -#ifdef CONFIG_USB_EHCI_MX6 -static iomux_v3_cfg_t const usb_otg_pads[] = { - MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), -}; -#endif - int board_init(void) { /* address of boot parameters */ @@ -429,26 +265,8 @@ int board_init(void) #ifdef CONFIG_VIDEO_IPUV3 setup_display(); #endif -#ifdef CONFIG_SYS_I2C - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); -#endif -#ifdef CONFIG_DWC_AHSATA - setup_sata(); -#endif #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif -#ifdef CONFIG_USB_EHCI_MX6 - imx_iomux_v3_setup_multiple_pads( - usb_otg_pads, ARRAY_SIZE(usb_otg_pads)); -#endif - return 0; -} - -int checkboard(void) -{ - puts("Board: TBS2910 Matrix ARM mini PC\n"); return 0; } diff --git a/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg deleted file mode 100644 index 29d1c3126c5..00000000000 --- a/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016 Toradex AG - */ - -DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 -DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7954 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB328F64 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023 -DATA 4, MX6_MMDC_P0_MDOTC, 0x09555050 -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 -DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 - -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x432A0338 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03260324 -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43340344 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x031E027C - -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37 - -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4336453F - -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E - -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg deleted file mode 100644 index 02e90dd5e65..00000000000 --- a/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016 Toradex AG - */ - -DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 -DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E78f5 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xff328f64 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 -DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 -DATA 4, MX6_MMDC_P0_MDSCR, 0x02888032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 - -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03300338 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03240324 -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x03440350 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x032C0308 - -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46 - -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x403E463E -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46 - -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E - -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS index 2c70ab4fbd9..7efe816a789 100644 --- a/board/toradex/apalis_imx6/MAINTAINERS +++ b/board/toradex/apalis_imx6/MAINTAINERS @@ -1,9 +1,9 @@ Apalis iMX6 M: Max Krummenacher <max.krummenacher@toradex.com> W: http://developer.toradex.com/software/linux/linux-software +W: https://www.toradex.com/community S: Maintained F: board/toradex/apalis_imx6/ F: include/configs/apalis_imx6.h F: configs/apalis_imx6_defconfig -F: configs/apalis_imx6_nospl_com_defconfig -F: configs/apalis_imx6_nospl_it_defconfig +F: arch/arm/dts/imx6-apalis.dts diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index d11207c7f44..3e591854380 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -2,38 +2,33 @@ /* * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> - * Copyright (C) 2014-2016, Toradex AG + * Copyright (C) 2014-2019, Toradex AG * copied from nitrogen6x */ #include <common.h> #include <dm.h> -#include <environment.h> + +#include <ahci.h> #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> -#include <asm/arch/mxc_hdmi.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mx6-pins.h> #include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/sys_proto.h> #include <asm/bootm.h> #include <asm/gpio.h> -#include <asm/io.h> +#include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/sata.h> -#include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/video.h> +#include <dm/device-internal.h> #include <dm/platform_data/serial_mxc.h> -#include <dm/platdata.h> +#include <dwc_ahsata.h> +#include <environment.h> #include <fsl_esdhc.h> -#include <i2c.h> -#include <input.h> #include <imx_thermal.h> -#include <linux/errno.h> -#include <malloc.h> -#include <mmc.h> #include <micrel.h> #include <miiphy.h> #include <netdev.h> @@ -50,40 +45,30 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_SLOW) -#define NO_PULLUP ( \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_SRE_SLOW) - #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) #define TRISTATE (PAD_CTL_HYS | PAD_CTL_SPEED_MED) -#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) - #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST) +#define APALIS_IMX6_SATA_INIT_RETRIES 10 + int dram_init(void) { /* use the DDR controllers configured size */ @@ -103,63 +88,7 @@ iomux_v3_cfg_t const uart1_pads_dte[] = { MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* Apalis I2C1 */ -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, - .gp = IMX_GPIO_NR(5, 26) - } -}; - -/* Apalis local, PMIC, SGTL5000, STMPE811 */ -struct i2c_pads_info i2c_pad_info_loc = { - .scl = { - .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -/* Apalis I2C3 / CAM */ -struct i2c_pads_info i2c_pad_info3 = { - .scl = { - .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, - .gp = IMX_GPIO_NR(3, 17) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, - .gp = IMX_GPIO_NR(3, 18) - } -}; - -/* Apalis I2C2 / DDC */ -struct i2c_pads_info i2c_pad_info_ddc = { - .scl = { - .i2c_mode = MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL | PC, - .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, - .gp = IMX_GPIO_NR(2, 30) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, - .gp = IMX_GPIO_NR(3, 16) - } -}; - +#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD) /* Apalis MMC1 */ iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -190,18 +119,19 @@ iomux_v3_cfg_t const usdhc2_pads[] = { /* eMMC */ iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION, }; +#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */ int mx6_rgmii_rework(struct phy_device *phydev) { @@ -241,7 +171,8 @@ iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), /* KSZ9031 PHY Reset */ - MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL) | + MUX_MODE_SION, # define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25) }; @@ -253,6 +184,7 @@ static void setup_iomux_enet(void) static int reset_enet_phy(struct mii_dev *bus) { /* Reset KSZ9031 PHY */ + gpio_request(GPIO_ENET_PHY_RESET, "ETH_RESET#"); gpio_direction_output(GPIO_ENET_PHY_RESET, 0); mdelay(10); gpio_set_value(GPIO_ENET_PHY_RESET, 1); @@ -263,15 +195,24 @@ static int reset_enet_phy(struct mii_dev *bus) /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */ iomux_v3_cfg_t const gpio_pads[] = { /* Apalis GPIO1 - GPIO8 */ - MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN), - MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN) | + MUX_MODE_SION, + MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, }; static void setup_iomux_gpio(void) @@ -281,7 +222,7 @@ static void setup_iomux_gpio(void) iomux_v3_cfg_t const usb_pads[] = { /* USBH_EN */ - MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION, # define GPIO_USBH_EN IMX_GPIO_NR(1, 0) /* USB_VBUS_DET */ MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -289,7 +230,7 @@ iomux_v3_cfg_t const usb_pads[] = { /* USBO1_ID */ MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), /* USBO1_EN */ - MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION, # define GPIO_USBO_EN IMX_GPIO_NR(3, 22) }; @@ -297,8 +238,11 @@ iomux_v3_cfg_t const usb_pads[] = { * UARTs are used in DTE mode, switch the mode on all UARTs before * any pinmuxing connects a (DCE) output to a transceiver output. */ +#define UCR3 0x88 /* FIFO Control Register */ +#define UCR3_RI BIT(8) /* RIDELT DTE mode */ +#define UCR3_DCD BIT(9) /* DCDDELT DTE mode */ #define UFCR 0x90 /* FIFO Control Register */ -#define UFCR_DCEDTE (1<<6) /* DCE=0 */ +#define UFCR_DCEDTE BIT(6) /* DCE=0 */ static void setup_dtemode_uart(void) { @@ -306,6 +250,11 @@ static void setup_dtemode_uart(void) setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE); setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE); setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE); + + clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI); + clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI); + clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI); + clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI); } static void setup_dcemode_uart(void) { @@ -321,7 +270,6 @@ static void setup_iomux_dte_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads_dte, ARRAY_SIZE(uart1_pads_dte)); } - static void setup_iomux_dce_uart(void) { setup_dcemode_uart(); @@ -335,32 +283,10 @@ int board_ehci_hcd_init(int port) imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); return 0; } - -int board_ehci_power(int port, int on) -{ - switch (port) { - case 0: - /* control OTG power */ - gpio_direction_output(GPIO_USBO_EN, on); - mdelay(100); - break; - case 1: - /* Control MXM USBH */ - gpio_direction_output(GPIO_USBH_EN, on); - mdelay(2); - /* Control onboard USB Hub VBUS */ - gpio_direction_output(GPIO_USB_VBUS_DET, on); - mdelay(100); - break; - default: - break; - } - return 0; -} #endif -#ifdef CONFIG_FSL_ESDHC -/* use the following sequence: eMMC, MMC, SD */ +#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD) +/* use the following sequence: eMMC, MMC1, SD1 */ struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { {USDHC3_BASE_ADDR}, {USDHC1_BASE_ADDR}, @@ -374,10 +300,12 @@ int board_mmc_getcd(struct mmc *mmc) switch (cfg->esdhc_base) { case USDHC1_BASE_ADDR: + gpio_request(GPIO_MMC_CD, "MMC_CD"); gpio_direction_input(GPIO_MMC_CD); ret = !gpio_get_value(GPIO_MMC_CD); break; case USDHC2_BASE_ADDR: + gpio_request(GPIO_MMC_CD, "SD_CD"); gpio_direction_input(GPIO_SD_CD); ret = !gpio_get_value(GPIO_SD_CD); break; @@ -388,43 +316,6 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { -#ifndef CONFIG_SPL_BUILD - s32 status = 0; - u32 index = 0; - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - - usdhc_cfg[0].max_bus_width = 8; - usdhc_cfg[1].max_bus_width = 8; - usdhc_cfg[2].max_bus_width = 4; - - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - break; - case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - break; - default: - printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; - } - - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - } - - return status; -#else struct src *psrc = (struct src *)SRC_BASE_ADDR; unsigned reg = readl(&psrc->sbmr1) >> 11; /* @@ -463,9 +354,8 @@ int board_mmc_init(bd_t *bis) } return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -#endif } -#endif +#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */ int board_phy_config(struct phy_device *phydev) { @@ -489,6 +379,7 @@ int board_eth_init(bd_t *bis) bus = fec_get_miibus(base, -1); if (!bus) return 0; + bus->reset = reset_enet_phy; /* scan PHY 4,5,6,7 */ phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); @@ -497,6 +388,7 @@ int board_eth_init(bd_t *bis) puts("no PHY found\n"); return 0; } + printf("using PHY at %d\n", phydev->addr); ret = fec_probe(bis, -1, base, bus, phydev); if (ret) { @@ -504,7 +396,8 @@ int board_eth_init(bd_t *bis) free(phydev); free(bus); } -#endif +#endif /* CONFIG_FEC_MXC */ + return 0; } @@ -520,18 +413,21 @@ static iomux_v3_cfg_t const pwr_intb_pads[] = { static iomux_v3_cfg_t const backlight_pads[] = { /* Backlight on RGB connector: J15 */ - MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) | + MUX_MODE_SION, #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13) /* additional CPU pin on BKL_PWM, keep in tristate */ MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE), /* Backlight PWM, used as GPIO in U-Boot */ - MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) | + MUX_MODE_SION, #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10) /* buffer output enable 0: buffer enabled */ - MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION, #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2) /* PSAVE# integrated VDAC */ - MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | + MUX_MODE_SION, #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31) }; @@ -571,12 +467,6 @@ static void do_enable_hdmi(struct display_info_t const *dev) imx_enable_hdmi_phy(); } -static int detect_i2c(struct display_info_t const *dev) -{ - return (0 == i2c_set_bus_num(dev->bus)) && - (0 == i2c_probe(dev->addr)); -} - static void enable_lvds(struct display_info_t const *dev) { struct iomuxc *iomux = (struct iomuxc *) @@ -670,7 +560,6 @@ struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, .pixfmt = IPU_PIX_FMT_LVDS666, - .detect = detect_i2c, .enable = enable_lvds, .mode = { .name = "wsvga-lvds", @@ -741,6 +630,9 @@ static void setup_display(void) imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); /* use 0 for EDT 7", use 1 for LG fullHD panel */ + gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM"); + gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN"); + gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON"); gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0); gpio_direction_output(RGB_BACKLIGHT_GP, 1); @@ -782,10 +674,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); - #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif @@ -835,16 +723,17 @@ int board_late_init(void) #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */ #endif /* CONFIG_REVISION_TAG */ - return 0; -} -#endif /* CONFIG_BOARD_LATE_INIT */ +#ifdef CONFIG_CMD_USB_SDP + if (is_boot_from_usb()) { + printf("Serial Downloader recovery mode, using sdp command\n"); + env_set("bootdelay", "0"); + env_set("bootcmd", "sdp 0"); + } +#endif /* CONFIG_CMD_USB_SDP */ -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP) -int ft_system_setup(void *blob, bd_t *bd) -{ return 0; } -#endif +#endif /* CONFIG_BOARD_LATE_INIT */ int checkboard(void) { @@ -1143,7 +1032,6 @@ MX6_MMDC_P0_MDSCR, 0x00000000, MX6_MMDC_P0_MAPSR, 0x00011006, }; - static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -1204,7 +1092,7 @@ void board_init_f(ulong dummy) ccgr_init(); gpr_init(); - /* iomux and setup of i2c */ + /* iomux */ board_early_init_f(); /* setup GP timer */ @@ -1232,7 +1120,7 @@ void reset_cpu(ulong addr) { } -#endif +#endif /* CONFIG_SPL_BUILD */ static struct mxc_serial_platdata mxc_serial_plat = { .reg = (struct mxc_uart *)UART1_BASE, @@ -1243,3 +1131,52 @@ U_BOOT_DEVICE(mxc_serial) = { .name = "serial_mxc", .platdata = &mxc_serial_plat, }; + +#if CONFIG_IS_ENABLED(AHCI) +static int sata_imx_probe(struct udevice *dev) +{ + int i, err; + + for (i = 0; i < APALIS_IMX6_SATA_INIT_RETRIES; i++) { + err = setup_sata(); + if (err) { + printf("SATA setup failed: %d\n", err); + return err; + } + + udelay(100); + + err = dwc_ahsata_probe(dev); + if (!err) + break; + + /* There is no device on the SATA port */ + if (sata_dm_port_status(0, 0) == 0) + break; + + /* There's a device, but link not established. Retry */ + device_remove(dev, DM_REMOVE_NORMAL); + } + + return 0; +} + +struct ahci_ops sata_imx_ops = { + .port_status = dwc_ahsata_port_status, + .reset = dwc_ahsata_bus_reset, + .scan = dwc_ahsata_scan, +}; + +static const struct udevice_id sata_imx_ids[] = { + { .compatible = "fsl,imx6q-ahci" }, + { } +}; + +U_BOOT_DRIVER(sata_imx) = { + .name = "dwc_ahci", + .id = UCLASS_AHCI, + .of_match = sata_imx_ids, + .ops = &sata_imx_ops, + .probe = sata_imx_probe, +}; +#endif /* AHCI */ diff --git a/board/toradex/apalis_imx6/apalis_imx6q.cfg b/board/toradex/apalis_imx6/apalis_imx6q.cfg deleted file mode 100644 index 739b1b70615..00000000000 --- a/board/toradex/apalis_imx6/apalis_imx6q.cfg +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -#include "ddr-setup.cfg" -#if CONFIG_DDR_MB == 2048 -#include "1066mhz_4x256mx16.cfg" -#else -#include "1066mhz_4x128mx16.cfg" -#endif -#include "clocks.cfg" diff --git a/board/toradex/apalis_imx6/clocks.cfg b/board/toradex/apalis_imx6/clocks.cfg deleted file mode 100644 index 1bcbc4fa380..00000000000 --- a/board/toradex/apalis_imx6/clocks.cfg +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0x00FFF300 -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz - */ -DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/toradex/apalis_imx6/ddr-setup.cfg b/board/toradex/apalis_imx6/ddr-setup.cfg deleted file mode 100644 index e42e3ce4387..00000000000 --- a/board/toradex/apalis_imx6/ddr-setup.cfg +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* - * DDR3 settings - * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), - * memory bus width: 64 bits x16/x32/x64 - * MX6DL ddr is limited to 800 MHz(400 MHz clock) - * memory bus width: 64 bits x16/x32/x64 - * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) - * memory bus width: 32 bits x16/x32 - */ -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 - -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 - -DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 - -DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 - -DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 - -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 - -/* (differential input) */ -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -/* (differential input) */ -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -/* disable ddr pullups */ -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 - -/* Read data DQ Byte0-3 delay */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 - -/* - * MDMISC mirroring interleaved (row/bank/col) - */ -DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 - -/* - * MDSCR con_req - */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 diff --git a/board/toradex/apalis_imx6/do_fuse.c b/board/toradex/apalis_imx6/do_fuse.c index e6793e366a3..22d191f52ae 100644 --- a/board/toradex/apalis_imx6/do_fuse.c +++ b/board/toradex/apalis_imx6/do_fuse.c @@ -29,7 +29,7 @@ static int mfgr_fuse(void) return CMD_RET_FAILURE; } /* boot cfg */ - fuse_prog(0, 5, 0x00005072); + fuse_prog(0, 5, 0x00005062); /* BT_FUSE_SEL */ fuse_prog(0, 6, 0x00000010); return CMD_RET_SUCCESS; diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c index 7334e92f2ef..ebd6418fd47 100644 --- a/board/toradex/apalis_imx6/pf0100.c +++ b/board/toradex/apalis_imx6/pf0100.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2014-2016, Toradex AG + * Copyright (C) 2014-2019, Toradex AG */ /* @@ -9,7 +9,6 @@ #include <common.h> #include <i2c.h> -#include <linux/compiler.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> #include <asm/arch/mx6-pins.h> @@ -22,6 +21,8 @@ /* define for PMIC register dump */ /*#define DEBUG */ +#define WARNBAR "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n" + /* use Apalis GPIO1 to switch on VPGM, ON: 1 */ static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = { MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -30,99 +31,100 @@ static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = { unsigned pmic_init(void) { + int rc; + struct udevice *dev = NULL; unsigned programmed = 0; uchar bus = 1; uchar devid, revid, val; - puts("PMIC: "); - if (!((0 == i2c_set_bus_num(bus)) && - (0 == i2c_probe(PFUZE100_I2C_ADDR)))) { - puts("i2c bus failed\n"); + puts("PMIC: "); + rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev); + if (rc) { + printf("failed to get device for PMIC at address 0x%x\n", + PFUZE100_I2C_ADDR); + return 0; + } + + /* check for errors in PMIC fuses */ + if (dm_i2c_read(dev, PFUZE100_INTSTAT3, &val, 1) < 0) { + puts("i2c pmic INTSTAT3 register read failed\n"); + return 0; + } + if (val & PFUZE100_BIT_OTP_ECCI) { + puts("\n" WARNBAR); + puts("WARNING: ecc errors found in pmic fuse banks\n"); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE1, &val, 1) < 0) { + puts("i2c pmic ECC_SE1 register read failed\n"); + return 0; + } + if (val & PFUZE100_BITS_ECC_SE1) { + puts(WARNBAR); + puts("WARNING: ecc has made bit corrections in banks 1 to 5\n"); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE2, &val, 1) < 0) { + puts("i2c pmic ECC_SE2 register read failed\n"); + return 0; + } + if (val & PFUZE100_BITS_ECC_SE2) { + puts(WARNBAR); + puts("WARNING: ecc has made bit corrections in banks 6 to 10\n" + ); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE1, &val, 1) < 0) { + puts("i2c pmic ECC_DE register read failed\n"); return 0; } + if (val & PFUZE100_BITS_ECC_DE1) { + puts(WARNBAR); + puts("ERROR: banks 1 to 5 have uncorrectable bits\n"); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE2, &val, 1) < 0) { + puts("i2c pmic ECC_DE register read failed\n"); + return 0; + } + if (val & PFUZE100_BITS_ECC_DE2) { + puts(WARNBAR); + puts("ERROR: banks 6 to 10 have uncorrectable bits\n"); + puts(WARNBAR); + } + /* get device ident */ - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) { + if (dm_i2c_read(dev, PFUZE100_DEVICEID, &devid, 1) < 0) { puts("i2c pmic devid read failed\n"); return 0; } - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) { + if (dm_i2c_read(dev, PFUZE100_REVID, &revid, 1) < 0) { puts("i2c pmic revid read failed\n"); return 0; } - printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid); - -#ifdef DEBUG - { - unsigned i, j; - - for (i = 0; i < 16; i++) - printf("\t%x", i); - for (j = 0; j < 0x80; ) { - printf("\n%2x", j); - for (i = 0; i < 16; i++) { - i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); - printf("\t%2x", val); - } - j += 0x10; - } - printf("\nEXT Page 1"); - - val = PFUZE100_PAGE_REGISTER_PAGE1; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, - &val, 1)) { - puts("i2c write failed\n"); - return 0; - } - - for (j = 0x80; j < 0x100; ) { - printf("\n%2x", j); - for (i = 0; i < 16; i++) { - i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); - printf("\t%2x", val); - } - j += 0x10; - } - printf("\nEXT Page 2"); + printf("device id: 0x%.2x, revision id: 0x%.2x, ", devid, revid); - val = PFUZE100_PAGE_REGISTER_PAGE2; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, - &val, 1)) { - puts("i2c write failed\n"); - return 0; - } - - for (j = 0x80; j < 0x100; ) { - printf("\n%2x", j); - for (i = 0; i < 16; i++) { - i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); - printf("\t%2x", val); - } - j += 0x10; - } - printf("\n"); - } -#endif /* get device programmed state */ val = PFUZE100_PAGE_REGISTER_PAGE1; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) { + if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) { puts("i2c write failed\n"); return 0; } - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) { + if (dm_i2c_read(dev, PFUZE100_FUSE_POR1, &val, 1) < 0) { puts("i2c fuse_por read failed\n"); return 0; } if (val & PFUZE100_FUSE_POR_M) programmed++; - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) { + if (dm_i2c_read(dev, PFUZE100_FUSE_POR2, &val, 1) < 0) { puts("i2c fuse_por read failed\n"); return programmed; } if (val & PFUZE100_FUSE_POR_M) programmed++; - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) { + if (dm_i2c_read(dev, PFUZE100_FUSE_POR3, &val, 1) < 0) { puts("i2c fuse_por read failed\n"); return programmed; } @@ -131,13 +133,13 @@ unsigned pmic_init(void) switch (programmed) { case 0: - printf("PMIC: not programmed\n"); + puts("not programmed\n"); break; case 3: - printf("PMIC: programmed\n"); + puts("programmed\n"); break; default: - printf("PMIC: undefined programming state\n"); + puts("undefined programming state\n"); break; } @@ -145,25 +147,75 @@ unsigned pmic_init(void) if (programmed != 3) { /* set VGEN1 to 1.2V */ val = PFUZE100_VGEN1_VAL; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_VGEN1CTL, 1, - &val, 1)) { + if (dm_i2c_write(dev, PFUZE100_VGEN1CTL, &val, 1)) { puts("i2c write failed\n"); return programmed; } /* set SWBST to 5.0V */ val = PFUZE100_SWBST_VAL; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_SWBSTCTL, 1, - &val, 1)) { + if (dm_i2c_write(dev, PFUZE100_SWBSTCTL, &val, 1)) puts("i2c write failed\n"); + } + +#ifdef DEBUG + { + unsigned int i, j; + + for (i = 0; i < 16; i++) + printf("\t%x", i); + for (j = 0; j < 0x80; ) { + printf("\n%2x", j); + for (i = 0; i < 16; i++) { + dm_i2c_read(dev, j + i, &val, 1); + printf("\t%2x", val); + } + j += 0x10; } + printf("\nEXT Page 1"); + + val = PFUZE100_PAGE_REGISTER_PAGE1; + if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) { + puts("i2c write failed\n"); + return 0; + } + + for (j = 0x80; j < 0x100; ) { + printf("\n%2x", j); + for (i = 0; i < 16; i++) { + dm_i2c_read(dev, j + i, &val, 1); + printf("\t%2x", val); + } + j += 0x10; + } + printf("\nEXT Page 2"); + + val = PFUZE100_PAGE_REGISTER_PAGE2; + if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) { + puts("i2c write failed\n"); + return 0; + } + + for (j = 0x80; j < 0x100; ) { + printf("\n%2x", j); + for (i = 0; i < 16; i++) { + dm_i2c_read(dev, j + i, &val, 1); + printf("\t%2x", val); + } + j += 0x10; + } + printf("\n"); } +#endif /* DEBUG */ + return programmed; } #ifndef CONFIG_SPL_BUILD static int pf0100_prog(void) { + int rc; + struct udevice *dev = NULL; unsigned char bus = 1; unsigned char val; unsigned int i; @@ -177,9 +229,10 @@ static int pf0100_prog(void) ARRAY_SIZE(pmic_prog_pads)); gpio_direction_output(PMIC_PROG_VOLTAGE, 0); - if (!((0 == i2c_set_bus_num(bus)) && - (0 == i2c_probe(PFUZE100_I2C_ADDR)))) { - puts("i2c bus failed\n"); + rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev); + if (rc) { + printf("failed to get device for PMIC at address 0x%x\n", + PFUZE100_I2C_ADDR); return CMD_RET_FAILURE; } @@ -187,8 +240,7 @@ static int pf0100_prog(void) switch (pmic_otp_prog[i].cmd) { case pmic_i2c: val = (unsigned char) (pmic_otp_prog[i].value & 0xff); - if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg, - 1, &val, 1)) { + if (dm_i2c_write(dev, pmic_otp_prog[i].reg, &val, 1)) { printf("i2c write failed, reg 0x%2x, value 0x%2x\n", pmic_otp_prog[i].reg, val); return CMD_RET_FAILURE; @@ -227,4 +279,4 @@ U_BOOT_CMD( "Program the OTP fuses on the PMIC PF0100", "" ); -#endif +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/toradex/apalis_imx6/pf0100.h b/board/toradex/apalis_imx6/pf0100.h index c0efb79bbc9..92576205110 100644 --- a/board/toradex/apalis_imx6/pf0100.h +++ b/board/toradex/apalis_imx6/pf0100.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2014-2016, Toradex AG + * Copyright (C) 2014-2019, Toradex AG */ /* @@ -10,11 +10,23 @@ #ifndef PF0100_H_ #define PF0100_H_ +/* bit definitions */ +#define PFUZE100_BIT_0 (0x01 << 0) +#define PFUZE100_BIT_1 (0x01 << 1) +#define PFUZE100_BIT_2 (0x01 << 2) +#define PFUZE100_BIT_3 (0x01 << 3) +#define PFUZE100_BIT_4 (0x01 << 4) +#define PFUZE100_BIT_5 (0x01 << 5) +#define PFUZE100_BIT_6 (0x01 << 6) +#define PFUZE100_BIT_7 (0x01 << 7) + /* 7-bit I2C bus slave address */ #define PFUZE100_I2C_ADDR (0x08) /* Register Addresses */ #define PFUZE100_DEVICEID (0x0) #define PFUZE100_REVID (0x3) +#define PFUZE100_INTSTAT3 (0xe) +#define PFUZE100_BIT_OTP_ECCI PFUZE100_BIT_7 #define PFUZE100_SW1AMODE (0x23) #define PFUZE100_SW1ACON 36 #define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */ @@ -39,12 +51,55 @@ #define PFUZE100_PAGE_REGISTER_PAGE2 (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M) /* extended page 1 */ +#define PFUZE100_OTP_ECC_SE1 0x8a +#define PFUZE100_BIT_ECC1_SE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC2_SE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC3_SE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC4_SE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC5_SE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_SE1 ((PFUZE100_BIT_ECC1_SE) | \ + (PFUZE100_BIT_ECC2_SE) | \ + (PFUZE100_BIT_ECC3_SE) | \ + (PFUZE100_BIT_ECC4_SE) | \ + (PFUZE100_BIT_ECC5_SE)) +#define PFUZE100_OTP_ECC_SE2 0x8b +#define PFUZE100_BIT_ECC6_SE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC7_SE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC8_SE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC9_SE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC10_SE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_SE2 ((PFUZE100_BIT_ECC6_SE) | \ + (PFUZE100_BIT_ECC7_SE) | \ + (PFUZE100_BIT_ECC8_SE) | \ + (PFUZE100_BIT_ECC9_SE) | \ + (PFUZE100_BIT_ECC10_SE)) +#define PFUZE100_OTP_ECC_DE1 0x8c +#define PFUZE100_BIT_ECC1_DE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC2_DE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC3_DE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC4_DE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC5_DE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_DE1 ((PFUZE100_BIT_ECC1_DE) | \ + (PFUZE100_BIT_ECC2_DE) | \ + (PFUZE100_BIT_ECC3_DE) | \ + (PFUZE100_BIT_ECC4_DE) | \ + (PFUZE100_BIT_ECC5_DE)) +#define PFUZE100_OTP_ECC_DE2 0x8d +#define PFUZE100_BIT_ECC6_DE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC7_DE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC8_DE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC9_DE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC10_DE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_DE2 ((PFUZE100_BIT_ECC6_DE) | \ + (PFUZE100_BIT_ECC7_DE) | \ + (PFUZE100_BIT_ECC8_DE) | \ + (PFUZE100_BIT_ECC9_DE) | \ + (PFUZE100_BIT_ECC10_DE)) #define PFUZE100_FUSE_POR1 0xe4 #define PFUZE100_FUSE_POR2 0xe5 #define PFUZE100_FUSE_POR3 0xe6 #define PFUZE100_FUSE_POR_M (0x1 << 1) - /* output some informational messages, return the number FUSE_POR=1 */ /* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */ unsigned pmic_init(void); diff --git a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg deleted file mode 100644 index c9407143d23..00000000000 --- a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - */ - -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D -DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x00301023 -DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D -/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */ -DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 -/* DDR3 DATA BUS SIZE: 64BIT */ -/* DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 */ -/* DDR3 DATA BUS SIZE: 32BIT */ -DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 - -/* Write commands to DDR */ -/* Load Mode Registers */ -/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ -/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 -/* ZQ calibration */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 - -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 - -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 - -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218 - -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344 -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930 - -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039 -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D - -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg deleted file mode 100644 index c319d2a7296..00000000000 --- a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - */ - -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D -DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x00301023 -DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D -/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */ -DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 -/* DDR3 DATA BUS SIZE: 64BIT */ -DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 -/* DDR3 DATA BUS SIZE: 32BIT */ -/* DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 */ - -/* Write commands to DDR */ -/* Load Mode Registers */ -/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/ -/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 -/* ZQ calibration */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 - -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 - -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 - -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218 - -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344 -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930 - -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039 -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D - -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS index 1cc7ef2e71b..e25c07306cc 100644 --- a/board/toradex/colibri_imx6/MAINTAINERS +++ b/board/toradex/colibri_imx6/MAINTAINERS @@ -1,8 +1,9 @@ Colibri iMX6 M: Max Krummenacher <max.krummenacher@toradex.com> W: http://developer.toradex.com/software/linux/linux-software +W: https://www.toradex.com/community S: Maintained F: board/toradex/colibri_imx6/ F: include/configs/colibri_imx6.h F: configs/colibri_imx6_defconfig -F: configs/colibri_imx6_nospl_defconfig +F: arch/arm/dts/imx6-colibri.dts diff --git a/board/toradex/colibri_imx6/clocks.cfg b/board/toradex/colibri_imx6/clocks.cfg deleted file mode 100644 index 1bcbc4fa380..00000000000 --- a/board/toradex/colibri_imx6/clocks.cfg +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0x00FFF300 -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz - */ -DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 17876f27e96..c634e3243dc 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -2,40 +2,35 @@ /* * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> - * Copyright (C) 2014-2016, Toradex AG + * Copyright (C) 2014-2019, Toradex AG * copied from nitrogen6x */ #include <common.h> #include <dm.h> + #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> #include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> #include <asm/arch/mxc_hdmi.h> #include <asm/arch/sys_proto.h> #include <asm/bootm.h> #include <asm/gpio.h> +#include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/sata.h> -#include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/video.h> -#include <asm/io.h> +#include <cpu.h> #include <dm/platform_data/serial_mxc.h> -#include <dm/platdata.h> +#include <environment.h> #include <fsl_esdhc.h> -#include <i2c.h> -#include <input.h> #include <imx_thermal.h> -#include <linux/errno.h> -#include <malloc.h> #include <micrel.h> #include <miiphy.h> -#include <mmc.h> #include <netdev.h> +#include <cpu.h> #include "../common/tdx-cfg-block.h" #ifdef CONFIG_TDX_CMD_IMX_MFGR @@ -49,22 +44,16 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_SLOW) @@ -77,8 +66,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) -#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) - #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST) int dram_init(void) @@ -96,36 +83,8 @@ iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* Colibri I2C */ -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, - .gp = IMX_GPIO_NR(1, 6) - } -}; - -/* Colibri local, PMIC, SGTL5000, STMPE811 */ -struct i2c_pads_info i2c_pad_info_loc = { - .scl = { - .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, - .gp = IMX_GPIO_NR(2, 30) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, - .gp = IMX_GPIO_NR(3, 16) - } -}; - -/* Apalis MMC */ +#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD) +/* Colibri MMC */ iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -139,18 +98,19 @@ iomux_v3_cfg_t const usdhc1_pads[] = { /* eMMC */ iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL), MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; +#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */ iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -173,68 +133,123 @@ static void setup_iomux_enet(void) /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */ iomux_v3_cfg_t const gpio_pads[] = { /* ADDRESS[17:18] [25] used as GPIO */ - MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* ADDRESS[19:24] used as GPIO */ - MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* DATA[16:29] [31] used as GPIO */ - MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* DQM[0:3] used as GPIO */ - MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* RDY used as GPIO */ - MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* ADDRESS[16] DATA[30] used as GPIO */ - MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN), - MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN) | + MUX_MODE_SION, + MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* CSI pins used as GPIO */ - MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN), - MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN) | + MUX_MODE_SION, + MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* GPIO */ - MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), - MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, + MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | + MUX_MODE_SION, /* USBH_OC */ MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP), /* USBC_ID */ @@ -249,8 +264,8 @@ static void setup_iomux_gpio(void) } iomux_v3_cfg_t const usb_pads[] = { - /* USB_PE */ - MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* USBH_PEN */ + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION, # define GPIO_USBH_EN IMX_GPIO_NR(3, 31) }; @@ -258,14 +273,21 @@ iomux_v3_cfg_t const usb_pads[] = { * UARTs are used in DTE mode, switch the mode on all UARTs before * any pinmuxing connects a (DCE) output to a transceiver output. */ +#define UCR3 0x88 /* FIFO Control Register */ +#define UCR3_RI BIT(8) /* RIDELT DTE mode */ +#define UCR3_DCD BIT(9) /* DCDDELT DTE mode */ #define UFCR 0x90 /* FIFO Control Register */ -#define UFCR_DCEDTE (1<<6) /* DCE=0 */ +#define UFCR_DCEDTE BIT(6) /* DCE=0 */ static void setup_dtemode_uart(void) { setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE); setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE); setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE); + + clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI); + clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI); + clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI); } static void setup_iomux_uart(void) @@ -280,29 +302,9 @@ int board_ehci_hcd_init(int port) imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); return 0; } - -int board_ehci_power(int port, int on) -{ - switch (port) { - case 0: - /* control OTG power */ - /* No special PE for USBC, always on when ID pin signals - host mode */ - break; - case 1: - /* Control MXM USBH */ - /* Set MXM USBH power enable, '0' means on */ - gpio_direction_output(GPIO_USBH_EN, !on); - mdelay(100); - break; - default: - break; - } - return 0; -} #endif -#ifdef CONFIG_FSL_ESDHC +#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD) /* use the following sequence: eMMC, MMC */ struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { {USDHC3_BASE_ADDR}, @@ -316,6 +318,7 @@ int board_mmc_getcd(struct mmc *mmc) switch (cfg->esdhc_base) { case USDHC1_BASE_ADDR: + gpio_request(GPIO_MMC_CD, "MMC_CD"); gpio_direction_input(GPIO_MMC_CD); ret = !gpio_get_value(GPIO_MMC_CD); break; @@ -326,37 +329,6 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { -#ifndef CONFIG_SPL_BUILD - s32 status = 0; - u32 index = 0; - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - usdhc_cfg[0].max_bus_width = 8; - usdhc_cfg[1].max_bus_width = 4; - - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - break; - default: - printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return status; - } - - status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - } - - return status; -#else struct src *psrc = (struct src *)SRC_BASE_ADDR; unsigned reg = readl(&psrc->sbmr1) >> 11; /* @@ -388,9 +360,8 @@ int board_mmc_init(bd_t *bis) } return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -#endif } -#endif +#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */ int board_phy_config(struct phy_device *phydev) { @@ -412,6 +383,7 @@ int board_eth_init(bd_t *bis) ret = enable_fec_anatop_clock(0, ENET_50MHZ); if (ret) return ret; + /* set gpr1[ENET_CLK_SEL] */ setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); @@ -421,6 +393,7 @@ int board_eth_init(bd_t *bis) bus = fec_get_miibus(base, -1); if (!bus) return 0; + /* scan PHY 1..7 */ phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII); if (!phydev) { @@ -428,6 +401,7 @@ int board_eth_init(bd_t *bis) puts("no PHY found\n"); return 0; } + phy_reset(phydev); printf("using PHY at %d\n", phydev->addr); ret = fec_probe(bis, -1, base, bus, phydev); @@ -436,7 +410,8 @@ int board_eth_init(bd_t *bis) free(phydev); free(bus); } -#endif +#endif /* CONFIG_FEC_MXC */ + return 0; } @@ -452,11 +427,12 @@ static iomux_v3_cfg_t const pwr_intb_pads[] = { static iomux_v3_cfg_t const backlight_pads[] = { /* Backlight On */ - MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION, #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26) /* Backlight PWM, used as GPIO in U-Boot */ MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP), - MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) | + MUX_MODE_SION, #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9) }; @@ -619,6 +595,8 @@ static void setup_display(void) imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); /* use 0 for EDT 7", use 1 for LG fullHD panel */ + gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>"); + gpio_request(RGB_BACKLIGHT_GP, "BL_ON"); gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); gpio_direction_output(RGB_BACKLIGHT_GP, 1); } @@ -656,9 +634,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc); - #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif @@ -689,16 +664,17 @@ int board_late_init(void) env_set("board_rev", env_str); #endif - return 0; -} -#endif /* CONFIG_BOARD_LATE_INIT */ +#ifdef CONFIG_CMD_USB_SDP + if (is_boot_from_usb()) { + printf("Serial Downloader recovery mode, using sdp command\n"); + env_set("bootdelay", "0"); + env_set("bootcmd", "sdp 0"); + } +#endif /* CONFIG_CMD_USB_SDP */ -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP) -int ft_system_setup(void *blob, bd_t *bd) -{ return 0; } -#endif +#endif /* CONFIG_BOARD_LATE_INIT */ int checkboard(void) { @@ -722,7 +698,18 @@ int checkboard(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, bd_t *bd) { - return ft_common_board_setup(blob, bd); + u32 cma_size; + + ft_common_board_setup(blob, bd); + + cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024); + cma_size = min((u32)(gd->ram_size >> 1), cma_size); + + fdt_setprop_u32(blob, + fdt_path_offset(blob, "/reserved-memory/linux,cma"), + "size", + cma_size); + return 0; } #endif @@ -1073,6 +1060,7 @@ static void spl_dram_init(void) case TEMP_AUTOMOTIVE: default: if (is_cpu_type(MXC_CPU_MX6DL)) { + puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n"); ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); } else { puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n"); @@ -1083,6 +1071,26 @@ static void spl_dram_init(void) udelay(100); } +static iomux_v3_cfg_t const gpio_reset_pad[] = { + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) | + MUX_MODE_SION +#define GPIO_NRESET IMX_GPIO_NR(6, 27) +}; + +#define IMX_RESET_CAUSE_POR 0x00011 +static void nreset_out(void) +{ + int reset_cause = get_imx_reset_cause(); + + if (reset_cause != IMX_RESET_CAUSE_POR) { + imx_iomux_v3_setup_multiple_pads(gpio_reset_pad, + ARRAY_SIZE(gpio_reset_pad)); + gpio_direction_output(GPIO_NRESET, 1); + udelay(100); + gpio_direction_output(GPIO_NRESET, 0); + } +} + void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ @@ -1091,7 +1099,7 @@ void board_init_f(ulong dummy) ccgr_init(); gpr_init(); - /* iomux and setup of i2c */ + /* iomux */ board_early_init_f(); /* setup GP timer */ @@ -1109,6 +1117,9 @@ void board_init_f(ulong dummy) /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); + /* Assert nReset_Out */ + nreset_out(); + /* load/boot image from boot device */ board_init_r(NULL, 0); } @@ -1117,7 +1128,7 @@ void reset_cpu(ulong addr) { } -#endif +#endif /* CONFIG_SPL_BUILD */ static struct mxc_serial_platdata mxc_serial_plat = { .reg = (struct mxc_uart *)UART1_BASE, diff --git a/board/toradex/colibri_imx6/colibri_imx6.cfg b/board/toradex/colibri_imx6/colibri_imx6.cfg deleted file mode 100644 index 517c5eb1072..00000000000 --- a/board/toradex/colibri_imx6/colibri_imx6.cfg +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014 Toradex AG - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -#include "ddr-setup.cfg" - -#if CONFIG_DDR_MB == 256 -#include "800mhz_2x64mx16.cfg" -#elif CONFIG_DDR_MB == 512 -#include "800mhz_4x64mx16.cfg" -#else -#error "unknown DDR size" -#endif - -#include "clocks.cfg" diff --git a/board/toradex/colibri_imx6/ddr-setup.cfg b/board/toradex/colibri_imx6/ddr-setup.cfg deleted file mode 100644 index a943fd228c4..00000000000 --- a/board/toradex/colibri_imx6/ddr-setup.cfg +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2014-2016, Toradex AG - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* - * DDR3 settings - * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), - * memory bus width: 64 bits x16/x32/x64 - * MX6DL ddr is limited to 800 MHz(400 MHz clock) - * memory bus width: 64 bits x16/x32/x64 - * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) - * memory bus width: 32 bits x16/x32 - */ -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 - -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 - -DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 - -DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 - -DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 - -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 - -/* (differential input) */ -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -/* (differential input) */ -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -/* disable ddr pullups */ -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 - -/* Read data DQ Byte0-3 delay */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 - -/* - * MDMISC mirroring interleaved (row/bank/col) - */ -/* TODO: check what the RALAT field does */ -DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 - -/* - * MDSCR con_req - */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c index e6793e366a3..22d191f52ae 100644 --- a/board/toradex/colibri_imx6/do_fuse.c +++ b/board/toradex/colibri_imx6/do_fuse.c @@ -29,7 +29,7 @@ static int mfgr_fuse(void) return CMD_RET_FAILURE; } /* boot cfg */ - fuse_prog(0, 5, 0x00005072); + fuse_prog(0, 5, 0x00005062); /* BT_FUSE_SEL */ fuse_prog(0, 6, 0x00000010); return CMD_RET_SUCCESS; diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c index fa63865670f..e744243297b 100644 --- a/board/toradex/colibri_imx6/pf0100.c +++ b/board/toradex/colibri_imx6/pf0100.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2014-2016, Toradex AG + * Copyright (C) 2014-2019, Toradex AG */ /* @@ -21,6 +21,8 @@ /* define for PMIC register dump */ /*#define DEBUG */ +#define WARNBAR "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n" + /* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */ static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = { MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -29,37 +31,128 @@ static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = { unsigned pmic_init(void) { + int rc; + struct udevice *dev = NULL; unsigned programmed = 0; uchar bus = 1; uchar devid, revid, val; - puts("PMIC: "); - if (!((0 == i2c_set_bus_num(bus)) && - (0 == i2c_probe(PFUZE100_I2C_ADDR)))) { - puts("i2c bus failed\n"); + puts("PMIC: "); + rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev); + if (rc) { + printf("failed to get device for PMIC at address 0x%x\n", + PFUZE100_I2C_ADDR); + return 0; + } + + /* check for errors in PMIC fuses */ + if (dm_i2c_read(dev, PFUZE100_INTSTAT3, &val, 1) < 0) { + puts("i2c pmic INTSTAT3 register read failed\n"); return 0; } + if (val & PFUZE100_BIT_OTP_ECCI) { + puts("\n" WARNBAR); + puts("WARNING: ecc errors found in pmic fuse banks\n"); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE1, &val, 1) < 0) { + puts("i2c pmic ECC_SE1 register read failed\n"); + return 0; + } + if (val & PFUZE100_BITS_ECC_SE1) { + puts(WARNBAR); + puts("WARNING: ecc has made bit corrections in banks 1 to 5\n"); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE2, &val, 1) < 0) { + puts("i2c pmic ECC_SE2 register read failed\n"); + return 0; + } + if (val & PFUZE100_BITS_ECC_SE2) { + puts(WARNBAR); + puts("WARNING: ecc has made bit corrections in banks 6 to 10\n" + ); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE1, &val, 1) < 0) { + puts("i2c pmic ECC_DE register read failed\n"); + return 0; + } + if (val & PFUZE100_BITS_ECC_DE1) { + puts(WARNBAR); + puts("ERROR: banks 1 to 5 have uncorrectable bits\n"); + puts(WARNBAR); + } + if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE2, &val, 1) < 0) { + puts("i2c pmic ECC_DE register read failed\n"); + return 0; + } + if (val & PFUZE100_BITS_ECC_DE2) { + puts(WARNBAR); + puts("ERROR: banks 6 to 10 have uncorrectable bits\n"); + puts(WARNBAR); + } + /* get device ident */ - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) { + if (dm_i2c_read(dev, PFUZE100_DEVICEID, &devid, 1) < 0) { puts("i2c pmic devid read failed\n"); return 0; } - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) { + if (dm_i2c_read(dev, PFUZE100_REVID, &revid, 1) < 0) { puts("i2c pmic revid read failed\n"); return 0; } - printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid); + printf("device id: 0x%.2x, revision id: 0x%.2x, ", devid, revid); + + /* get device programmed state */ + val = PFUZE100_PAGE_REGISTER_PAGE1; + if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) { + puts("i2c write failed\n"); + return 0; + } + if (dm_i2c_read(dev, PFUZE100_FUSE_POR1, &val, 1) < 0) { + puts("i2c fuse_por read failed\n"); + return 0; + } + if (val & PFUZE100_FUSE_POR_M) + programmed++; + + if (dm_i2c_read(dev, PFUZE100_FUSE_POR2, &val, 1) < 0) { + puts("i2c fuse_por read failed\n"); + return programmed; + } + if (val & PFUZE100_FUSE_POR_M) + programmed++; + + if (dm_i2c_read(dev, PFUZE100_FUSE_POR3, &val, 1) < 0) { + puts("i2c fuse_por read failed\n"); + return programmed; + } + if (val & PFUZE100_FUSE_POR_M) + programmed++; + + switch (programmed) { + case 0: + puts("not programmed\n"); + break; + case 3: + puts("programmed\n"); + break; + default: + puts("undefined programming state\n"); + break; + } #ifdef DEBUG { - unsigned i, j; + unsigned int i, j; for (i = 0; i < 16; i++) printf("\t%x", i); for (j = 0; j < 0x80; ) { printf("\n%2x", j); for (i = 0; i < 16; i++) { - i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); + dm_i2c_read(dev, j + i, &val, 1); printf("\t%2x", val); } j += 0x10; @@ -67,8 +160,7 @@ unsigned pmic_init(void) printf("\nEXT Page 1"); val = PFUZE100_PAGE_REGISTER_PAGE1; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, - &val, 1)) { + if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) { puts("i2c write failed\n"); return 0; } @@ -76,7 +168,7 @@ unsigned pmic_init(void) for (j = 0x80; j < 0x100; ) { printf("\n%2x", j); for (i = 0; i < 16; i++) { - i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); + dm_i2c_read(dev, j + i, &val, 1); printf("\t%2x", val); } j += 0x10; @@ -84,8 +176,7 @@ unsigned pmic_init(void) printf("\nEXT Page 2"); val = PFUZE100_PAGE_REGISTER_PAGE2; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, - &val, 1)) { + if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) { puts("i2c write failed\n"); return 0; } @@ -93,52 +184,14 @@ unsigned pmic_init(void) for (j = 0x80; j < 0x100; ) { printf("\n%2x", j); for (i = 0; i < 16; i++) { - i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1); + dm_i2c_read(dev, j + i, &val, 1); printf("\t%2x", val); } j += 0x10; } printf("\n"); } -#endif - /* get device programmed state */ - val = PFUZE100_PAGE_REGISTER_PAGE1; - if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) { - puts("i2c write failed\n"); - return 0; - } - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) { - puts("i2c fuse_por read failed\n"); - return 0; - } - if (val & PFUZE100_FUSE_POR_M) - programmed++; - - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) { - puts("i2c fuse_por read failed\n"); - return programmed; - } - if (val & PFUZE100_FUSE_POR_M) - programmed++; - - if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) { - puts("i2c fuse_por read failed\n"); - return programmed; - } - if (val & PFUZE100_FUSE_POR_M) - programmed++; - - switch (programmed) { - case 0: - printf("PMIC: not programmed\n"); - break; - case 3: - printf("PMIC: programmed\n"); - break; - default: - printf("PMIC: undefined programming state\n"); - break; - } +#endif /* DEBUG */ return programmed; } @@ -146,6 +199,8 @@ unsigned pmic_init(void) #ifndef CONFIG_SPL_BUILD static int pf0100_prog(void) { + int rc; + struct udevice *dev = NULL; unsigned char bus = 1; unsigned char val; unsigned int i; @@ -159,9 +214,10 @@ static int pf0100_prog(void) ARRAY_SIZE(pmic_prog_pads)); gpio_direction_output(PMIC_PROG_VOLTAGE, 0); - if (!((0 == i2c_set_bus_num(bus)) && - (0 == i2c_probe(PFUZE100_I2C_ADDR)))) { - puts("i2c bus failed\n"); + rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev); + if (rc) { + printf("failed to get device for PMIC at address 0x%x\n", + PFUZE100_I2C_ADDR); return CMD_RET_FAILURE; } @@ -169,8 +225,7 @@ static int pf0100_prog(void) switch (pmic_otp_prog[i].cmd) { case pmic_i2c: val = (unsigned char) (pmic_otp_prog[i].value & 0xff); - if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg, - 1, &val, 1)) { + if (dm_i2c_write(dev, pmic_otp_prog[i].reg, &val, 1)) { printf("i2c write failed, reg 0x%2x, value 0x%2x\n", pmic_otp_prog[i].reg, val); return CMD_RET_FAILURE; @@ -209,4 +264,4 @@ U_BOOT_CMD( "Program the OTP fuses on the PMIC PF0100", "" ); -#endif +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/toradex/colibri_imx6/pf0100.h b/board/toradex/colibri_imx6/pf0100.h index c0efb79bbc9..92576205110 100644 --- a/board/toradex/colibri_imx6/pf0100.h +++ b/board/toradex/colibri_imx6/pf0100.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2014-2016, Toradex AG + * Copyright (C) 2014-2019, Toradex AG */ /* @@ -10,11 +10,23 @@ #ifndef PF0100_H_ #define PF0100_H_ +/* bit definitions */ +#define PFUZE100_BIT_0 (0x01 << 0) +#define PFUZE100_BIT_1 (0x01 << 1) +#define PFUZE100_BIT_2 (0x01 << 2) +#define PFUZE100_BIT_3 (0x01 << 3) +#define PFUZE100_BIT_4 (0x01 << 4) +#define PFUZE100_BIT_5 (0x01 << 5) +#define PFUZE100_BIT_6 (0x01 << 6) +#define PFUZE100_BIT_7 (0x01 << 7) + /* 7-bit I2C bus slave address */ #define PFUZE100_I2C_ADDR (0x08) /* Register Addresses */ #define PFUZE100_DEVICEID (0x0) #define PFUZE100_REVID (0x3) +#define PFUZE100_INTSTAT3 (0xe) +#define PFUZE100_BIT_OTP_ECCI PFUZE100_BIT_7 #define PFUZE100_SW1AMODE (0x23) #define PFUZE100_SW1ACON 36 #define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */ @@ -39,12 +51,55 @@ #define PFUZE100_PAGE_REGISTER_PAGE2 (0x02 & PFUZE100_PAGE_REGISTER_PAGE_M) /* extended page 1 */ +#define PFUZE100_OTP_ECC_SE1 0x8a +#define PFUZE100_BIT_ECC1_SE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC2_SE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC3_SE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC4_SE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC5_SE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_SE1 ((PFUZE100_BIT_ECC1_SE) | \ + (PFUZE100_BIT_ECC2_SE) | \ + (PFUZE100_BIT_ECC3_SE) | \ + (PFUZE100_BIT_ECC4_SE) | \ + (PFUZE100_BIT_ECC5_SE)) +#define PFUZE100_OTP_ECC_SE2 0x8b +#define PFUZE100_BIT_ECC6_SE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC7_SE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC8_SE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC9_SE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC10_SE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_SE2 ((PFUZE100_BIT_ECC6_SE) | \ + (PFUZE100_BIT_ECC7_SE) | \ + (PFUZE100_BIT_ECC8_SE) | \ + (PFUZE100_BIT_ECC9_SE) | \ + (PFUZE100_BIT_ECC10_SE)) +#define PFUZE100_OTP_ECC_DE1 0x8c +#define PFUZE100_BIT_ECC1_DE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC2_DE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC3_DE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC4_DE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC5_DE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_DE1 ((PFUZE100_BIT_ECC1_DE) | \ + (PFUZE100_BIT_ECC2_DE) | \ + (PFUZE100_BIT_ECC3_DE) | \ + (PFUZE100_BIT_ECC4_DE) | \ + (PFUZE100_BIT_ECC5_DE)) +#define PFUZE100_OTP_ECC_DE2 0x8d +#define PFUZE100_BIT_ECC6_DE PFUZE100_BIT_0 +#define PFUZE100_BIT_ECC7_DE PFUZE100_BIT_1 +#define PFUZE100_BIT_ECC8_DE PFUZE100_BIT_2 +#define PFUZE100_BIT_ECC9_DE PFUZE100_BIT_3 +#define PFUZE100_BIT_ECC10_DE PFUZE100_BIT_4 +#define PFUZE100_BITS_ECC_DE2 ((PFUZE100_BIT_ECC6_DE) | \ + (PFUZE100_BIT_ECC7_DE) | \ + (PFUZE100_BIT_ECC8_DE) | \ + (PFUZE100_BIT_ECC9_DE) | \ + (PFUZE100_BIT_ECC10_DE)) #define PFUZE100_FUSE_POR1 0xe4 #define PFUZE100_FUSE_POR2 0xe5 #define PFUZE100_FUSE_POR3 0xe6 #define PFUZE100_FUSE_POR_M (0x1 << 1) - /* output some informational messages, return the number FUSE_POR=1 */ /* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */ unsigned pmic_init(void); diff --git a/board/toradex/colibri_imx6/pf0100_otp.inc b/board/toradex/colibri_imx6/pf0100_otp.inc index ce29b95ae2a..c3b1f67f815 100644 --- a/board/toradex/colibri_imx6/pf0100_otp.inc +++ b/board/toradex/colibri_imx6/pf0100_otp.inc @@ -5,16 +5,17 @@ // Register Output for PF0100 programmer // Customer: Toradex AG -// Program: Colibri iMX6 +// Program: Colibri iMX6 V1.1 // Sample marking: -// Date: 24.07.2015 -// Time: 10:52:58 +// Date: 01.05.2017 +// Time: 16:22:32 // Generated from Spreadsheet Revision: P1.8 -/* sed commands to get from programmer script to struct */ +/* sed commands to get from programmer script to struct content */ /* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc - sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */ + sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc +*/ enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr }; struct pmic_otp_prog_t{ @@ -47,7 +48,8 @@ struct pmic_otp_prog_t pmic_otp_prog[] = { {pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134 {pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138 {pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139 -{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142 +{pmic_i2c, 0xD0, 0x0F}, // Auto gen from Row142 +{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143 {pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147 {pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150 {pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151 @@ -185,4 +187,4 @@ struct pmic_otp_prog_t pmic_otp_prog[] = { {pmic_delay, 0, 500}, {pmic_pwr, 0, 1}, #endif -};
\ No newline at end of file +}; diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS index a1217a47bdc..3ee2b331526 100644 --- a/board/toradex/colibri_vf/MAINTAINERS +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -1,10 +1,12 @@ Colibri VFxx M: Stefan Agner <stefan.agner@toradex.com> +W: http://developer.toradex.com/software/linux/linux-software +W: https://www.toradex.com/community S: Maintained F: board/toradex/colibri_vf/ F: include/configs/colibri_vf.h F: configs/colibri_vf_defconfig -F: configs/colibri_vf_dtb_defconfig F: arch/arm/dts/vf-colibri.dtsi +F: arch/arm/dts/vf-colibri-u-boot.dtsi F: arch/arm/dts/vf500-colibri.dts F: arch/arm/dts/vf610-colibri.dts diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 79f702f2bf1..9d63fbf3bd1 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -1,48 +1,41 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2015 Toradex, Inc. + * Copyright 2015-2019 Toradex, Inc. * * Based on vf610twr.c: * Copyright 2013 Freescale Semiconductor, Inc. */ #include <common.h> -#include <asm/io.h> + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/ddrmc-vf610.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux-vf610.h> -#include <asm/arch/ddrmc-vf610.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/clock.h> -#include <mmc.h> +#include <asm/gpio.h> +#include <asm/io.h> #include <fdt_support.h> -#include <fsl_esdhc.h> #include <fsl_dcu_fb.h> +#include <g_dnl.h> #include <jffs2/load_kernel.h> -#include <miiphy.h> #include <mtd_node.h> -#include <netdev.h> -#include <i2c.h> -#include <g_dnl.h> -#include <asm/gpio.h> #include <usb.h> + #include "../common/tdx-common.h" DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE) - -#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) - -#define USB_PEN_GPIO 83 -#define USB_CDET_GPIO 102 #define PTC0_GPIO_45 45 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { + { DDRMC_CR79_CTLUPD_AREF(1), 79 }, + /* sets manual values for read lvl. (gate) delay of data slice 0/1 */ + { DDRMC_CR105_RDLVL_DL_0(28), 105 }, + { DDRMC_CR106_RDLVL_GTDL_0(24), 106 }, + { DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 }, + { DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 }, + /* AXI */ { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, @@ -89,11 +82,6 @@ static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { { 0, -1 } }; -static const iomux_v3_cfg_t usb_pads[] = { - VF610_PAD_PTD4__GPIO_83, - VF610_PAD_PTC29__GPIO_102, -}; - int dram_init(void) { static const struct ddr3_jedec_timings timings = { @@ -120,15 +108,21 @@ int dram_init(void) .tras_lockout = 0, .tdal = 12, .bstlen = 3, - .tdll = 512, + .tdll = 512, /* not applicable since freq. scaling + * is not used + */ .trp_ab = 6, .tref = 3120, .trfc = 64, .tref_int = 0, .tpdex = 3, .txpdll = 10, - .txsnr = 48, - .txsr = 468, + .txsnr = 68, /* changed to conform to JEDEC + * specifications + */ + .txsr = 506, /* changed to conform to JEDEC + * specifications + */ .cksrx = 5, .cksre = 5, .freq_chg_en = 0, @@ -147,92 +141,12 @@ int dram_init(void) .wldqsen = 25, }; - ddrmc_setup_iomux(NULL, 0); - ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2); gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } -static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); -} - -static void setup_iomux_enet(void) -{ - static const iomux_v3_cfg_t enet0_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); -} - -static void setup_iomux_i2c(void) -{ - static const iomux_v3_cfg_t i2c0_pads[] = { - VF610_PAD_PTB14__I2C0_SCL, - VF610_PAD_PTB15__I2C0_SDA, - }; - - imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); -} - -#ifdef CONFIG_NAND_VF610_NFC -static void setup_iomux_nfc(void) -{ - static const iomux_v3_cfg_t nfc_pads[] = { - VF610_PAD_PTD23__NF_IO7, - VF610_PAD_PTD22__NF_IO6, - VF610_PAD_PTD21__NF_IO5, - VF610_PAD_PTD20__NF_IO4, - VF610_PAD_PTD19__NF_IO3, - VF610_PAD_PTD18__NF_IO2, - VF610_PAD_PTD17__NF_IO1, - VF610_PAD_PTD16__NF_IO0, - VF610_PAD_PTB24__NF_WE_B, - VF610_PAD_PTB25__NF_CE0_B, - VF610_PAD_PTB27__NF_RE_B, - VF610_PAD_PTC26__NF_RB_B, - VF610_PAD_PTC27__NF_ALE, - VF610_PAD_PTC28__NF_CLE - }; - - imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); -} -#endif - -#ifdef CONFIG_FSL_DSPI -static void setup_iomux_dspi(void) -{ - static const iomux_v3_cfg_t dspi1_pads[] = { - VF610_PAD_PTD5__DSPI1_CS0, - VF610_PAD_PTD6__DSPI1_SIN, - VF610_PAD_PTD7__DSPI1_SOUT, - VF610_PAD_PTD8__DSPI1_SCK, - }; - - imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads)); -} -#endif - #ifdef CONFIG_VYBRID_GPIO static void setup_iomux_gpio(void) { @@ -331,37 +245,6 @@ static void setup_tcon(void) } #endif -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {ESDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - /* eSDHC1 is always present */ - return 1; -} - -int board_mmc_init(bd_t *bis) -{ - static const iomux_v3_cfg_t esdhc1_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), - }; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - imx_iomux_v3_setup_multiple_pads( - esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); - - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} -#endif - static inline int is_colibri_vf61(void) { struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR; @@ -394,7 +277,7 @@ static void clock_init(void) CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | - CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); + CCM_CCGR4_GPC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, @@ -483,34 +366,15 @@ static void mscm_init(void) writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); } -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - int board_early_init_f(void) { clock_init(); mscm_init(); - setup_iomux_uart(); - setup_iomux_enet(); - setup_iomux_i2c(); -#ifdef CONFIG_NAND_VF610_NFC - setup_iomux_nfc(); -#endif - #ifdef CONFIG_VYBRID_GPIO setup_iomux_gpio(); #endif -#ifdef CONFIG_FSL_DSPI - setup_iomux_dspi(); -#endif - #ifdef CONFIG_VIDEO_FSL_DCU_FB setup_tcon(); setup_iomux_fsl_dcu(); @@ -548,22 +412,17 @@ int board_init(void) * so we must use the external oscillator in order * to maintain correct time in the hwclock */ - setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); -#ifdef CONFIG_USB_EHCI_VF - gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); -#endif - return 0; } int checkboard(void) { if (is_colibri_vf61()) - puts("Board: Colibri VF61\n"); + puts("Model: Toradex Colibri VF61\n"); else - puts("Board: Colibri VF50\n"); + puts("Model: Toradex Colibri VF50\n"); return 0; } @@ -591,49 +450,6 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif -#ifdef CONFIG_USB_EHCI_VF -int board_ehci_hcd_init(int port) -{ - imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); - - switch (port) { - case 0: - /* USBC does not have PEN, also configured as USB client only */ - break; - case 1: - gpio_request(USB_PEN_GPIO, "usb-pen-gpio"); - gpio_direction_output(USB_PEN_GPIO, 0); - break; - } - return 0; -} - -int board_usb_phy_mode(int port) -{ - switch (port) { - case 0: - /* - * Port 0 is used only in client mode on Colibri Vybrid modules - * Check for state of USB client gpio pin and accordingly return - * USB_INIT_DEVICE or USB_INIT_HOST. - */ - if (gpio_get_value(USB_CDET_GPIO)) - return USB_INIT_DEVICE; - else - return USB_INIT_HOST; - case 1: - /* Port 1 is used only in host mode on Colibri Vybrid modules */ - return USB_INIT_HOST; - default: - /* - * There are only two USB controllers on Vybrid. Ideally we will - * not reach here. However return USB_INIT_HOST if we do. - */ - return USB_INIT_HOST; - } -} -#endif - /* * Backlight off before OS handover */ diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index d4f5b1803ad..b90077bedc0 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -261,7 +261,7 @@ int read_tdx_cfg_block(void) } /* Cap product id to avoid issues with a yet unknown one */ - if (tdx_hw_tag.prodid > (sizeof(toradex_modules) / + if (tdx_hw_tag.prodid >= (sizeof(toradex_modules) / sizeof(toradex_modules[0]))) tdx_hw_tag.prodid = 0; @@ -418,6 +418,7 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc, int offset = 0; int ret = CMD_RET_SUCCESS; int err; + int force_overwrite = 0; /* Allocate RAM area for config block */ config_block = memalign(ARCH_DMA_MINALIGN, size); @@ -428,6 +429,11 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc, memset(config_block, 0xff, size); + if (argc >= 3) { + if (argv[2][0] == '-' && argv[2][1] == 'y') + force_overwrite = 1; + } + read_tdx_cfg_block(); if (valid_cfgblock) { #if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND) @@ -448,24 +454,31 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc, CONFIG_TDX_CFG_BLOCK_OFFSET); goto out; #else - char message[CONFIG_SYS_CBSIZE]; - sprintf(message, - "A valid Toradex config block is present, still recreate? [y/N] "); + if (!force_overwrite) { + char message[CONFIG_SYS_CBSIZE]; - if (!cli_readline(message)) - goto out; + sprintf(message, + "A valid Toradex config block is present, still recreate? [y/N] "); - if (console_buffer[0] != 'y' && console_buffer[0] != 'Y') - goto out; + if (!cli_readline(message)) + goto out; + + if (console_buffer[0] != 'y' && + console_buffer[0] != 'Y') + goto out; + } #endif } /* Parse new Toradex config block data... */ - if (argc < 3) + if (argc < 3 || (force_overwrite && argc < 4)) { err = get_cfgblock_interactive(); - else - err = get_cfgblock_barcode(argv[2]); - + } else { + if (force_overwrite) + err = get_cfgblock_barcode(argv[3]); + else + err = get_cfgblock_barcode(argv[2]); + } if (err) { ret = CMD_RET_FAILURE; goto out; @@ -549,8 +562,8 @@ static int do_cfgblock(cmd_tbl_t *cmdtp, int flag, int argc, } U_BOOT_CMD( - cfgblock, 3, 0, do_cfgblock, + cfgblock, 4, 0, do_cfgblock, "Toradex config block handling commands", - "create [barcode] - (Re-)create Toradex config block\n" + "create [-y] [barcode] - (Re-)create Toradex config block\n" "cfgblock reload - Reload Toradex config block from flash" ); diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index fde230c955a..2d560cceaf5 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -12,6 +12,8 @@ #include <asm/setup.h> #include "tdx-common.h" +#define TORADEX_OUI 0x00142dUL + #ifdef CONFIG_TDX_CFG_BLOCK static char tdx_serial_str[9]; static char tdx_board_rev_str[6]; @@ -68,20 +70,25 @@ int show_board_info(void) unsigned char ethaddr[6]; if (read_tdx_cfg_block()) { - printf("Missing Toradex config block\n"); + printf("MISSING TORADEX CONFIG BLOCK\n"); + tdx_eth_addr.oui = htonl(TORADEX_OUI << 8); + tdx_eth_addr.nic = htonl(tdx_serial << 8); checkboard(); - return 0; + } else { + sprintf(tdx_serial_str, "%08u", tdx_serial); + sprintf(tdx_board_rev_str, "V%1d.%1d%c", + tdx_hw_tag.ver_major, + tdx_hw_tag.ver_minor, + (char)tdx_hw_tag.ver_assembly + 'A'); + + env_set("serial#", tdx_serial_str); + + printf("Model: Toradex %s %s, Serial# %s\n", + toradex_modules[tdx_hw_tag.prodid], + tdx_board_rev_str, + tdx_serial_str); } - /* board serial-number */ - sprintf(tdx_serial_str, "%08u", tdx_serial); - sprintf(tdx_board_rev_str, "V%1d.%1d%c", - tdx_hw_tag.ver_major, - tdx_hw_tag.ver_minor, - (char)tdx_hw_tag.ver_assembly + 'A'); - - env_set("serial#", tdx_serial_str); - /* * Check if environment contains a valid MAC address, * set the one from config block if not @@ -101,11 +108,6 @@ int show_board_info(void) } #endif - printf("Model: Toradex %s %s, Serial# %s\n", - toradex_modules[tdx_hw_tag.prodid], - tdx_board_rev_str, - tdx_serial_str); - return 0; } diff --git a/board/wandboard/MAINTAINERS b/board/wandboard/MAINTAINERS index d7cbae8f950..00a31a93462 100644 --- a/board/wandboard/MAINTAINERS +++ b/board/wandboard/MAINTAINERS @@ -1,6 +1,9 @@ WANDBOARD BOARD M: Fabio Estevam <fabio.estevam@nxp.com> S: Maintained +F: arch/arm/dts/imx6qdl-wandboard.dtsi +F: arch/arm/dts/imx6qdl-wandboard-revb1.dtsi +F: arch/arm/dts/imx6dl-wandboard-revb1.dts F: board/wandboard/ F: include/configs/wandboard.h F: configs/wandboard_defconfig diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c index 9c3350019c8..000cb109fc1 100644 --- a/board/wandboard/spl.c +++ b/board/wandboard/spl.c @@ -422,4 +422,96 @@ void board_init_f(ulong dummy) /* DDR initialization */ spl_dram_init(); } + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) +#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC3_BASE_ADDR}, + {USDHC1_BASE_ADDR}, +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + /* Carrier MicroSD Card Detect */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + /* SOM MicroSD Card Detect */ + IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + u32 index = 0; + + /* + * Following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 SOM MicroSD + * mmc1 Carrier board MicroSD + */ + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + SETUP_IOMUX_PADS(usdhc3_pads); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 4; + gpio_direction_input(USDHC3_CD_GPIO); + break; + case 1: + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].max_bus_width = 4; + gpio_direction_input(USDHC1_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; + } + + return 0; +} + #endif diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 6af1b458829..69fbc8b6907 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -22,8 +22,6 @@ #include <asm/io.h> #include <linux/sizes.h> #include <common.h> -#include <fsl_esdhc.h> -#include <mmc.h> #include <miiphy.h> #include <netdev.h> #include <phy.h> @@ -37,10 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) @@ -48,8 +42,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) -#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) -#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) #define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13) #define REV_DETECTION IMX_GPIO_NR(2, 28) @@ -68,28 +60,6 @@ static iomux_v3_cfg_t const uart1_pads[] = { IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; -static iomux_v3_cfg_t const usdhc1_pads[] = { - IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - /* Carrier MicroSD Card Detect */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - /* SOM MicroSD Card Detect */ - IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), @@ -131,80 +101,20 @@ static void setup_iomux_enet(void) if (with_pmic) { SETUP_IOMUX_PADS(enet_ar8035_power_pads); /* enable AR8035 POWER */ + gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER"); gpio_direction_output(ETH_PHY_AR8035_POWER, 0); } /* wait until 3.3V of PHY and clock become stable */ mdelay(10); /* Reset AR8031 PHY */ + gpio_request(ETH_PHY_RESET, "PHY_RESET"); gpio_direction_output(ETH_PHY_RESET, 0); mdelay(10); gpio_set_value(ETH_PHY_RESET, 1); udelay(100); } -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR}, - {USDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = !gpio_get_value(USDHC3_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - u32 index = 0; - - /* - * Following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 SOM MicroSD - * mmc1 Carrier board MicroSD - */ - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - SETUP_IOMUX_PADS(usdhc3_pads); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[0].max_bus_width = 4; - gpio_direction_input(USDHC3_CD_GPIO); - break; - case 1: - SETUP_IOMUX_PADS(usdhc1_pads); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - usdhc_cfg[1].max_bus_width = 4; - gpio_direction_input(USDHC1_CD_GPIO); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} - static int ar8031_phy_fixup(struct phy_device *phydev) { unsigned short val; @@ -348,14 +258,29 @@ static void do_enable_hdmi(struct display_info_t const *dev) static int detect_i2c(struct display_info_t const *dev) { +#ifdef CONFIG_DM_I2C + struct udevice *bus, *udev; + int rc; + + rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus); + if (rc) + return rc; + rc = dm_i2c_probe(bus, dev->addr, 0, &udev); + if (rc) + return 0; + return 1; +#else return (0 == i2c_set_bus_num(dev->bus)) && (0 == i2c_probe(dev->addr)); +#endif } static void enable_fwadapt_7wvga(struct display_info_t const *dev) { SETUP_IOMUX_PADS(fwadapt_7wvga_pads); + gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN"); + gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN"); gpio_direction_output(IMX_GPIO_NR(2, 10), 1); gpio_direction_output(IMX_GPIO_NR(2, 11), 1); } @@ -418,6 +343,7 @@ static void setup_display(void) /* Disable LCD backlight */ SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20); + gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN"); gpio_direction_input(IMX_GPIO_NR(4, 20)); } #endif /* CONFIG_VIDEO_IPUV3 */ @@ -443,24 +369,30 @@ int board_early_init_f(void) int power_init_board(void) { - struct pmic *p; - u32 reg; - - /* configure PFUZE100 PMIC */ - power_pfuze100_init(PMIC_I2C_BUS); - p = pmic_get("PFUZE100"); - if (p && !pmic_probe(p)) { - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); - with_pmic = true; - - /* Set VGEN2 to 1.5V and enable */ - pmic_reg_read(p, PFUZE100_VGEN2VOL, ®); - reg &= ~(LDO_VOL_MASK); - reg |= (LDOA_1_50V | (1 << (LDO_EN))); - pmic_reg_write(p, PFUZE100_VGEN2VOL, reg); + struct udevice *dev; + int reg, ret; + + puts("PMIC: "); + + ret = pmic_get("pfuze100", &dev); + if (ret < 0) { + printf("pmic_get() ret %d\n", ret); + return 0; } + reg = pmic_reg_read(dev, PFUZE100_DEVICEID); + if (reg < 0) { + printf("pmic_reg_read() ret %d\n", reg); + return 0; + } + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + with_pmic = true; + + /* Set VGEN2 to 1.5V and enable */ + reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL); + reg &= ~(LDO_VOL_MASK); + reg |= (LDOA_1_50V | (1 << (LDO_EN))); + pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg); return 0; } @@ -531,13 +463,13 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #if defined(CONFIG_VIDEO_IPUV3) - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); + setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info); if (is_mx6dq() || is_mx6dqp()) { - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info); + setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6q_i2c2_pad_info); + setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6q_i2c3_pad_info); } else { - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info); + setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info); + setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6dl_i2c3_pad_info); } setup_display(); @@ -548,6 +480,8 @@ int board_init(void) int checkboard(void) { + gpio_request(REV_DETECTION, "REV_DETECT"); + if (is_revd1()) puts("Board: Wandboard rev D1\n"); else if (is_revc1()) diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 86dabd37360..06695208bc8 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -9,12 +9,14 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_CMD_HDMIDETECT=y -CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q" CONFIG_BOOTDELAY=1 # CONFIG_CONSOLE_MUX is not set -CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set @@ -26,9 +28,7 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y -CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Apalis iMX6 # " -CONFIG_CMD_BOOTZ=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set @@ -38,30 +38,41 @@ CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6-apalis" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DWC_AHSATA=y CONFIG_DFU_MMC=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_SCSI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y -CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y CONFIG_USB_KEYBOARD=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" @@ -70,8 +81,8 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y CONFIG_OF_LIBFDT_OVERLAY=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/apalis_imx6_nospl_com_defconfig b/configs/apalis_imx6_nospl_com_defconfig deleted file mode 100644 index b6ab5285c2a..00000000000 --- a/configs/apalis_imx6_nospl_com_defconfig +++ /dev/null @@ -1,65 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_TARGET_APALIS_IMX6=y -CONFIG_CMD_HDMIDETECT=y -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=1024" -CONFIG_BOOTDELAY=1 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_MISC_INIT_R=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Apalis iMX6 # " -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -CONFIG_CMD_ASKENV=y -CONFIG_CRC32_VERIFY=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_DWC_AHSATA=y -CONFIG_DFU_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_MII=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Toradex" -CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 -CONFIG_USB_GADGET_PRODUCT_NUM=0x4020 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_HOST_ETHER=y -CONFIG_VIDEO=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/apalis_imx6_nospl_it_defconfig b/configs/apalis_imx6_nospl_it_defconfig deleted file mode 100644 index c972b11eb5b..00000000000 --- a/configs/apalis_imx6_nospl_it_defconfig +++ /dev/null @@ -1,65 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_TARGET_APALIS_IMX6=y -CONFIG_CMD_HDMIDETECT=y -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=2048" -CONFIG_BOOTDELAY=1 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_MISC_INIT_R=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Apalis iMX6 # " -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -CONFIG_CMD_ASKENV=y -CONFIG_CRC32_VERIFY=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_DWC_AHSATA=y -CONFIG_DFU_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_MII=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Toradex" -CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 -CONFIG_USB_GADGET_PRODUCT_NUM=0x4020 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_HOST_ETHER=y -CONFIG_VIDEO=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index b852b4d630a..1dd2c3b6b88 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -55,6 +55,7 @@ CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig index 7806d0a41c0..e58541f7e07 100644 --- a/configs/aristainetos2b_defconfig +++ b/configs/aristainetos2b_defconfig @@ -53,6 +53,7 @@ CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig index bad6aebf006..0f2412ba801 100644 --- a/configs/aristainetos_defconfig +++ b/configs/aristainetos_defconfig @@ -53,6 +53,7 @@ CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index 9e31b4ac979..439207fd39a 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -2,15 +2,18 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_SYS_TEXT_BASE=0x3f401000 +CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_TARGET_BK4R1=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_EEPROM=y +# CONFIG_CMD_ELF is not set CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DM=y +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -19,19 +22,44 @@ CONFIG_CMD_SF=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y +CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nand0=NAND,nor0=NOR" -CONFIG_MTDPARTS_DEFAULT="mtdparts=NAND:640k(bootloader),128k(env1),128k(env2),128k(dtb),6144k(kernel),-(root);NOR:-(nor)" +CONFIG_MTDIDS_DEFAULT="nand0=vf610_nfc,nor0=NOR" +CONFIG_MTDPARTS_DEFAULT="mtdparts=vf610_nfc:2048k(bootloader),128k(env1),128k(env2),10240k(initrd),40960k(dtbkernel),-(system);NOR:-(nor)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="bk4r1" +CONFIG_DEFAULT_DEVICE_TREE="vf610-bk4r1" CONFIG_ENV_IS_IN_NAND=y +CONFIG_NETCONSOLE=y CONFIG_DM=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y +CONFIG_SYS_BOOTCOUNT_ADDR=0x4006e02c CONFIG_DM_GPIO=y CONFIG_VYBRID_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2 +CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_EEPROM_SIZE=32768 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y +CONFIG_MTD=y CONFIG_NAND_VF610_NFC=y +CONFIG_NAND_VF610_NFC_DT=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y @@ -39,10 +67,18 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_VYBRID=y +CONFIG_DM_RTC=y CONFIG_RTC_M41T62=y +# CONFIG_SPL_SERIAL_PRESENT is not set +# CONFIG_TPL_SERIAL_PRESENT is not set CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig index 2311c4f3aae..d5d170f3087 100644 --- a/configs/cgtqmx6eval_defconfig +++ b/configs/cgtqmx6eval_defconfig @@ -74,5 +74,6 @@ CONFIG_CI_UDC=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 6156ac2bee4..4a46bb58c33 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -51,6 +51,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-cm-fx6" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DWC_AHSATA=y +# CONFIG_DWC_AHSATA_AHCI is not set CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y @@ -78,4 +79,5 @@ CONFIG_DM_USB=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 20722813545..bf05c688072 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -9,12 +9,13 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_CMD_HDMIDETECT=y -CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL" CONFIG_BOOTDELAY=1 # CONFIG_CONSOLE_MUX is not set -CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set @@ -26,9 +27,7 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_USB_SDP_SUPPORT=y -CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Colibri iMX6 # " -CONFIG_CMD_BOOTZ=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set @@ -38,28 +37,38 @@ CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6-colibri" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y -CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y CONFIG_USB_KEYBOARD=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" @@ -68,8 +77,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IPUV3=y CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y CONFIG_OF_LIBFDT_OVERLAY=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/colibri_imx6_nospl_defconfig b/configs/colibri_imx6_nospl_defconfig deleted file mode 100644 index 5e9490bc421..00000000000 --- a/configs/colibri_imx6_nospl_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_TARGET_COLIBRI_IMX6=y -CONFIG_CMD_HDMIDETECT=y -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg,MX6DL,DDR_MB=256" -CONFIG_BOOTDELAY=1 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_MISC_INIT_R=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Colibri iMX6 # " -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -CONFIG_CMD_ASKENV=y -CONFIG_CRC32_VERIFY=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_DFU_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_MII=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Toradex" -CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 -CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_HOST_ETHER=y -CONFIG_VIDEO=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 41925012571..8f6cceca7fd 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_SYS_TEXT_BASE=0x3f401000 +CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_TARGET_COLIBRI_VF=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_NR_DRAM_BANKS=1 @@ -16,11 +17,18 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y # CONFIG_CMDLINE_EDITING is not set # CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="Colibri VFxx # " +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y +CONFIG_CMD_DM=y +# CONFIG_CMD_FLASH is not set CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADB is not set @@ -45,17 +53,28 @@ CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri" CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y -CONFIG_DFU_MMC=y CONFIG_DFU_NAND=y CONFIG_DM_GPIO=y CONFIG_VYBRID_GPIO=y +CONFIG_DM_MMC=y +# CONFIG_MMC_HW_PARTITIONING is not set CONFIG_FSL_ESDHC=y +CONFIG_MTD=y CONFIG_NAND_VF610_NFC=y +CONFIG_NAND_VF610_NFC_DT=y CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_VYBRID=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +# CONFIG_SPL_SERIAL_PRESENT is not set +# CONFIG_TPL_SERIAL_PRESENT is not set CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_USB=y @@ -72,4 +91,5 @@ CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y CONFIG_SYS_CONSOLE_FG_COL=0x00 CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_FDT_FIXUP_PARTITIONS=y # CONFIG_EFI_UNICODE_CAPITALIZATION is not set diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig index 6ca5d2bb329..c274c3af0ee 100644 --- a/configs/dms-ba16-1g_defconfig +++ b/configs/dms-ba16-1g_defconfig @@ -53,5 +53,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig index 4ad3df6214a..6c27c3865c8 100644 --- a/configs/dms-ba16_defconfig +++ b/configs/dms-ba16_defconfig @@ -52,5 +52,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 7319919998f..1db59c7940c 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -50,3 +50,17 @@ CONFIG_MXC_SPI=y CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y # CONFIG_EFI_LOADER is not set +CONFIG_DM=y +CONFIG_CMD_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-bx50v3" +CONFIG_DM_MMC=y +CONFIG_BLK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_GPIO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IPUV3=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 07171c70099..2e041270144 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -84,6 +84,7 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_HEXDUMP=y CONFIG_OF_LIBFDT=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 0ed2209e3b7..275aa89ed6e 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -88,6 +88,7 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_HEXDUMP=y CONFIG_OF_LIBFDT=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 57e4a999aba..477d205bc3f 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -87,6 +87,7 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_HEXDUMP=y CONFIG_OF_LIBFDT=y diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index 69c45b948b3..7b1f7abc4ed 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -50,5 +50,5 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y CONFIG_VIDEO_IPUV3=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index b53a5010e5d..1e26f7a8c91 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -51,5 +51,5 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y CONFIG_VIDEO_IPUV3=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 24e99718e63..223f732207f 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -67,5 +67,5 @@ CONFIG_PINCTRL_IMX6=y CONFIG_DEBUG_UART_MXC=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y CONFIG_VIDEO_IPUV3=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index cf149d615b3..8702426561f 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -50,5 +50,5 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y CONFIG_VIDEO_IPUV3=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 5555e05030b..e830b2c92e1 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -64,6 +64,7 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_IMX_WATCHDOG=y CONFIG_FAT_WRITE=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index 320e14e2bef..a2a0390ca6e 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -35,5 +35,6 @@ CONFIG_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index e93e81f3c3e..dc0b3b3f779 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -31,5 +31,6 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig index 07f3a23028d..831d50925f3 100644 --- a/configs/mx53cx9020_defconfig +++ b/configs/mx53cx9020_defconfig @@ -32,4 +32,5 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX5=y CONFIG_MXC_UART=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index 4e161371e36..776fc8bab44 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -32,5 +32,6 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 28540719df3..2a6183b77b5 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -39,6 +39,16 @@ CONFIG_RTC_S35392A=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y +CONFIG_DM=y +CONFIG_CMD_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx53-ppd" +CONFIG_DM_MMC=y +CONFIG_BLK=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX5=y +CONFIG_OF_BOARD_SETUP=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 506e3a71df1..f1c2fd4dba8 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -39,5 +39,6 @@ CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_KEYBOARD=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 39893528b61..8a5f9dbb93b 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -57,5 +57,6 @@ CONFIG_CI_UDC=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index d0f950bb6ec..23fd9977d0e 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -84,5 +84,6 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 0fd32aa1d62..eaf0f010046 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -95,5 +95,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y -CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index debe60b3f0e..5b3899d5901 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -59,5 +59,6 @@ CONFIG_CI_UDC=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 96d9c02b477..d89069a0d5d 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -59,5 +59,6 @@ CONFIG_CI_UDC=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 5bc4219deee..e9214d472b6 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -61,5 +61,6 @@ CONFIG_CI_UDC=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index 37fa4059311..f1480f15c75 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -61,5 +61,6 @@ CONFIG_CI_UDC=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index 1d3f0151fe3..b920db0dad3 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -59,5 +59,6 @@ CONFIG_CI_UDC=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index 5bf2b3a021f..c3b8032d471 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -59,5 +59,6 @@ CONFIG_CI_UDC=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 4c9c1cb9eb5..103d9183cb1 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -58,6 +58,7 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT=y diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index e207df51a80..fd093b35c23 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -9,7 +9,6 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y -CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -18,23 +17,53 @@ CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nand0=NAND" CONFIG_MTDPARTS_DEFAULT="mtdparts=NAND:640k(bootloader),128k(env1),128k(env2),128k(dtb),6144k(kernel),-(root)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="pcm052" +CONFIG_DEFAULT_DEVICE_TREE="vf610-pcm052" CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_VYBRID_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2 +CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_SYS_I2C_MXC_I2C4=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_EEPROM_SIZE=32768 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y +CONFIG_MTD=y CONFIG_NAND_VF610_NFC=y +CONFIG_NAND_VF610_NFC_DT=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_VYBRID=y +CONFIG_DM_RTC=y CONFIG_RTC_M41T62=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index e3d16df6a89..84561c82322 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -35,5 +35,6 @@ CONFIG_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig index 51fa98d5a93..db6ee8fc3fa 100644 --- a/configs/riotboard_spl_defconfig +++ b/configs/riotboard_spl_defconfig @@ -44,6 +44,7 @@ CONFIG_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_VIDEO=y +CONFIG_VIDEO_IPUV3=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y CONFIG_SPL_OF_LIBFDT=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index 78beb9a5220..96b813d8770 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -4,6 +4,7 @@ CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_TARGET_TBS2910=y CONFIG_CMD_HDMIDETECT=y +CONFIG_AHCI=y CONFIG_NR_DRAM_BANKS=1 CONFIG_BOOTDELAY=3 CONFIG_PRE_CONSOLE_BUFFER=y @@ -14,6 +15,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Matrix U-Boot> " CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FDT is not set CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -28,7 +30,6 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y @@ -36,15 +37,28 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-tbs2910" CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_DWC_AHSATA=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_KEYBOARD=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y CONFIG_DM_THERMAL=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y @@ -54,5 +68,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_I2C_EDID=y CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y +CONFIG_VIDEO_IPUV3=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index 5725487446b..ba0c8442620 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_CMD_HDMIDETECT=y +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" @@ -32,15 +33,29 @@ CONFIG_CMD_SATA=y CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-wandboard-revb1" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_DWC_AHSATA=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_SCSI=y CONFIG_DM_THERMAL=y CONFIG_USB=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y +CONFIG_DM_USB=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IPUV3=y diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 7ebee75c0a5..593e9cbc1f2 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -66,6 +66,14 @@ config DWC_AHSATA Enable this driver to support the DWC AHSATA SATA controller found in i.MX5 and i.MX6 SoCs. +config DWC_AHSATA_AHCI + bool "Enable DWC AHSATA AHCI driver support" + depends on DWC_AHSATA + depends on AHCI + default y + help + Enable this option unless you need your private ahci implementation + config FSL_SATA bool "Enable Freescale SATA controller driver support" select LIBATA diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index 4c5b98482ff..afced8e7e3f 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -16,6 +16,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#include <asm/mach-imx/sata.h> #include <linux/bitops.h> #include <linux/ctype.h> #include <linux/errno.h> @@ -511,15 +512,9 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) static void dwc_ahsata_print_info(struct blk_desc *pdev) { printf("SATA Device Info:\n\r"); -#ifdef CONFIG_SYS_64BIT_LBA printf("S/N: %s\n\rProduct model number: %s\n\r" - "Firmware version: %s\n\rCapacity: %lld sectors\n\r", + "Firmware version: %s\n\rCapacity: " LBAFU " sectors\n\r", pdev->product, pdev->vendor, pdev->revision, pdev->lba); -#else - printf("S/N: %s\n\rProduct model number: %s\n\r" - "Firmware version: %s\n\rCapacity: %ld sectors\n\r", - pdev->product, pdev->vendor, pdev->revision, pdev->lba); -#endif } static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id) @@ -754,7 +749,6 @@ static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv, u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 }; u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 }; u8 product[ATA_ID_PROD_LEN + 1] = { 0 }; - u64 n_sectors; u8 port = uc_priv->hard_port_no; ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS); @@ -773,9 +767,8 @@ static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv, ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); memcpy(pdev->vendor, product, sizeof(product)); - /* Totoal sectors */ - n_sectors = ata_id_n_sectors(id); - pdev->lba = (u32)n_sectors; + /* Total sectors */ + pdev->lba = ata_id_n_sectors(id); pdev->type = DEV_TYPE_HARDDISK; pdev->blksz = ATA_SECT_SIZE; @@ -1028,6 +1021,9 @@ int dwc_ahsata_probe(struct udevice *dev) struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); int ret; +#if defined(CONFIG_MX6) + setup_sata(); +#endif uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI; uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev); @@ -1075,4 +1071,24 @@ U_BOOT_DRIVER(dwc_ahsata_blk) = { .ops = &dwc_ahsata_blk_ops, }; +#if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI) +struct ahci_ops dwc_ahsata_ahci_ops = { + .port_status = dwc_ahsata_port_status, + .reset = dwc_ahsata_bus_reset, + .scan = dwc_ahsata_scan, +}; + +static const struct udevice_id dwc_ahsata_ahci_ids[] = { + { .compatible = "fsl,imx6q-ahci" }, + { } +}; + +U_BOOT_DRIVER(dwc_ahsata_ahci) = { + .name = "dwc_ahsata_ahci", + .id = UCLASS_AHCI, + .of_match = dwc_ahsata_ahci_ids, + .ops = &dwc_ahsata_ahci_ops, + .probe = dwc_ahsata_probe, +}; +#endif #endif diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index d6e677fba84..0e645f58be0 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -128,6 +128,8 @@ config JZ4780_EFUSE config MXC_OCOTP bool "Enable MXC OCOTP Driver" + depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_VF610 + default y help If you say Y here, you will get support for the One Time Programmable memory pages that are stored on the some diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 77d0b3a01f4..d0e5426a99d 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -190,7 +190,7 @@ config FEC_MXC_MDIO_BASE config FEC_MXC bool "FEC Ethernet controller" - depends on MX5 || MX6 || MX7 || IMX8 + depends on MX5 || MX6 || MX7 || IMX8 || VF610 help This driver supports the 10/100 Fast Ethernet controller for NXP i.MX processors. diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 84f010d8057..a672250e16a 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1491,6 +1491,7 @@ static const struct udevice_id fecmxc_ids[] = { { .compatible = "fsl,imx6ul-fec" }, { .compatible = "fsl,imx53-fec" }, { .compatible = "fsl,imx7d-fec" }, + { .compatible = "fsl,mvf600-fec" }, { } }; diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index ba1e6bfa43b..0fbc1158011 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -154,6 +154,13 @@ config USB_EHCI_OMAP Enables support for the on-chip EHCI controller on OMAP3 and later SoCs. +config USB_EHCI_VF + bool "Support for Vybrid on-chip EHCI USB controller" + depends on ARCH_VF610 + default y + help + Enables support for the on-chip EHCI controller on Vybrid SoCs. + if USB_EHCI_MX7 config MXC_USB_OTG_HACTIVE diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 43412873c98..c3781b160d9 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -538,6 +538,8 @@ config VIDEO_TEGRA124 source "drivers/video/bridge/Kconfig" +source "drivers/video/imx/Kconfig" + config VIDEO bool "Enable legacy video support" depends on !DM_VIDEO @@ -547,13 +549,6 @@ config VIDEO model. Video drivers typically provide a colour text console and cursor. -config VIDEO_IPUV3 - bool "i.MX IPUv3 Core video support" - depends on VIDEO && MX6 - help - This enables framebuffer driver for i.MX processors working - on the IPUv3(Image Processing Unit) internal graphic processor. - config CFB_CONSOLE bool "Enable colour frame buffer console" depends on VIDEO diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 671f037c350..349a207035b 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -46,7 +46,7 @@ obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o obj-$(CONFIG_VIDEO_EFI) += efi.o obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o -obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o +obj-$(CONFIG_VIDEO_IPUV3) += imx/ obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig new file mode 100644 index 00000000000..c33620e0750 --- /dev/null +++ b/drivers/video/imx/Kconfig @@ -0,0 +1,8 @@ + +config VIDEO_IPUV3 + bool "i.MX IPUv3 Core video support" + depends on (VIDEO || DM_VIDEO) && (MX5 || MX6) + help + This enables framebuffer driver for i.MX processors working + on the IPUv3(Image Processing Unit) internal graphic processor. + diff --git a/drivers/video/imx/Makefile b/drivers/video/imx/Makefile new file mode 100644 index 00000000000..179ea651fe8 --- /dev/null +++ b/drivers/video/imx/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o diff --git a/drivers/video/ipu.h b/drivers/video/imx/ipu.h index 1e02c7ab6d5..1e02c7ab6d5 100644 --- a/drivers/video/ipu.h +++ b/drivers/video/imx/ipu.h diff --git a/drivers/video/ipu_common.c b/drivers/video/imx/ipu_common.c index cbe1984e4f7..cbe1984e4f7 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/imx/ipu_common.c diff --git a/drivers/video/ipu_disp.c b/drivers/video/imx/ipu_disp.c index 5c7722962d7..5c7722962d7 100644 --- a/drivers/video/ipu_disp.c +++ b/drivers/video/imx/ipu_disp.c diff --git a/drivers/video/ipu_regs.h b/drivers/video/imx/ipu_regs.h index deb44002d75..deb44002d75 100644 --- a/drivers/video/ipu_regs.h +++ b/drivers/video/imx/ipu_regs.h diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index 23cd55de479..3e38d4bdcc3 100644 --- a/drivers/video/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -17,13 +17,17 @@ #include <linux/list.h> #include <linux/fb.h> #include <asm/io.h> +#include <asm/mach-imx/video.h> #include <malloc.h> #include <video_fb.h> -#include "videomodes.h" +#include "../videomodes.h" #include "ipu.h" #include "mxcfb.h" #include "ipu_regs.h" +#include <dm.h> +#include <video.h> + DECLARE_GLOBAL_DATA_PTR; static int mxcfb_map_video_memory(struct fb_info *fbi); @@ -401,8 +405,14 @@ static int mxcfb_map_video_memory(struct fb_info *fbi) fbi->fix.line_length; } fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN); + +#if CONFIG_IS_ENABLED(DM_VIDEO) + fbi->screen_base = (char *)gd->video_bottom; +#else fbi->screen_base = (char *)memalign(ARCH_DMA_MINALIGN, fbi->fix.smem_len); +#endif + fbi->fix.smem_start = (unsigned long)fbi->screen_base; if (fbi->screen_base == 0) { puts("Unable to allocate framebuffer memory\n"); @@ -416,7 +426,9 @@ static int mxcfb_map_video_memory(struct fb_info *fbi) fbi->screen_size = fbi->fix.smem_len; +#if CONFIG_IS_ENABLED(VIDEO) gd->fb_base = fbi->fix.smem_start; +#endif /* Clear the screen */ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); @@ -611,3 +623,78 @@ int ipuv3_fb_init(struct fb_videomode const *mode, return 0; } + +#if CONFIG_IS_ENABLED(DM_VIDEO) +enum { + /* Maximum display size we support */ + LCD_MAX_WIDTH = 1920, + LCD_MAX_HEIGHT = 1080, + LCD_MAX_LOG2_BPP = VIDEO_BPP16, +}; + +static int ipuv3_video_probe(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + u32 fb_start, fb_end; + int ret; + + debug("%s() plat: base 0x%lx, size 0x%x\n", + __func__, plat->base, plat->size); + + ret = ipu_probe(); + if (ret) + return ret; + + ret = ipu_displays_init(); + if (ret < 0) + return ret; + + ret = mxcfb_probe(gpixfmt, gdisp, gmode); + if (ret < 0) + return ret; + + uc_priv->xsize = gmode->xres; + uc_priv->ysize = gmode->yres; + uc_priv->bpix = LCD_MAX_LOG2_BPP; + + /* Enable dcache for the frame buffer */ + fb_start = plat->base & ~(MMU_SECTION_SIZE - 1); + fb_end = plat->base + plat->size; + fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT); + mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, + DCACHE_WRITEBACK); + video_set_flush_dcache(dev, true); + + return 0; +} + +struct ipuv3_video_priv { + ulong regs; +}; + +static int ipuv3_video_bind(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + + plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * + (1 << LCD_MAX_LOG2_BPP) / 8; + + return 0; +} + +static const struct udevice_id ipuv3_video_ids[] = { + { .compatible = "fsl,imx6q-ipu" }, + { } +}; + +U_BOOT_DRIVER(ipuv3_video) = { + .name = "ipuv3_video", + .id = UCLASS_VIDEO, + .of_match = ipuv3_video_ids, + .bind = ipuv3_video_bind, + .probe = ipuv3_video_probe, + .priv_auto_alloc_size = sizeof(struct ipuv3_video_priv), + .flags = DM_FLAG_PRE_RELOC, +}; +#endif /* CONFIG_DM_VIDEO */ diff --git a/drivers/video/mxcfb.h b/drivers/video/imx/mxcfb.h index 0dc38861938..0dc38861938 100644 --- a/drivers/video/mxcfb.h +++ b/drivers/video/imx/mxcfb.h diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c index 1cfeaa980fa..d7614329ffe 100644 --- a/drivers/video/videomodes.c +++ b/drivers/video/videomodes.c @@ -397,7 +397,7 @@ int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t, EDID_DETAILED_TIMING_VERTICAL_BLANKING(*t) == 0 || EDID_DETAILED_TIMING_HSYNC_OFFSET(*t) == 0 || EDID_DETAILED_TIMING_VSYNC_OFFSET(*t) == 0 || - /* 3d formats are not supported*/ + /* 3d formats are not supported */ EDID_DETAILED_TIMING_FLAG_STEREO(*t) != 0) return -EINVAL; diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index e2c70605b21..57edeee941e 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -34,8 +34,6 @@ #define CONFIG_MXC_UART -#define CONFIG_MXC_OCOTP - /* SATA Configs */ #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 @@ -217,7 +215,6 @@ /* Framebuffer */ #ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index ba4e96da505..96169f55f08 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2013-2015 Toradex, Inc. + * Copyright 2013-2019 Toradex, Inc. * * Configuration settings for the Toradex Apalis iMX6 */ @@ -34,17 +34,12 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* I2C Configs */ -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 - -/* OCOTP Configs */ -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif +#define CONFIG_SYS_MXC_I2C3_SPEED 400000 /* MMC Configs */ #define CONFIG_FSL_USDHC @@ -57,9 +52,6 @@ * SATA Configs */ #ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 #endif @@ -82,11 +74,7 @@ /* Client */ #define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_MASS_STORAGE - /* Framebuffer and LCD */ -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN @@ -115,37 +103,36 @@ #define CONFIG_LOADADDR 0x12000000 -#ifdef CONFIG_CMD_SATA -#define CONFIG_DRIVE_SATA "sata " -#else -#define CONFIG_DRIVE_SATA -#endif - -#ifdef CONFIG_CMD_MMC -#define CONFIG_DRIVE_MMC "mmc " -#else -#define CONFIG_DRIVE_MMC -#endif - -#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include <config_distro_bootcmd.h> +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" +#else /* CONFIG_SPL_BUILD */ +#define BOOTENV +#endif /* CONFIG_SPL_BUILD */ #define DFU_ALT_EMMC_INFO \ "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \ "boot part 0 1;" \ "rootfs part 0 2;" \ - "uImage fat 0 1;" \ - "imx6q-colibri-eval-v3.dtb fat 0 1;" \ - "imx6q-colibri-cam-eval-v3.dtb fat 0 1" + "zImage fat 0 1;" \ + "imx6q-apalis-eval.dtb fat 0 1;" \ + "imx6q-apalis-cam-eval.dtb fat 0 1" #define EMMC_BOOTCMD \ - "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \ + "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \ "rootwait\0" \ "emmcboot=run setup; " \ "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ "${vidargs}; echo Booting from internal eMMC chip...; " \ "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "bootz ${kernel_addr_r} ${dtbparam}\0" \ "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" @@ -155,7 +142,9 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "kernel_addr_r=0x11000000\0" \ - "ramdisk_addr_r=0x12100000\0" + "pxefile_addr_r=0x17100000\0" \ + "ramdisk_addr_r=0x12100000\0" \ + "scriptaddr=0x17000000\0" #define NFS_BOOTCMD \ "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ @@ -163,30 +152,30 @@ "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ "run nfsdtbload; dhcp ${kernel_addr_r} " \ - "&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \ + "&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \ "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" -#define SD_BOOTCMD \ - "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \ +#define SD_BOOTCMD \ + "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \ "rootwait\0" \ "sdboot=run setup; " \ "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \ "${vidargs}; echo Booting from SD card; " \ "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "bootz ${kernel_addr_r} ${dtbparam}\0" \ "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" #define USB_BOOTCMD \ - "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \ + "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext4 " \ "rootwait\0" \ "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \ "${usbargs} ${vidargs}; echo Booting from USB stick...; " \ "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "bootz ${kernel_addr_r} ${dtbparam}\0" \ "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" @@ -197,11 +186,12 @@ #define FDT_FILE "imx6q-apalis_v1_0-eval.dtb" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \ - "run nfsboot ; echo ; echo nfsboot failed ; " \ - "usb start ;" \ + "run distro_bootcmd ; " \ + "usb start ; " \ "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \ - "boot_file=uImage\0" \ + "boot_file=zImage\0" \ "console=ttymxc0\0" \ "defargs=enable_wait_mode=off vmalloc=400M\0" \ "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ @@ -214,8 +204,10 @@ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ "flash_eth.img && source ${loadaddr}\0" \ - "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \ - "${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ + "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \ + "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img " \ + "|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1" \ + " ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ "setup=setenv setupargs fec_mac=${ethaddr} " \ "consoleblank=0 no_console_suspend=1 console=tty1 " \ @@ -255,7 +247,6 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* environment organization */ - #define CONFIG_ENV_SIZE (8 * 1024) #if defined(CONFIG_ENV_IS_IN_MMC) @@ -266,8 +257,6 @@ #define CONFIG_SYS_MMC_ENV_PART 1 #endif -#define CONFIG_OF_SYSTEM_SETUP - #define CONFIG_CMD_TIME #endif /* __CONFIG_H */ diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index 4f28f524020..a24814673c5 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -187,7 +187,6 @@ /* UBI support */ /* Framebuffer */ -#define CONFIG_VIDEO_IPUV3 /* check this console not needed, after test remove it */ #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index a012705870f..05ebb7d9c5c 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -1,24 +1,271 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright (C) 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * * Copyright 2016 3ADEV <http://3adev.com> * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> * - * Configuration settings for the phytec PCM-052 SoM-based BK4R1. + * Configuration settings for BK4R1. */ +#ifndef __CONFIG_H +#define __CONFIG_H + /* Define the BK4r1-specific env commands */ -#define PCM052_EXTRA_ENV_SETTINGS \ +#define BK4_EXTRA_ENV_SETTINGS \ + "bootlimit=3\0" \ + "eraseuserdata=false\0" \ + "altbootcmd=led 5 on; " \ + "boot\0" \ "set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \ - "set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0" + "set_gpio102=mw 0x400ff0c4 0x40; mw 0x40048198 0x000011bf\0" \ + "set_gpio96=mw 0x40048180 0x282; mw 0x400ff0c4 0x1\0"\ + "set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0"\ + "set_gpio6=mw 0x40048018 0x282; mw 0x400ff008 0x40\0"\ + "manage_userdata=" MANAGE_USERDATA "\0"\ + "ncenable=true\0"\ + "ncserverip=192.168.0.77\0"\ + "if_netconsole=ping $ncserverip\0"\ + "start_netconsole=setenv ncip $serverip; setenv bootdelay 10;" \ + "setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ + "preboot=" BK4_NET_INIT \ + "if ${ncenable}; then run if_netconsole start_netconsole; fi\0" /* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/ -#define PCM052_BOOTCOMMAND "run set_gpio103; sf probe; " +#define BK4_BOOTCOMMAND "run set_gpio122; run set_gpio96; sf probe; " \ + "run manage_userdata; " + +/* Enable PREBOOT variable */ +#define CONFIG_PREBOOT + +/* Set ARP_TIMEOUT to 500ms */ +#define CONFIG_ARP_TIMEOUT 500UL + +/* Set ARP_TIMEOUT_COUNT to 3 repetitions */ +#define CONFIG_NET_RETRY_COUNT 5 /* BK4r1 net init sets GPIO122/PTE17 to enable Ethernet */ -#define PCM052_NET_INIT "run set_gpio122; " +#define BK4_NET_INIT "run set_gpio122;" + +/* Check if userdata volume shall be erased */ +#define MANAGE_USERDATA "if ${eraseuserdata}; " \ + "then ubi part system; " \ + "ubi remove userdata; " \ + "ubi create userdata; " \ + "ubi detach; " \ + "setenv eraseuserdata false; " \ + "saveenv; " \ + "fi; " + +/* Autoboot options */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT \ + "Enter passphrase to stop autoboot, booting in %d seconds\n" +#define CONFIG_AUTOBOOT_STOP_STR "123" + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* Enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 4 * SZ_1M) + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* NAND support */ +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define IMX_FEC1_BASE ENET1_BASE_ADDR + +/* QSPI Configs*/ +#ifdef CONFIG_FSL_QSPI +#define FSL_QSPI_FLASH_SIZE (SZ_16M) +#define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SYS_FSL_QSPI_LE +#endif + +#define CONFIG_LOADADDR 0x82000000 + +/* We boot from the gfxRAM area of the OCRAM. */ +#define CONFIG_BOARD_SIZE_LIMIT 520192 + +/* boot command, including the target-defined one if any */ +#define CONFIG_BOOTCOMMAND BK4_BOOTCOMMAND "run bootcmd_nand" + +/* Extra env settings (including the target-defined ones if any) */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BK4_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "blimg_file=u-boot.vyb\0" \ + "blimg_addr=0x81000000\0" \ + "dtbkernel_file=fitImage\0" \ + "dtbkernel_addr=0x82000000\0" \ + "ram_file=uRamdisk\0" \ + "ram_addr=0x83000000\0" \ + "filesys=rootfs.ubifs\0" \ + "sys_addr=0x81000000\0" \ + "nfs_root=/path/to/nfs/root\0" \ + "tftptimeout=1000\0" \ + "tftptimeoutcountmax=1000000\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "ipaddr=192.168.0.60\0" \ + "serverip=192.168.0.1\0" \ + "bootargs_base=setenv bootargs rw " \ + "console=ttyLP1,115200n8\0" \ + "bootargs_sd=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootargs_nand=setenv bootargs ${bootargs} " \ + "ubi.mtd=5 rootfstype=" \ + "ubifs root=ubi0:rootfs${active_workset}\0" \ + "bootargs_ram=setenv bootargs ${bootargs} " \ + "root=/dev/ram rw initrd=${ram_addr}\0" \ + "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \ + "fatload mmc 0:2 ${dtbkernel_addr} ${dtbkernel_file}; " \ + "bootm ${dtbkernel_addr}\0" \ + "bootcmd_nand=sf probe;run bootargs_base bootargs_nand bootargs_mtd; " \ + "ubi part dtbkernel; " \ + "ubi readvol ${dtbkernel_addr} dtbkernel${active_workset}; " \ + "led 0 on; " \ + "bootm ${dtbkernel_addr}\0" \ + "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \ + "nand read ${fdt_addr} dtb; " \ + "nand read ${kernel_addr} kernel; " \ + "nand read ${ram_addr} root; " \ + "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ + "update_bootloader_from_sd=if fatload mmc 0:2 ${blimg_addr} " \ + "${blimg_file}; " \ + "then sf probe; " \ + "mtdparts default; " \ + "nand erase.part bootloader; " \ + "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ + "update_bootloader_from_tftp=if tftp ${blimg_addr} "\ + "${tftpdir}${blimg_file}; "\ + "then sf probe; " \ + "mtdparts default; " \ + "nand erase.part bootloader; " \ + "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ + "update_dtbkernel_from_sd=if fatload mmc 0:2 ${dtbkernel_addr} " \ + "${dtbkernel_file}; " \ + "then sf probe; " \ + "ubi part dtbkernel; " \ + "ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \ + "${filesize}; " \ + "ubi detach; fi\0" \ + "update_dtbkernel_from_tftp=if tftp ${dtbkernel_addr} " \ + "${tftpdir}${dtbkernel_file}; " \ + "then sf probe; " \ + "ubi part dtbkernel; " \ + "ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \ + "${filesize}; " \ + "ubi detach; fi\0" \ + "update_ramdisk_from_sd=if fatload mmc 0:2 ${ram_addr} " \ + "${ram_file}; " \ + "then sf probe; " \ + "mtdparts default; " \ + "nand erase.part initrd; " \ + "nand write ${ram_addr} initrd ${filesize}; fi\0" \ + "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ + "then sf probe; " \ + "nand erase.part initrd; " \ + "nand write ${ram_addr} initrd ${filesize}; fi\0" \ + "update_rootfs_from_sd=if fatload mmc 0:2 ${sys_addr} " \ + "${filesys}; " \ + "then sf probe; " \ + "ubi part system; " \ + "ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \ + "ubi detach; fi\0" \ + "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \ + "then sf probe; " \ + "ubi part system; " \ + "ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \ + "ubi detach; fi\0" \ + "setup_dtbkernel=nand erase.part dtbkernel; " \ + "ubi part dtbkernel; " \ + "ubi create dtbkernel1 972000 s; " \ + "ubi create dtbkernel2 972000 s; " \ + "ubi detach\0" \ + "setup_system=nand erase.part system; " \ + "ubi part system; " \ + "ubi create rootfs1 15E15000 d; " \ + "ubi create rootfs2 15E15000 d; " \ + "ubi create userdata; " \ + "ubi detach\0" \ + "setup_nor1=" BK4_NET_INIT \ + "if tftp ${sys_addr} ${tftpdir}ubinor1.img; " \ + "then sf probe 0:0; " \ + "sf erase 0 01000000; " \ + "mtdparts default; " \ + "ubi part nor; " \ + "ubi create nor1fs; " \ + "ubi write ${sys_addr} nor1fs ${filesize}; " \ + "ubi detach; fi\0" \ + "setup_nor2=" BK4_NET_INIT \ + "if tftp ${sys_addr} ${tftpdir}ubinor2.img; " \ + "then sf probe 0:1; " \ + "sf erase 0 01000000; " \ + "mtdparts default; " \ + "ubi part nor; " \ + "ubi create nor2fs; " \ + "ubi write ${sys_addr} nor2fs ${filesize}; " \ + "ubi detach; fi\0" \ + "prepare_install_bk4r1_envs=" \ + "echo 'Preparing envs for SD card recovery!';" \ + "setenv ipaddr 192.168.0.99;" \ + "setenv serverip 192.168.0.50;" \ + "\0" \ + "install_bk4r1rs="\ + "led 0 on; " \ + "nand erase.chip; mtdparts default; "\ + "led 1 on; "\ + "run setup_dtbkernel; " \ + "run setup_system; " \ + "led 2 on;" \ + "run update_bootloader_from_sd; "\ + "run update_dtbkernel_from_sd; "\ + "run update_rootfs_from_sd; "\ + "setenv bootcmd 'run bootcmd_nand'; "\ + "saveenv; " \ + "led 3 on; " \ + "echo Finished - Please Power off, REMOVE SDCARD and set boot" \ + "source to NAND\0" \ + "active_workset=1\0" + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_MEMTEST_START 0x80010000 +#define CONFIG_SYS_MEMTEST_END 0x87C00000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Physical memory map */ +#define PHYS_SDRAM (0x80000000) +#define PHYS_SDRAM_SIZE (SZ_512M) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* add NOR to MTD env */ +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* now include standard PCM052 config */ +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE (SZ_128K) +#define CONFIG_ENV_SIZE (SZ_8K) +#define CONFIG_ENV_OFFSET 0x200000 +#define CONFIG_ENV_SIZE_REDUND (SZ_8K) +#define CONFIG_ENV_OFFSET_REDUND 0x220000 +#endif -#include "configs/pcm052.h" +#endif /* __CONFIG_H */ diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index ad0a64a9368..07c6409e8fb 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -60,7 +60,6 @@ #define CONFIG_USBD_HS /* Framebuffer */ -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index dfd96ff8d59..2e8dda8ab85 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -212,7 +212,6 @@ #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) /* Display */ -#define CONFIG_VIDEO_IPUV3 #define CONFIG_IMX_HDMI #define CONFIG_SPLASH_SCREEN diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 2d40ceb24e9..803c9be0646 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2013-2015 Toradex, Inc. + * Copyright 2013-2019 Toradex, Inc. * * Configuration settings for the Toradex Colibri iMX6 */ @@ -32,17 +32,12 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* I2C Configs */ -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 - -/* OCOTP Configs */ -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif +#define CONFIG_SYS_MXC_I2C3_SPEED 400000 /* MMC Configs */ #define CONFIG_FSL_USDHC @@ -70,11 +65,7 @@ /* Client */ #define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_MASS_STORAGE - /* Framebuffer and LCD */ -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN @@ -103,31 +94,35 @@ #define CONFIG_LOADADDR 0x12000000 -#ifdef CONFIG_CMD_MMC -#define CONFIG_DRIVE_MMC "mmc " -#else -#define CONFIG_DRIVE_MMC -#endif - -#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_MMC +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include <config_distro_bootcmd.h> +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" +#else /* CONFIG_SPL_BUILD */ +#define BOOTENV +#endif /* CONFIG_SPL_BUILD */ #define DFU_ALT_EMMC_INFO \ "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \ "boot part 0 1;" \ "rootfs part 0 2;" \ - "uImage fat 0 1;" \ - "imx6q-colibri-eval-v3.dtb fat 0 1;" \ - "imx6q-colibri-cam-eval-v3.dtb fat 0 1" + "zImage fat 0 1;" \ + "imx6dl-colibri-eval-v3.dtb fat 0 1;" \ + "imx6dl-colibri-cam-eval-v3.dtb fat 0 1" #define EMMC_BOOTCMD \ - "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \ + "emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \ "rootwait\0" \ "emmcboot=run setup; " \ "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ "${vidargs}; echo Booting from internal eMMC chip...; " \ "run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "bootz ${kernel_addr_r} ${dtbparam}\0" \ "emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" @@ -137,7 +132,9 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "kernel_addr_r=0x11000000\0" \ - "ramdisk_addr_r=0x12100000\0" + "pxefile_addr_r=0x17100000\0" \ + "ramdisk_addr_r=0x12100000\0" \ + "scriptaddr=0x17000000\0" #define NFS_BOOTCMD \ "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ @@ -145,40 +142,41 @@ "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ "run nfsdtbload; dhcp ${kernel_addr_r} " \ - "&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \ + "&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \ "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" -#define SD_BOOTCMD \ - "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \ +#define SD_BOOTCMD \ + "sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \ "rootwait\0" \ "sdboot=run setup; " \ "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \ "${vidargs}; echo Booting from SD card; " \ "run sddtbload; load mmc 1:1 ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "bootz ${kernel_addr_r} ${dtbparam}\0" \ "sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" #define USB_BOOTCMD \ - "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \ + "usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext4 " \ "rootwait\0" \ "usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \ "${usbargs} ${vidargs}; echo Booting from USB stick...; " \ "usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \ "${boot_file} && run fdt_fixup && " \ - "bootm ${kernel_addr_r} ${dtbparam}\0" \ + "bootz ${kernel_addr_r} ${dtbparam}\0" \ "usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \ "${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0" #define FDT_FILE "imx6dl-colibri-eval-v3.dtb" #define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ "bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \ - "run nfsboot ; echo ; echo nfsboot failed ; " \ - "usb start ;" \ + "run distro_bootcmd ; " \ + "usb start ; " \ "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \ - "boot_file=uImage\0" \ + "boot_file=zImage\0" \ "console=ttymxc0\0" \ "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \ "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ @@ -240,8 +238,6 @@ #define CONFIG_SYS_MMC_ENV_PART 1 #endif -#define CONFIG_OF_SYSTEM_SETUP - #define CONFIG_CMD_TIME #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 31ff8a00a69..0d57e303a1b 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2015-2016 Toradex, Inc. + * Copyright 2015-2019 Toradex, Inc. * * Configuration settings for the Toradex VF50/VF61 modules. * @@ -12,15 +12,12 @@ #define __CONFIG_H #include <asm/arch/imx-regs.h> +#include <linux/sizes.h> #define CONFIG_SYS_FSL_CLK #define CONFIG_SKIP_LOWLEVEL_INIT -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif - #ifdef CONFIG_VIDEO_FSL_DCU_FB #define CONFIG_SPLASH_SCREEN_ALIGN #define CONFIG_VIDEO_LOGO @@ -32,7 +29,7 @@ #endif /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) /* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -40,17 +37,6 @@ /* NAND support */ #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR - -/* Dynamic MTD partition support */ - -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET1_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 @@ -62,13 +48,15 @@ /* We boot from the gfxRAM area of the OCRAM. */ #define CONFIG_BOARD_SIZE_LIMIT 520192 -#define SD_BOOTCMD \ - "sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \ - "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \ - "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ - "load mmc 0:2 ${kernel_addr_r} /boot/${kernel_file} && " \ - "load mmc 0:2 ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "fdt_addr_r=0x82000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x87000000\0" #define NFS_BOOTCMD \ "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ @@ -79,7 +67,15 @@ "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ -#define UBI_BOOTCMD \ +#define SD_BOOTCMD \ + "sdargs=root=/dev/mmcblk0p2 ro rootwait\0" \ + "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \ + "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ + "load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \ + "load mmc 0:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define UBI_BOOTCMD \ "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ "ubi.fm_autoconvert=1\0" \ "ubiboot=run setup; " \ @@ -90,36 +86,43 @@ "ubi read ${fdt_addr_r} dtb && " \ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ -#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot" +#define CONFIG_BOOTCOMMAND "run ubiboot; " \ + "setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd;" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include <config_distro_bootcmd.h> +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" #define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4" #define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x82000000\0" \ - "fdt_addr_r=0x84000000\0" \ - "kernel_file=zImage\0" \ - "fdt_file=${soc}-colibri-${fdt_board}.dtb\0" \ + BOOTENV \ + MEM_LAYOUT_ENV_SETTINGS \ + NFS_BOOTCMD \ + SD_BOOTCMD \ + UBI_BOOTCMD \ + "console=ttyLP0\0" \ + "defargs=user_debug=30\0" \ + "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ "fdt_board=eval-v3\0" \ "fdt_fixup=;\0" \ - "defargs=\0" \ - "console=ttyLP0\0" \ - "setup=setenv setupargs " \ - "console=tty1 console=${console}" \ - ",${baudrate}n8 ${memargs}\0" \ + "kernel_file=zImage\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "setsdupdate=mmc rescan && set interface mmc && " \ - "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ - "setusbupdate=usb start && set interface usb && " \ - "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ + "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ + "setup=setenv setupargs console=tty1 console=${console}" \ + ",${baudrate}n8 ${memargs}\0" \ "setupdate=run setsdupdate || run setusbupdate\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ - "video-mode=dcufb:640x480-16@60,monitor=lcd\0" \ + "setusbupdate=usb start && set interface usb && " \ + "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ + "source ${loadaddr}\0" \ "splashpos=m,m\0" \ - SD_BOOTCMD \ - NFS_BOOTCMD \ - UBI_BOOTCMD + "video-mode=dcufb:640x480-16@60,monitor=lcd\0" /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -133,7 +136,7 @@ /* Physical memory map */ #define PHYS_SDRAM (0x80000000) -#define PHYS_SDRAM_SIZE (256 * 1024 * 1024) +#define PHYS_SDRAM_SIZE (256 * SZ_1M) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR @@ -145,13 +148,6 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Environment organization */ - -#ifdef CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_OFFSET (12 * 64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) -#endif - #ifdef CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE (64 * 2048) #define CONFIG_ENV_RANGE (4 * 64 * 2048) @@ -159,13 +155,10 @@ #endif /* USB Host Support */ -#define CONFIG_USB_EHCI_VF #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* USB DFU */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024 * 1024) - -/* USB Storage */ +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) #endif /* __CONFIG_H */ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 48514ff076b..3eee382a643 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -48,11 +48,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_ARP_TIMEOUT 200UL -/* Fuses */ -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif - /* I2C Configs */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 5142680e7d6..858bed012c6 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -86,7 +86,6 @@ #endif /* Framebuffer */ -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 33365780717..196f114c60e 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -35,8 +35,6 @@ #define CONFIG_MXC_UART -#define CONFIG_MXC_OCOTP - /* SATA Configs */ #ifdef CONFIG_CMD_SATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 @@ -45,10 +43,6 @@ #define CONFIG_LBA48 #endif -/* MMC Configs */ -#define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - /* USB Configs */ #ifdef CONFIG_USB #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 @@ -77,12 +71,37 @@ #define CONFIG_LOADADDR 0x12000000 +#ifdef CONFIG_NFS_CMD +#define NETWORKBOOT \ + "setnetworkboot=" \ + "setenv ipaddr 172.16.2.10; setenv serverip 172.16.2.20; " \ + "setenv gatewayip 172.16.2.20; setenv nfsserver 172.16.2.20; " \ + "setenv netmask 255.255.255.0; setenv ethaddr ca:fe:de:ca:f0:11; " \ + "setenv bootargs root=/dev/nfs nfsroot=${nfsserver}:/srv/nfs/,v3,tcp rw rootwait" \ + "setenv bootargs $bootargs ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off " \ + "setenv bootargs $bootargs cma=128M bootcause=POR console=${console} ${videoargs} " \ + "setenv bootargs $bootargs systemd.mask=helix-network-defaults.service " \ + "setenv bootargs $bootargs watchdog.handle_boot_enabled=1\0" \ + "networkboot=" \ + "run setnetworkboot; " \ + "nfs ${loadaddr} /srv/nfs/fitImage; " \ + "bootm ${loadaddr}#conf@${confidx}\0" \ + +#define CONFIG_NETWORKBOOTCOMMAND \ + "run networkboot; " \ + +#else +#define NETWORKBOOT \ + +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ + NETWORKBOOT \ "bootcause=POR\0" \ "image=/boot/fitImage\0" \ "fdt_high=0xffffffff\0" \ "dev=mmc\0" \ - "devnum=1\0" \ + "devnum=2\0" \ "rootdev=mmcblk0p\0" \ "quiet=quiet loglevel=0\0" \ "console=" CONSOLE_DEV "\0" \ @@ -140,13 +159,14 @@ #define CONFIG_USBBOOTCOMMAND \ "echo Unsupported; " \ -#ifdef CONFIG_CMD_USB +#ifdef CONFIG_NFS_CMD +#define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND +#elif CONFIG_CMD_USB #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND #else #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND #endif -#define CONFIG_ARP_TIMEOUT 200UL /* Miscellaneous configurable options */ @@ -176,18 +196,10 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 /* Framebuffer */ -#define CONFIG_VIDEO -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_FG_COL 0xFF -#define CONFIG_SYS_CONSOLE_BG_COL 0x00 #define CONFIG_HIDE_LOGO_VERSION #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP #define CONFIG_CMD_BMP -#endif #define CONFIG_PWM_IMX #define CONFIG_IMX6_PWM_PER_CLK 66000000 diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 84ee44e8720..93608e5aec4 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -132,7 +132,6 @@ #define CONFIG_NETCONSOLE /* Framebuffer and LCD */ -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_LOGO #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index a9e38a70e60..6094d1bf180 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -230,7 +230,6 @@ #define CONFIG_MXC_GPIO -#define CONFIG_MXC_OCOTP #define CONFIG_CMD_FUSE /* I2C Configs */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index b6b27ee1d5e..d2ebf929536 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -31,11 +31,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_ARP_TIMEOUT 200UL -/* Fuses */ -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif - /* I2C Configs */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 51456fbe556..84d061339ec 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -138,7 +138,6 @@ * LCD */ #ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SPLASH_SCREEN diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index eb172c97b35..9bf9773c69d 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -68,7 +68,6 @@ /* Framebuffer and LCD */ #define CONFIG_PREBOOT -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_BMP_16BPP diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 3ed5ee3c57e..1e3ea88b77a 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -161,7 +161,6 @@ /* Framebuffer and LCD */ #define CONFIG_PREBOOT -#define CONFIG_VIDEO_IPUV3 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 816164e87ee..2d18f05423b 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -178,7 +178,6 @@ /* Framebuffer and LCD */ #define CONFIG_PREBOOT -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_BMP_16BPP diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index d2a8e6571af..f002324fddc 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -30,10 +30,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2 - /* Eth Configs */ #define CONFIG_FEC_MXC @@ -89,10 +85,10 @@ "nfsroot=/opt/springdale/rd\0" \ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ "${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \ - "choose_ip=if test $use_dhcp = 1; then set kern_ipconf ip=dhcp; " \ - "set getcmd dhcp; else set kern_ipconf " \ + "choose_ip=if test $use_dhcp = 1; then setenv kern_ipconf ip=dhcp; " \ + "setenv getcmd dhcp; else setenv kern_ipconf " \ "ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; " \ - "set getcmd tftp; fi\0" \ + "setenv getcmd tftp; fi\0" \ "nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \ "${nfsserver}:${image}; bootm ${loadaddr}\0" \ @@ -101,7 +97,7 @@ "image=/boot/fitImage\0" \ "fdt_high=0xffffffff\0" \ "dev=mmc\0" \ - "devnum=0\0" \ + "devnum=2\0" \ "rootdev=mmcblk0p\0" \ "quiet=quiet loglevel=0\0" \ "console=" CONSOLE_DEV "\0" \ @@ -219,9 +215,4 @@ #define CONFIG_PWM_IMX #define CONFIG_IMX6_PWM_PER_CLK 66666000 -/* Framebuffer and LCD */ -#ifdef CONFIG_VIDEO - #define CONFIG_VIDEO_IPUV3 -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index cdc88337780..6b20c6db580 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -57,9 +57,6 @@ /* MMC */ #define CONFIG_FSL_USDHC -/* Fuses */ -#define CONFIG_MXC_OCOTP - /* Secure boot (HAB) support */ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CSF_SIZE 0x2000 diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index a62e14f7c61..7b4ae2102eb 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -35,7 +35,6 @@ #define CONFIG_PHY_ATHEROS /* Framebuffer */ -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 6fe0467229f..c137612b01c 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -185,7 +185,6 @@ #endif /* Framebuffer */ -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index a895c936aa2..cc7e87269ee 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -42,9 +42,6 @@ /* MMC */ #define CONFIG_FSL_USDHC -/* Fuses */ -#define CONFIG_MXC_OCOTP - #define CONFIG_ARMV7_SECURE_BASE 0x00900000 #define CONFIG_ARMV7_PSCI_1_0 diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index d941caa905e..afaa9084062 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -58,7 +58,6 @@ #define CONFIG_MXC_USB_FLAGS 0 /* Framebuffer and LCD */ -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN diff --git a/include/configs/novena.h b/include/configs/novena.h index 25736f3c03e..bb5bf808c2b 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -125,7 +125,6 @@ /* Video output */ #ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_BMP_16BPP diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index e125a38e7d4..fb8f3c8609c 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -9,6 +9,7 @@ #define __CONFIG_H #include <asm/arch/imx-regs.h> +#include <linux/sizes.h> #define CONFIG_SKIP_LOWLEVEL_INIT @@ -16,7 +17,7 @@ #define CONFIG_CMDLINE_TAG /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) /* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -24,48 +25,14 @@ /* NAND support */ #define CONFIG_SYS_NAND_ONFI_DETECTION -#ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR - -#define CONFIG_JFFS2_NAND - -/* Dynamic MTD partition support */ - -#endif - -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/ - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 - /* QSPI Configs*/ - #ifdef CONFIG_FSL_QSPI -#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_SIZE (SZ_16M) #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_SYS_FSL_QSPI_LE #endif -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC_I2C3 -#define CONFIG_SYS_I2C_MXC - -/* RTC (actually an RV-4162 but M41T62-compatible) */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_RTC_BUS_NUM 2 - -/* EEPROM (24FC256) */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_BUS 2 - #define CONFIG_LOADADDR 0x82000000 @@ -188,7 +155,7 @@ /* Physical memory map */ #define PHYS_SDRAM (0x80000000) -#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * 1024 * 1024) +#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR @@ -201,17 +168,17 @@ /* environment organization */ #ifdef CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_SIZE (SZ_8K) -#define CONFIG_ENV_OFFSET (12 * 64 * 1024) +#define CONFIG_ENV_OFFSET (12 * SZ_64K) #define CONFIG_SYS_MMC_ENV_DEV 0 #endif #ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_SECT_SIZE (SZ_128K) +#define CONFIG_ENV_SIZE (SZ_8K) #define CONFIG_ENV_OFFSET 0xA0000 -#define CONFIG_ENV_SIZE_REDUND (8 * 1024) +#define CONFIG_ENV_SIZE_REDUND (SZ_8K) #define CONFIG_ENV_OFFSET_REDUND 0xC0000 #endif diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index b06c90939cc..a753d418354 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -40,13 +40,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ -/* Filesystems / image support */ - -/* MMC */ -#define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT - /* Ethernet */ #define CONFIG_FEC_MXC #define CONFIG_FEC_MXC @@ -58,7 +51,6 @@ /* Framebuffer */ #ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP @@ -77,11 +69,11 @@ #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 +#define CONFIG_SYS_64BIT_LBA #endif /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #ifdef CONFIG_CMD_USB_MASS_STORAGE @@ -98,23 +90,6 @@ #endif /* CONFIG_USB_KEYBOARD */ #endif /* CONFIG_CMD_USB */ -/* RTC */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1307 -#define CONFIG_SYS_RTC_BUS_NUM 2 -#endif - -/* I2C */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_I2C_EDID -#endif - /* Environment organization */ #define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */ #define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 686a3837393..ba85bc91e74 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -19,10 +19,6 @@ /* Enable passing of ATAGs */ #define CONFIG_CMDLINE_TAG -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXC_OCOTP -#endif - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index b03a1c550cd..2e6262f0f4c 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -32,26 +32,11 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - /* MMC Configuration */ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 @@ -64,8 +49,6 @@ #define CONFIG_PHY_ATHEROS /* Framebuffer */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN @@ -74,7 +57,6 @@ #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP -#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index fa98efc24c0..31c1ba3477c 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4514,7 +4514,6 @@ CONFIG_USB_EHCI_MXS CONFIG_USB_EHCI_SPEAR CONFIG_USB_EHCI_TXFIFO_THRESH CONFIG_USB_EHCI_VCT -CONFIG_USB_EHCI_VF CONFIG_USB_ETH_QMULT CONFIG_USB_ETH_SUBSET CONFIG_USB_EXT2_BOOT |