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-rw-r--r--arch/arm/include/asm/arch-imx8/crm_regs.h10
-rw-r--r--arch/arm/include/asm/arch-imx8/imx-regs.h3
-rw-r--r--arch/arm/mach-imx/imx8/cpu.c8
-rw-r--r--drivers/crypto/fsl_caam.c55
-rw-r--r--drivers/crypto/fsl_caam_internal.h17
-rw-r--r--include/configs/imx8qm_mek_android_auto.h3
-rw-r--r--include/configs/imx8qxp_mek_android_auto.h3
7 files changed, 94 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-imx8/crm_regs.h b/arch/arm/include/asm/arch-imx8/crm_regs.h
new file mode 100644
index 0000000000..20c867bb59
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/crm_regs.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_MX8_CRM_REGS_H
+#define _ASM_ARCH_MX8_CRM_REGS_H
+/* Dummy header, some imx-common code needs this file */
+#endif
diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h
index 3bc6714648..e3d3e2b504 100644
--- a/arch/arm/include/asm/arch-imx8/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
@@ -58,7 +58,8 @@
#define USB_BASE_ADDR 0x5b0d0000
#define USB_PHY0_BASE_ADDR 0x5b100000
-#define CAAM_ARB_BASE_ADDR (0x31800000)
+#define CAAM_ARB_BASE_ADDR (0x31800000)
+#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 9887933ac8..c511e909fd 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -203,6 +203,14 @@ int arch_cpu_init(void)
return 0;
#endif
+/* Dual bootloader feature will require CAAM access, but JR0 and JR1 will be
+ * assigned to seco for imx8, use JR3 instead.
+ */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_DUAL_BOOTLOADER)
+ sc_pm_set_resource_power_mode(ipcHndl, SC_R_CAAM_JR3, SC_PM_PW_MODE_ON);
+ sc_pm_set_resource_power_mode(ipcHndl, SC_R_CAAM_JR3_OUT, SC_PM_PW_MODE_ON);
+#endif
+
return 0;
}
diff --git a/drivers/crypto/fsl_caam.c b/drivers/crypto/fsl_caam.c
index 144d7c2cb5..449b187db3 100644
--- a/drivers/crypto/fsl_caam.c
+++ b/drivers/crypto/fsl_caam.c
@@ -246,13 +246,16 @@ u32 caam_hwrng(u8 *output_ptr, u32 output_len)
*/
void caam_open(void)
{
- u32 temp_reg;
int ret;
/* switch on the clock */
+ /* for imx8, the CAAM initialization should have been done
+ * in seco, so we should skip this part.
+ */
#ifndef CONFIG_ARCH_IMX8
+ u32 temp_reg;
+
caam_clock_enable();
-#endif
/* reset the CAAM */
temp_reg = __raw_readl(CAAM_MCFGR) |
@@ -262,6 +265,7 @@ void caam_open(void)
;
jr_reset();
+
ret = do_cfg_jrqueue();
if (ret != SUCCESS) {
@@ -275,8 +279,15 @@ void caam_open(void)
printf("RNG already instantiated 0x%X\n", temp_reg);
return;
}
-
rng_init();
+#else
+ ret = do_cfg_jrqueue();
+
+ if (ret != SUCCESS) {
+ printf("Error CAAM JR initialization\n");
+ return;
+ }
+#endif
#ifdef CONFIG_CAAM_KB_SELF_TEST
caam_test();
@@ -543,7 +554,14 @@ static int do_job(u32 *desc)
int ret;
phys_addr_t p_desc = virt_to_phys(desc);
+ /* for imx8, JR0 and JR1 will be assigned to seco, so we use
+ * the JR3 instead.
+ */
+#ifndef CONFIG_ARCH_IMX8
if (__raw_readl(CAAM_IRSAR0) == 0)
+#else
+ if (__raw_readl(CAAM_IRSAR3) == 0)
+#endif
return ERROR_ANY;
g_jrdata.inrings[0].desc = p_desc;
@@ -559,9 +577,15 @@ static int do_job(u32 *desc)
+ ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN));
/* Inform HW that a new JR is available */
+#ifndef CONFIG_ARCH_IMX8
__raw_writel(1, CAAM_IRJAR0);
while (__raw_readl(CAAM_ORSFR0) == 0)
;
+#else
+ __raw_writel(1, CAAM_IRJAR3);
+ while (__raw_readl(CAAM_ORSFR3) == 0)
+ ;
+#endif
if (PTR2CAAMDMA(desc) == g_jrdata.outrings[0].desc) {
ret = g_jrdata.outrings[0].status;
@@ -571,10 +595,15 @@ static int do_job(u32 *desc)
}
/* Acknowledge interrupt */
+#ifndef CONFIG_ARCH_IMX8
setbits_le32(CAAM_JRINTR0, JRINTR_JRI);
-
/* Remove the JR from the output list even if no JR caller found */
__raw_writel(1, CAAM_ORJRR0);
+#else
+ setbits_le32(CAAM_JRINTR3, JRINTR_JRI);
+ /* Remove the JR from the output list even if no JR caller found */
+ __raw_writel(1, CAAM_ORJRR3);
+#endif
return ret;
}
@@ -632,6 +661,11 @@ static int do_cfg_jrqueue(void)
/* Configure the HW Job Rings */
ip_base = virt_to_phys((void *)g_jrdata.inrings);
op_base = virt_to_phys((void *)g_jrdata.outrings);
+
+ /* for imx8, JR0 and JR1 will be assigned to seco, so we use
+ * the JR3 instead.
+ */
+#ifndef CONFIG_ARCH_IMX8
__raw_writel(ip_base, CAAM_IRBAR0);
__raw_writel(1, CAAM_IRSR0);
@@ -639,6 +673,15 @@ static int do_cfg_jrqueue(void)
__raw_writel(1, CAAM_ORSR0);
setbits_le32(CAAM_JRINTR0, JRINTR_JRI);
+#else
+ __raw_writel(ip_base, CAAM_IRBAR3);
+ __raw_writel(1, CAAM_IRSR3);
+
+ __raw_writel(op_base, CAAM_ORBAR3);
+ __raw_writel(1, CAAM_ORSR3);
+
+ setbits_le32(CAAM_JRINTR3, JRINTR_JRI);
+#endif
/*
* Configure interrupts but disable it:
@@ -650,10 +693,14 @@ static int do_cfg_jrqueue(void)
value |= (1 << BS_JRCFGR_LS_ICDCT) & BM_JRCFGR_LS_ICDCT;
value |= BM_JRCFGR_LS_ICEN;
value |= BM_JRCFGR_LS_IMSK;
+#ifndef CONFIG_ARCH_IMX8
__raw_writel(value, CAAM_JRCFGR0_LS);
/* Enable deco watchdog */
setbits_le32(CAAM_MCFGR, BM_MCFGR_WDE);
+#else
+ __raw_writel(value, CAAM_JRCFGR3_LS);
+#endif
return 0;
}
diff --git a/drivers/crypto/fsl_caam_internal.h b/drivers/crypto/fsl_caam_internal.h
index a58e215d85..e922d505c8 100644
--- a/drivers/crypto/fsl_caam_internal.h
+++ b/drivers/crypto/fsl_caam_internal.h
@@ -105,6 +105,23 @@
#define CAAM_SMAG1JR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x111c)
#define CAAM_SMPO (CONFIG_SYS_FSL_SEC_ADDR + 0x1fbc)
+/* JR0 and JR1 will be assigned to seco in imx8, so we need to
+ * use JR3 instead.
+ */
+#ifdef CONFIG_ARCH_IMX8
+#define CAAM_IRBAR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x40004)
+#define CAAM_IRSR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x4000c)
+#define CAAM_IRSAR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x40014)
+#define CAAM_IRJAR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x4001c)
+#define CAAM_ORBAR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x40024)
+#define CAAM_ORSR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x4002c)
+#define CAAM_ORSFR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x4003c)
+#define CAAM_JRINTR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x4004c)
+#define CAAM_ORJRR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x40034)
+#define CAAM_JRCFGR3_LS (CONFIG_SYS_FSL_SEC_ADDR + 0x40054)
+#define CAAM_JRCR3 (CONFIG_SYS_FSL_SEC_ADDR + 0x4006c)
+#endif
+
#define DESC_MAX_SIZE (0x40) /* Descriptor max size */
#define JRCFG_LS_IMSK (0x01) /* Interrupt Mask */
#define JR_MID (0x02) /* Matches ROM configuration */
diff --git a/include/configs/imx8qm_mek_android_auto.h b/include/configs/imx8qm_mek_android_auto.h
index 09463934a4..968e7e71bb 100644
--- a/include/configs/imx8qm_mek_android_auto.h
+++ b/include/configs/imx8qm_mek_android_auto.h
@@ -110,6 +110,9 @@
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_BLK
+#define CONFIG_FSL_CAAM_KB
+#define CONFIG_SPL_CRYPTO_SUPPORT
+#define CONFIG_SYS_FSL_SEC_LE
#endif
#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED
diff --git a/include/configs/imx8qxp_mek_android_auto.h b/include/configs/imx8qxp_mek_android_auto.h
index a74b0bf43c..5c5216fd88 100644
--- a/include/configs/imx8qxp_mek_android_auto.h
+++ b/include/configs/imx8qxp_mek_android_auto.h
@@ -102,6 +102,9 @@
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_BLK
+#define CONFIG_FSL_CAAM_KB
+#define CONFIG_SPL_CRYPTO_SUPPORT
+#define CONFIG_SYS_FSL_SEC_LE
#endif
#define AVB_AB_I_UNDERSTAND_LIBAVB_AB_IS_DEPRECATED
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-28 00:29:12 +0000