diff options
| -rw-r--r-- | arch/arm/dts/ast2500-u-boot.dtsi | 53 | ||||
| -rw-r--r-- | arch/arm/dts/ast2500.dtsi | 174 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 125 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-aspeed/sdram_ast2500.h | 138 | ||||
| -rw-r--r-- | arch/arm/mach-aspeed/Kconfig | 2 | ||||
| -rw-r--r-- | arch/arm/mach-aspeed/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/mach-aspeed/ast2500/Kconfig | 14 | ||||
| -rw-r--r-- | arch/arm/mach-aspeed/ast2500/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/mach-aspeed/ast2500/clk_ast2500.c | 30 | ||||
| -rw-r--r-- | arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 432 | ||||
| -rw-r--r-- | drivers/clk/Makefile | 2 | ||||
| -rw-r--r-- | drivers/clk/aspeed/Makefile | 7 | ||||
| -rw-r--r-- | drivers/clk/aspeed/clk_ast2500.c | 265 | ||||
| -rw-r--r-- | include/dt-bindings/clock/ast2500-scu.h | 29 |
14 files changed, 1273 insertions, 0 deletions
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi new file mode 100644 index 0000000000..c95a7ba835 --- /dev/null +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -0,0 +1,53 @@ +#include <dt-bindings/clock/ast2500-scu.h> + +#include "ast2500.dtsi" + +/ { + scu: clock-controller@1e6e2000 { + compatible = "aspeed,ast2500-scu"; + reg = <0x1e6e2000 0x1000>; + u-boot,dm-pre-reloc; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + sdrammc: sdrammc@1e6e0000 { + u-boot,dm-pre-reloc; + compatible = "aspeed,ast2500-sdrammc"; + reg = <0x1e6e0000 0x174 + 0x1e6e0200 0x1d4 >; + clocks = <&scu PLL_MPLL>; + }; + + ahb { + u-boot,dm-pre-reloc; + + apb { + u-boot,dm-pre-reloc; + + timer: timer@1e782000 { + u-boot,dm-pre-reloc; + }; + + uart1: serial@1e783000 { + clocks = <&scu PCLK_UART1>; + }; + + uart2: serial@1e78d000 { + clocks = <&scu PCLK_UART2>; + }; + + uart3: serial@1e78e000 { + clocks = <&scu PCLK_UART3>; + }; + + uart4: serial@1e78f000 { + clocks = <&scu PCLK_UART4>; + }; + + uart5: serial@1e784000 { + clocks = <&scu PCLK_UART5>; + }; + }; + }; +}; diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi new file mode 100644 index 0000000000..97fac69d11 --- /dev/null +++ b/arch/arm/dts/ast2500.dtsi @@ -0,0 +1,174 @@ +/* + * This device tree is copied from + * https://raw.githubusercontent.com/torvalds/linux/02440622/arch/arm/boot/dts/ + */ +#include "skeleton.dtsi" + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2500"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm1176jzf-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vic: interrupt-controller@1e6c0080 { + compatible = "aspeed,ast2400-vic"; + interrupt-controller; + #interrupt-cells = <1>; + valid-sources = <0xfefff7ff 0x0807ffff>; + reg = <0x1e6c0080 0x80>; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clk_clkin: clk_clkin@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-clkin-clock"; + reg = <0x1e6e2070 0x04>; + }; + + clk_hpll: clk_hpll@1e6e2024 { + #clock-cells = <0>; + compatible = "aspeed,g5-hpll-clock"; + reg = <0x1e6e2024 0x4>; + clocks = <&clk_clkin>; + }; + + clk_ahb: clk_ahb@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-ahb-clock"; + reg = <0x1e6e2070 0x4>; + clocks = <&clk_hpll>; + }; + + clk_apb: clk_apb@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,g5-apb-clock"; + reg = <0x1e6e2008 0x4>; + clocks = <&clk_hpll>; + }; + + clk_uart: clk_uart@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,uart-clock"; + reg = <0x1e6e202c 0x4>; + }; + + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x9000>; // 36K + }; + + timer: timer@1e782000 { + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + // The moxart_timer driver registers only one + // interrupt and assumes it's for timer 1 + //interrupts = <16 17 18 35 36 37 38 39>; + interrupts = <16>; + clocks = <&clk_apb>; + }; + + wdt1: wdt@1e785000 { + compatible = "aspeed,wdt"; + reg = <0x1e785000 0x1c>; + interrupts = <27>; + }; + + wdt2: wdt@1e785020 { + compatible = "aspeed,wdt"; + reg = <0x1e785020 0x1c>; + interrupts = <27>; + status = "disabled"; + }; + + wdt3: wdt@1e785040 { + compatible = "aspeed,wdt"; + reg = <0x1e785074 0x1c>; + status = "disabled"; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x1000>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x1000>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x1000>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x1000>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + current-speed = <38400>; + no-loopback-test; + status = "disabled"; + }; + + uart6: serial@1e787000 { + compatible = "ns16550a"; + reg = <0x1e787000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h new file mode 100644 index 0000000000..fc0c01ae33 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_SCU_AST2500_H +#define _ASM_ARCH_SCU_AST2500_H + +#define SCU_UNLOCK_VALUE 0x1688a8a8 + +#define SCU_HWSTRAP_VGAMEM_MASK 3 +#define SCU_HWSTRAP_VGAMEM_SHIFT 2 +#define SCU_HWSTRAP_DDR4 (1 << 24) +#define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23) + +#define SCU_MPLL_DENUM_SHIFT 0 +#define SCU_MPLL_DENUM_MASK 0x1f +#define SCU_MPLL_NUM_SHIFT 5 +#define SCU_MPLL_NUM_MASK 0xff +#define SCU_MPLL_POST_SHIFT 13 +#define SCU_MPLL_POST_MASK 0x3f + +#define SCU_HPLL_DENUM_SHIFT 0 +#define SCU_HPLL_DENUM_MASK 0x1f +#define SCU_HPLL_NUM_SHIFT 5 +#define SCU_HPLL_NUM_MASK 0xff +#define SCU_HPLL_POST_SHIFT 13 +#define SCU_HPLL_POST_MASK 0x3f + +#define SCU_MISC2_UARTCLK_SHIFT 24 + +#define SCU_MISC_UARTCLK_DIV13 (1 << 12) + +#ifndef __ASSEMBLY__ + +struct ast2500_clk_priv { + struct ast2500_scu *scu; +}; + +struct ast2500_scu { + u32 protection_key; + u32 sysreset_ctrl1; + u32 clk_sel1; + u32 clk_stop_ctrl1; + u32 freq_counter_ctrl; + u32 freq_counter_cmp; + u32 intr_ctrl; + u32 d2_pll_param; + u32 m_pll_param; + u32 h_pll_param; + u32 d_pll_param; + u32 misc_ctrl1; + u32 pci_config[3]; + u32 sysreset_status; + u32 vga_handshake[2]; + u32 mac_clk_delay; + u32 misc_ctrl2; + u32 vga_scratch[8]; + u32 hwstrap; + u32 rng_ctrl; + u32 rng_data; + u32 rev_id; + u32 pinmux_ctrl[6]; + u32 reserved0; + u32 extrst_sel; + u32 pinmux_ctrl1[4]; + u32 reserved1[2]; + u32 mac_clk_delay_100M; + u32 mac_clk_delay_10M; + u32 wakeup_enable; + u32 wakeup_control; + u32 reserved2[3]; + u32 sysreset_ctrl2; + u32 clk_sel2; + u32 clk_stop_ctrl2; + u32 freerun_counter; + u32 freerun_counter_ext; + u32 clk_duty_meas_ctrl; + u32 clk_duty_meas_res; + u32 reserved3[4]; + /* The next registers are not key-protected */ + struct ast2500_cpu2 { + u32 ctrl; + u32 base_addr[9]; + u32 cache_ctrl; + } cpu2; + u32 reserved4; + u32 d_pll_ext_param[3]; + u32 d2_pll_ext_param[3]; + u32 mh_pll_ext_param; + u32 reserved5; + u32 chip_id[2]; + u32 reserved6[2]; + u32 uart_clk_ctrl; + u32 reserved7[7]; + u32 pcie_config; + u32 mmio_decode; + u32 reloc_ctrl_decode[2]; + u32 mailbox_addr; + u32 shared_sram_decode[2]; + u32 bmc_rev_id; + u32 reserved8; + u32 bmc_device_id; + u32 reserved9[13]; + u32 clk_duty_sel; +}; + +/** + * ast_get_clk() - get a pointer to Clock Driver + * + * @devp, OUT - pointer to Clock Driver + * @return zero on success, error code (< 0) otherwise. + */ +int ast_get_clk(struct udevice **devp); + +/** + * ast_get_scu() - get a pointer to SCU registers + * + * @return pointer to struct ast2500_scu on success, ERR_PTR otherwise + */ +void *ast_get_scu(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_ARCH_SCU_AST2500_H */ diff --git a/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h b/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h new file mode 100644 index 0000000000..a5f8615ae2 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_SDRAM_AST2500_H +#define _ASM_ARCH_SDRAM_AST2500_H + +#define SDRAM_UNLOCK_KEY 0xfc600309 +#define SDRAM_VIDEO_UNLOCK_KEY 0x2003000f + +#define SDRAM_PCR_CKE_EN (1 << 0) +#define SDRAM_PCR_AUTOPWRDN_EN (1 << 1) +#define SDRAM_PCR_CKE_DELAY_SHIFT 4 +#define SDRAM_PCR_CKE_DELAY_MASK 7 +#define SDRAM_PCR_RESETN_DIS (1 << 7) +#define SDRAM_PCR_ODT_EN (1 << 8) +#define SDRAM_PCR_ODT_AUTO_ON (1 << 10) +#define SDRAM_PCR_ODT_EXT_EN (1 << 11) +#define SDRAM_PCR_TCKE_PW_SHIFT 12 +#define SDRAM_PCR_TCKE_PW_MASK 7 +#define SDRAM_PCR_RGAP_CTRL_EN (1 << 15) +#define SDRAM_PCR_MREQI_DIS (1 << 17) + +/* Fixed priority DRAM Requests mask */ +#define SDRAM_REQ_VGA_HW_CURSOR (1 << 0) +#define SDRAM_REQ_VGA_TEXT_CG_FONT (1 << 1) +#define SDRAM_REQ_VGA_TEXT_ASCII (1 << 2) +#define SDRAM_REQ_VGA_CRT (1 << 3) +#define SDRAM_REQ_SOC_DC_CURSOR (1 << 4) +#define SDRAM_REQ_SOC_DC_OCD (1 << 5) +#define SDRAM_REQ_SOC_DC_CRT (1 << 6) +#define SDRAM_REQ_VIDEO_HIPRI_WRITE (1 << 7) +#define SDRAM_REQ_USB20_EHCI1 (1 << 8) +#define SDRAM_REQ_USB20_EHCI2 (1 << 9) +#define SDRAM_REQ_CPU (1 << 10) +#define SDRAM_REQ_AHB2 (1 << 11) +#define SDRAM_REQ_AHB (1 << 12) +#define SDRAM_REQ_MAC0 (1 << 13) +#define SDRAM_REQ_MAC1 (1 << 14) +#define SDRAM_REQ_PCIE (1 << 16) +#define SDRAM_REQ_XDMA (1 << 17) +#define SDRAM_REQ_ENCRYPTION (1 << 18) +#define SDRAM_REQ_VIDEO_FLAG (1 << 21) +#define SDRAM_REQ_VIDEO_LOW_PRI_WRITE (1 << 28) +#define SDRAM_REQ_2D_RW (1 << 29) +#define SDRAM_REQ_MEMCHECK (1 << 30) + +#define SDRAM_ICR_RESET_ALL (1 << 31) + +#define SDRAM_CONF_CAP_SHIFT 0 +#define SDRAM_CONF_CAP_MASK 3 +#define SDRAM_CONF_DDR4 (1 << 4) +#define SDRAM_CONF_SCRAMBLE (1 << 8) +#define SDRAM_CONF_SCRAMBLE_PAT2 (1 << 9) +#define SDRAM_CONF_CACHE_EN (1 << 10) +#define SDRAM_CONF_CACHE_INIT_EN (1 << 12) +#define SDRAM_CONF_DUALX8 (1 << 13) +#define SDRAM_CONF_CACHE_INIT_DONE (1 << 19) + +#define SDRAM_CONF_CAP_128M 0 +#define SDRAM_CONF_CAP_256M 1 +#define SDRAM_CONF_CAP_512M 2 +#define SDRAM_CONF_CAP_1024M 3 + +#define SDRAM_MISC_DDR4_TREFRESH (1 << 3) + +#define SDRAM_PHYCTRL0_INIT (1 << 0) +#define SDRAM_PHYCTRL0_AUTO_UPDATE (1 << 1) +#define SDRAM_PHYCTRL0_NRST (1 << 2) + +#define SDRAM_REFRESH_CYCLES_SHIFT 0 +#define SDRAM_REFRESH_CYCLES_MASK 0xf +#define SDRAM_REFRESH_ZQCS_EN (1 << 7) +#define SDRAM_REFRESH_PERIOD_SHIFT 8 +#define SDRAM_REFRESH_PERIOD_MASK 0xf + +#define SDRAM_TEST_LEN_SHIFT 4 +#define SDRAM_TEST_LEN_MASK 0xfffff +#define SDRAM_TEST_START_ADDR_SHIFT 24 +#define SDRAM_TEST_START_ADDR_MASK 0x3f + +#define SDRAM_TEST_EN (1 << 0) +#define SDRAM_TEST_MODE_SHIFT 1 +#define SDRAM_TEST_MODE_MASK 3 +#define SDRAM_TEST_MODE_WO 0 +#define SDRAM_TEST_MODE_RB 1 +#define SDRAM_TEST_MODE_RW 2 +#define SDRAM_TEST_GEN_MODE_SHIFT 3 +#define SDRAM_TEST_GEN_MODE_MASK 7 +#define SDRAM_TEST_TWO_MODES (1 << 6) +#define SDRAM_TEST_ERRSTOP (1 << 7) +#define SDRAM_TEST_DONE (1 << 12) +#define SDRAM_TEST_FAIL (1 << 13) + +#define SDRAM_AC_TRFC_SHIFT 0 +#define SDRAM_AC_TRFC_MASK 0xff + +#ifndef __ASSEMBLY__ + +struct ast2500_sdrammc_regs { + u32 protection_key; + u32 config; + u32 gm_protection_key; + u32 refresh_timing; + u32 ac_timing[3]; + u32 misc_control; + u32 mr46_mode_setting; + u32 mr5_mode_setting; + u32 mode_setting_control; + u32 mr02_mode_setting; + u32 mr13_mode_setting; + u32 power_control; + u32 req_limit_mask; + u32 pri_group_setting; + u32 max_grant_len[4]; + u32 intr_ctrl; + u32 ecc_range_ctrl; + u32 first_ecc_err_addr; + u32 last_ecc_err_addr; + u32 phy_ctrl[4]; + u32 ecc_test_ctrl; + u32 test_addr; + u32 test_fail_dq_bit; + u32 test_init_val; + u32 phy_debug_ctrl; + u32 phy_debug_data; + u32 reserved1[30]; + u32 scu_passwd; + u32 reserved2[7]; + u32 scu_mpll; + u32 reserved3[19]; + u32 scu_hwstrap; +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_ARCH_SDRAM_AST2500_H */ diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index b72ed89af7..c5b90bd96a 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -24,4 +24,6 @@ config WDT_NUM The number of Watchdot Timers on a SoC. AST2500 has three WDTsk earlier versions have two or fewer. +source "arch/arm/mach-aspeed/ast2500/Kconfig" + endif diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile index a14b8f751d..1f7af71b03 100644 --- a/arch/arm/mach-aspeed/Makefile +++ b/arch/arm/mach-aspeed/Makefile @@ -5,3 +5,4 @@ # obj-$(CONFIG_ARCH_ASPEED) += ast_wdt.o +obj-$(CONFIG_ASPEED_AST2500) += ast2500/ diff --git a/arch/arm/mach-aspeed/ast2500/Kconfig b/arch/arm/mach-aspeed/ast2500/Kconfig new file mode 100644 index 0000000000..05cb27ea1f --- /dev/null +++ b/arch/arm/mach-aspeed/ast2500/Kconfig @@ -0,0 +1,14 @@ +if ASPEED_AST2500 + +config SYS_CPU + default "arm1176" + +config TARGET_EVB_AST2500 + bool "Evb-AST2500" + help + Evb-AST2500 is Aspeed evaluation board for AST2500 chip. + It has 512M of RAM, 32M of SPI flash, two Ethernet ports, + 4 Serial ports, 4 USB ports, VGA port, PCIe, SD card slot, + 20 pin JTAG, pinouts for 14 I2Cs, 3 SPIs and eSPI, 8 PWMs. + +endif diff --git a/arch/arm/mach-aspeed/ast2500/Makefile b/arch/arm/mach-aspeed/ast2500/Makefile new file mode 100644 index 0000000000..a35b239ef3 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2500/Makefile @@ -0,0 +1 @@ +obj-y += clk_ast2500.o sdram_ast2500.o diff --git a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c new file mode 100644 index 0000000000..079909fa64 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/arch/scu_ast2500.h> + +int ast_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(aspeed_ast2500_scu), devp); +} + +void *ast_get_scu(void) +{ + struct ast2500_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = ast_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->scu; +} diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c new file mode 100644 index 0000000000..ace1028116 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c @@ -0,0 +1,432 @@ +/* + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * + * Copyright 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <errno.h> +#include <ram.h> +#include <regmap.h> +#include <asm/io.h> +#include <asm/arch/scu_ast2500.h> +#include <asm/arch/sdram_ast2500.h> +#include <asm/arch/wdt.h> +#include <linux/err.h> +#include <linux/kernel.h> +#include <dt-bindings/clock/ast2500-scu.h> + +/* These configuration parameters are taken from Aspeed SDK */ +#define DDR4_MR46_MODE 0x08000000 +#define DDR4_MR5_MODE 0x400 +#define DDR4_MR13_MODE 0x101 +#define DDR4_MR02_MODE 0x410 +#define DDR4_TRFC 0x45457188 + +#define PHY_CFG_SIZE 15 + +static const u32 ddr4_ac_timing[3] = {0x63604e37, 0xe97afa99, 0x00019000}; +static const struct { + u32 index[PHY_CFG_SIZE]; + u32 value[PHY_CFG_SIZE]; +} ddr4_phy_config = { + .index = {0, 1, 3, 4, 5, 56, 57, 58, 59, 60, 61, 62, 36, 49, 50}, + .value = { + 0x42492aae, 0x09002000, 0x55e00b0b, 0x20000000, 0x24, + 0x03002900, 0x0e0000a0, 0x000e001c, 0x35b8c106, 0x08080607, + 0x9b000900, 0x0e400a00, 0x00100008, 0x3c183c3c, 0x00631e0e, + }, +}; + +#define SDRAM_MAX_SIZE (1024 * 1024 * 1024) +#define SDRAM_MIN_SIZE (128 * 1024 * 1024) + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Bandwidth configuration parameters for different SDRAM requests. + * These are hardcoded settings taken from Aspeed SDK. + */ +static const u32 ddr_max_grant_params[4] = { + 0x88448844, 0x24422288, 0x22222222, 0x22222222 +}; + +/* + * These registers are not documented by Aspeed at all. + * All writes and reads are taken pretty much as is from SDK. + */ +struct ast2500_ddr_phy { + u32 phy[117]; +}; + +struct dram_info { + struct ram_info info; + struct clk ddr_clk; + struct ast2500_sdrammc_regs *regs; + struct ast2500_scu *scu; + struct ast2500_ddr_phy *phy; + ulong clock_rate; +}; + +static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy *phy) +{ + writel(0, &phy->phy[2]); + writel(0, &phy->phy[6]); + writel(0, &phy->phy[8]); + writel(0, &phy->phy[10]); + writel(0, &phy->phy[12]); + writel(0, &phy->phy[42]); + writel(0, &phy->phy[44]); + + writel(0x86000000, &phy->phy[16]); + writel(0x00008600, &phy->phy[17]); + writel(0x80000000, &phy->phy[18]); + writel(0x80808080, &phy->phy[19]); + + return 0; +} + +static void ast2500_ddr_phy_init_process(struct dram_info *info) +{ + struct ast2500_sdrammc_regs *regs = info->regs; + + writel(0, ®s->phy_ctrl[0]); + writel(0x4040, &info->phy->phy[51]); + + writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); + while ((readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT)) + ; + writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_AUTO_UPDATE, + ®s->phy_ctrl[0]); +} + +static void ast2500_sdrammc_set_vref(struct dram_info *info, u32 vref) +{ + writel(0, &info->regs->phy_ctrl[0]); + writel((vref << 8) | 0x6, &info->phy->phy[48]); + ast2500_ddr_phy_init_process(info); +} + +static int ast2500_ddr_cbr_test(struct dram_info *info) +{ + struct ast2500_sdrammc_regs *regs = info->regs; + int i; + const u32 test_params = SDRAM_TEST_EN + | SDRAM_TEST_ERRSTOP + | SDRAM_TEST_TWO_MODES; + int ret = 0; + + writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) | + (0x5c << SDRAM_REFRESH_PERIOD_SHIFT), ®s->refresh_timing); + writel((0xfff << SDRAM_TEST_LEN_SHIFT), ®s->test_addr); + writel(0xff00ff00, ®s->test_init_val); + writel(SDRAM_TEST_EN | (SDRAM_TEST_MODE_RW << SDRAM_TEST_MODE_SHIFT) | + SDRAM_TEST_ERRSTOP, ®s->ecc_test_ctrl); + + while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE)) + ; + + if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) { + ret = -EIO; + } else { + for (i = 0; i <= SDRAM_TEST_GEN_MODE_MASK; ++i) { + writel((i << SDRAM_TEST_GEN_MODE_SHIFT) | test_params, + ®s->ecc_test_ctrl); + while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE)) + ; + if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) { + ret = -EIO; + break; + } + } + } + + writel(0, ®s->refresh_timing); + writel(0, ®s->ecc_test_ctrl); + + return ret; +} + +static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info) +{ + int i; + int vref_min = 0xff; + int vref_max = 0; + int range_size = 0; + + for (i = 1; i < 0x40; ++i) { + int res; + + ast2500_sdrammc_set_vref(info, i); + res = ast2500_ddr_cbr_test(info); + if (res < 0) { + if (range_size > 0) + break; + } else { + ++range_size; + vref_min = min(vref_min, i); + vref_max = max(vref_max, i); + } + } + + /* Pick average setting */ + ast2500_sdrammc_set_vref(info, (vref_min + vref_max + 1) / 2); + + return 0; +} + +static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info) +{ + size_t vga_mem_size_base = 8 * 1024 * 1024; + u32 vga_hwconf = (readl(&info->scu->hwstrap) + >> SCU_HWSTRAP_VGAMEM_SHIFT) + & SCU_HWSTRAP_VGAMEM_MASK; + + return vga_mem_size_base << vga_hwconf; +} + +/* + * Find out RAM size and save it in dram_info + * + * The procedure is taken from Aspeed SDK + */ +static void ast2500_sdrammc_calc_size(struct dram_info *info) +{ + /* The controller supports 128/256/512/1024 MB ram */ + size_t ram_size = SDRAM_MIN_SIZE; + const int write_test_offset = 0x100000; + u32 test_pattern = 0xdeadbeef; + u32 cap_param = SDRAM_CONF_CAP_1024M; + u32 refresh_timing_param = DDR4_TRFC; + const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; + + for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; + ram_size >>= 1) { + writel(test_pattern, write_addr_base + (ram_size >> 1)); + test_pattern = (test_pattern >> 4) | (test_pattern << 28); + } + + /* One last write to overwrite all wrapped values */ + writel(test_pattern, write_addr_base); + + /* Reset the pattern and see which value was really written */ + test_pattern = 0xdeadbeef; + for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; + ram_size >>= 1) { + if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) + break; + + --cap_param; + refresh_timing_param >>= 8; + test_pattern = (test_pattern >> 4) | (test_pattern << 28); + } + + clrsetbits_le32(&info->regs->ac_timing[1], + (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), + ((refresh_timing_param & SDRAM_AC_TRFC_MASK) + << SDRAM_AC_TRFC_SHIFT)); + + info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info); + clrsetbits_le32(&info->regs->config, + (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT), + ((cap_param & SDRAM_CONF_CAP_MASK) + << SDRAM_CONF_CAP_SHIFT)); +} + +static int ast2500_sdrammc_init_ddr4(struct dram_info *info) +{ + int i; + const u32 power_control = SDRAM_PCR_CKE_EN + | (1 << SDRAM_PCR_CKE_DELAY_SHIFT) + | (2 << SDRAM_PCR_TCKE_PW_SHIFT) + | SDRAM_PCR_RESETN_DIS + | SDRAM_PCR_RGAP_CTRL_EN | SDRAM_PCR_ODT_EN | SDRAM_PCR_ODT_EXT_EN; + const u32 conf = (SDRAM_CONF_CAP_1024M << SDRAM_CONF_CAP_SHIFT) +#ifdef CONFIG_DUALX8_RAM + | SDRAM_CONF_DUALX8 +#endif + | SDRAM_CONF_SCRAMBLE | SDRAM_CONF_SCRAMBLE_PAT2 | SDRAM_CONF_DDR4; + int ret; + + writel(conf, &info->regs->config); + for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) + writel(ddr4_ac_timing[i], &info->regs->ac_timing[i]); + + writel(DDR4_MR46_MODE, &info->regs->mr46_mode_setting); + writel(DDR4_MR5_MODE, &info->regs->mr5_mode_setting); + writel(DDR4_MR02_MODE, &info->regs->mr02_mode_setting); + writel(DDR4_MR13_MODE, &info->regs->mr13_mode_setting); + + for (i = 0; i < PHY_CFG_SIZE; ++i) { + writel(ddr4_phy_config.value[i], + &info->phy->phy[ddr4_phy_config.index[i]]); + } + + writel(power_control, &info->regs->power_control); + + ast2500_ddr_phy_init_process(info); + + ret = ast2500_sdrammc_ddr4_calibrate_vref(info); + if (ret < 0) { + debug("Vref calibration failed!\n"); + return ret; + } + + writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) + | SDRAM_REFRESH_ZQCS_EN | (0x2f << SDRAM_REFRESH_PERIOD_SHIFT), + &info->regs->refresh_timing); + + setbits_le32(&info->regs->power_control, + SDRAM_PCR_AUTOPWRDN_EN | SDRAM_PCR_ODT_AUTO_ON); + + ast2500_sdrammc_calc_size(info); + + setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_INIT_EN); + while (!(readl(&info->regs->config) & SDRAM_CONF_CACHE_INIT_DONE)) + ; + setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_EN); + + writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control); + + /* Enable all requests except video & display */ + writel(SDRAM_REQ_USB20_EHCI1 + | SDRAM_REQ_USB20_EHCI2 + | SDRAM_REQ_CPU + | SDRAM_REQ_AHB2 + | SDRAM_REQ_AHB + | SDRAM_REQ_MAC0 + | SDRAM_REQ_MAC1 + | SDRAM_REQ_PCIE + | SDRAM_REQ_XDMA + | SDRAM_REQ_ENCRYPTION + | SDRAM_REQ_VIDEO_FLAG + | SDRAM_REQ_VIDEO_LOW_PRI_WRITE + | SDRAM_REQ_2D_RW + | SDRAM_REQ_MEMCHECK, &info->regs->req_limit_mask); + + return 0; +} + +static void ast2500_sdrammc_unlock(struct dram_info *info) +{ + writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); + while (!readl(&info->regs->protection_key)) + ; +} + +static void ast2500_sdrammc_lock(struct dram_info *info) +{ + writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); + while (readl(&info->regs->protection_key)) + ; +} + +static int ast2500_sdrammc_probe(struct udevice *dev) +{ + struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); + struct ast2500_sdrammc_regs *regs = priv->regs; + int i; + int ret = clk_get_by_index(dev, 0, &priv->ddr_clk); + + if (ret) { + debug("DDR:No CLK\n"); + return ret; + } + + priv->scu = ast_get_scu(); + if (IS_ERR(priv->scu)) { + debug("%s(): can't get SCU\n", __func__); + return PTR_ERR(priv->scu); + } + + clk_set_rate(&priv->ddr_clk, priv->clock_rate); + ret = ast_wdt_reset_masked(ast_get_wdt(0), WDT_RESET_SDRAM); + if (ret) { + debug("%s(): SDRAM reset failed\n", __func__); + return ret; + } + + ast2500_sdrammc_unlock(priv); + + writel(SDRAM_PCR_MREQI_DIS | SDRAM_PCR_RESETN_DIS, + ®s->power_control); + writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); + + /* Mask all requests except CPU and AHB during PHY init */ + writel(~(SDRAM_REQ_CPU | SDRAM_REQ_AHB), ®s->req_limit_mask); + + for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) + writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); + + setbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL); + + ast2500_sdrammc_init_phy(priv->phy); + if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) { + ast2500_sdrammc_init_ddr4(priv); + } else { + debug("Unsupported DRAM3\n"); + return -EINVAL; + } + + clrbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL); + ast2500_sdrammc_lock(priv); + + return 0; +} + +static int ast2500_sdrammc_ofdata_to_platdata(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct regmap *map; + int ret; + + ret = regmap_init_mem(dev, &map); + if (ret) + return ret; + + priv->regs = regmap_get_range(map, 0); + priv->phy = regmap_get_range(map, 1); + + priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "clock-frequency", 0); + + if (!priv->clock_rate) { + debug("DDR Clock Rate not defined\n"); + return -EINVAL; + } + + return 0; +} + +static int ast2500_sdrammc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops ast2500_sdrammc_ops = { + .get_info = ast2500_sdrammc_get_info, +}; + +static const struct udevice_id ast2500_sdrammc_ids[] = { + { .compatible = "aspeed,ast2500-sdrammc" }, + { } +}; + +U_BOOT_DRIVER(sdrammc_ast2500) = { + .name = "aspeed_ast2500_sdrammc", + .id = UCLASS_RAM, + .of_match = ast2500_sdrammc_ids, + .ops = &ast2500_sdrammc_ops, + .ofdata_to_platdata = ast2500_sdrammc_ofdata_to_platdata, + .probe = ast2500_sdrammc_probe, + .priv_auto_alloc_size = sizeof(struct dram_info), +}; diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f55348e8f1..884c21c68b 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -17,3 +17,5 @@ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_AT91) += at91/ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o + +obj-$(CONFIG_ARCH_ASPEED) += aspeed/ diff --git a/drivers/clk/aspeed/Makefile b/drivers/clk/aspeed/Makefile new file mode 100644 index 0000000000..65d1cd6e29 --- /dev/null +++ b/drivers/clk/aspeed/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2016 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ASPEED_AST2500) += clk_ast2500.o diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c new file mode 100644 index 0000000000..af369cc4c8 --- /dev/null +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -0,0 +1,265 @@ +/* + * (C) Copyright 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/scu_ast2500.h> +#include <dm/lists.h> +#include <dt-bindings/clock/ast2500-scu.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * For H-PLL and M-PLL the formula is + * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) + * M - Numerator + * N - Denumerator + * P - Post Divider + * They have the same layout in their control register. + */ + +/* + * Get the rate of the M-PLL clock from input clock frequency and + * the value of the M-PLL Parameter Register. + */ +static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg) +{ + const ulong num = (mpll_reg >> SCU_MPLL_NUM_SHIFT) & SCU_MPLL_NUM_MASK; + const ulong denum = (mpll_reg >> SCU_MPLL_DENUM_SHIFT) + & SCU_MPLL_DENUM_MASK; + const ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT) + & SCU_MPLL_POST_MASK; + + return (clkin * ((num + 1) / (denum + 1))) / post_div; +} + +/* + * Get the rate of the H-PLL clock from input clock frequency and + * the value of the H-PLL Parameter Register. + */ +static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg) +{ + const ulong num = (hpll_reg >> SCU_HPLL_NUM_SHIFT) & SCU_HPLL_NUM_MASK; + const ulong denum = (hpll_reg >> SCU_HPLL_DENUM_SHIFT) + & SCU_HPLL_DENUM_MASK; + const ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT) + & SCU_HPLL_POST_MASK; + + return (clkin * ((num + 1) / (denum + 1))) / post_div; +} + +static ulong ast2500_get_clkin(struct ast2500_scu *scu) +{ + return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ + ? 25 * 1000 * 1000 : 24 * 1000 * 1000; +} + +/** + * Get current rate or uart clock + * + * @scu SCU registers + * @uart_index UART index, 1-5 + * + * @return current setting for uart clock rate + */ +static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index) +{ + /* + * ast2500 datasheet is very confusing when it comes to UART clocks, + * especially when CLKIN = 25 MHz. The settings are in + * different registers and it is unclear how they interact. + * + * This has only been tested with default settings and CLKIN = 24 MHz. + */ + ulong uart_clkin; + + if (readl(&scu->misc_ctrl2) & + (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT))) + uart_clkin = 192 * 1000 * 1000; + else + uart_clkin = 24 * 1000 * 1000; + + if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13) + uart_clkin /= 13; + + return uart_clkin; +} + +static ulong ast2500_clk_get_rate(struct clk *clk) +{ + struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); + ulong clkin = ast2500_get_clkin(priv->scu); + ulong rate; + + switch (clk->id) { + case PLL_HPLL: + case ARMCLK: + /* + * This ignores dynamic/static slowdown of ARMCLK and may + * be inaccurate. + */ + rate = ast2500_get_hpll_rate(clkin, + readl(&priv->scu->h_pll_param)); + break; + case MCLK_DDR: + rate = ast2500_get_mpll_rate(clkin, + readl(&priv->scu->m_pll_param)); + break; + case PCLK_UART1: + rate = ast2500_get_uart_clk_rate(priv->scu, 1); + break; + case PCLK_UART2: + rate = ast2500_get_uart_clk_rate(priv->scu, 2); + break; + case PCLK_UART3: + rate = ast2500_get_uart_clk_rate(priv->scu, 3); + break; + case PCLK_UART4: + rate = ast2500_get_uart_clk_rate(priv->scu, 4); + break; + case PCLK_UART5: + rate = ast2500_get_uart_clk_rate(priv->scu, 5); + break; + default: + return -ENOENT; + } + + return rate; +} + +static void ast2500_scu_unlock(struct ast2500_scu *scu) +{ + writel(SCU_UNLOCK_VALUE, &scu->protection_key); + while (!readl(&scu->protection_key)) + ; +} + +static void ast2500_scu_lock(struct ast2500_scu *scu) +{ + writel(~SCU_UNLOCK_VALUE, &scu->protection_key); + while (readl(&scu->protection_key)) + ; +} + +static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate) +{ + ulong clkin = ast2500_get_clkin(scu); + u32 mpll_reg; + + /* + * There are not that many combinations of numerator, denumerator + * and post divider, so just brute force the best combination. + * However, to avoid overflow when multiplying, use kHz. + */ + const ulong clkin_khz = clkin / 1000; + const ulong rate_khz = rate / 1000; + ulong best_num = 0; + ulong best_denum = 0; + ulong best_post = 0; + ulong delta = rate; + ulong num, denum, post; + + for (denum = 0; denum <= SCU_MPLL_DENUM_MASK; ++denum) { + for (post = 0; post <= SCU_MPLL_POST_MASK; ++post) { + num = (rate_khz * (post + 1) / clkin_khz) * (denum + 1); + ulong new_rate_khz = (clkin_khz + * ((num + 1) / (denum + 1))) + / (post + 1); + + /* Keep the rate below requested one. */ + if (new_rate_khz > rate_khz) + continue; + + if (new_rate_khz - rate_khz < delta) { + delta = new_rate_khz - rate_khz; + + best_num = num; + best_denum = denum; + best_post = post; + + if (delta == 0) + goto rate_calc_done; + } + } + } + + rate_calc_done: + mpll_reg = readl(&scu->m_pll_param); + mpll_reg &= ~((SCU_MPLL_POST_MASK << SCU_MPLL_POST_SHIFT) + | (SCU_MPLL_NUM_MASK << SCU_MPLL_NUM_SHIFT) + | (SCU_MPLL_DENUM_MASK << SCU_MPLL_DENUM_SHIFT)); + mpll_reg |= (best_post << SCU_MPLL_POST_SHIFT) + | (best_num << SCU_MPLL_NUM_SHIFT) + | (best_denum << SCU_MPLL_DENUM_SHIFT); + + ast2500_scu_unlock(scu); + writel(mpll_reg, &scu->m_pll_param); + ast2500_scu_lock(scu); + + return ast2500_get_mpll_rate(clkin, mpll_reg); +} + +static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate) +{ + struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); + + ulong new_rate; + switch (clk->id) { + case PLL_MPLL: + case MCLK_DDR: + new_rate = ast2500_configure_ddr(priv->scu, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +struct clk_ops ast2500_clk_ops = { + .get_rate = ast2500_clk_get_rate, + .set_rate = ast2500_clk_set_rate, +}; + +static int ast2500_clk_probe(struct udevice *dev) +{ + struct ast2500_clk_priv *priv = dev_get_priv(dev); + + priv->scu = dev_get_addr_ptr(dev); + if (IS_ERR(priv->scu)) + return PTR_ERR(priv->scu); + + return 0; +} + +static int ast2500_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); + if (ret) + debug("Warning: No reset driver: ret=%d\n", ret); + + return 0; +} + +static const struct udevice_id ast2500_clk_ids[] = { + { .compatible = "aspeed,ast2500-scu" }, + { } +}; + +U_BOOT_DRIVER(aspeed_ast2500_scu) = { + .name = "aspeed_ast2500_scu", + .id = UCLASS_CLK, + .of_match = ast2500_clk_ids, + .priv_auto_alloc_size = sizeof(struct ast2500_clk_priv), + .ops = &ast2500_clk_ops, + .bind = ast2500_clk_bind, + .probe = ast2500_clk_probe, +}; diff --git a/include/dt-bindings/clock/ast2500-scu.h b/include/dt-bindings/clock/ast2500-scu.h new file mode 100644 index 0000000000..ca58b12943 --- /dev/null +++ b/include/dt-bindings/clock/ast2500-scu.h @@ -0,0 +1,29 @@ +/* + * Copyright 2016 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Core Clocks */ +#define PLL_HPLL 1 +#define PLL_DPLL 2 +#define PLL_D2PLL 3 +#define PLL_MPLL 4 +#define ARMCLK 5 + + +/* Bus Clocks, derived from core clocks */ +#define BCLK_PCLK 101 +#define BCLK_LHCLK 102 +#define BCLK_MACCLK 103 +#define BCLK_SDCLK 104 +#define BCLK_ARMCLK 105 + +#define MCLK_DDR 201 + +/* Special clocks */ +#define PCLK_UART1 501 +#define PCLK_UART2 502 +#define PCLK_UART3 503 +#define PCLK_UART4 504 +#define PCLK_UART5 505 |