diff options
| -rw-r--r-- | arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/global_data.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/soc.c | 103 | ||||
| -rw-r--r-- | board/freescale/imx8ulp_evk/imx8ulp_evk.c | 8 |
4 files changed, 92 insertions, 23 deletions
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h index 5f030eaa0ad..e240ee6fca5 100644 --- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h @@ -19,5 +19,6 @@ enum boot_device get_boot_device(void); void set_lpav_qos(void); void load_lposc_fuse(void); bool m33_image_booted(void); +bool is_m33_handshake_necessary(void); int m33_image_handshake(ulong timeout_ms); #endif diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 6ee2a767615..8d25c32c3a9 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -97,6 +97,9 @@ struct arch_global_data { u32 uid[4]; #endif +#ifdef CONFIG_ARCH_IMX8ULP + bool m33_handshake_done; +#endif }; #include <asm-generic/global_data.h> diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 62915e03166..2a3f417ab94 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -186,14 +186,70 @@ enum bt_mode get_boot_mode(void) bool m33_image_booted(void) { - u32 gp6 = 0; + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + u32 gp6 = 0; + + /* DGO_GP6 */ + gp6 = readl(SIM_SEC_BASE_ADDR + 0x28); + if (gp6 & (1 << 5)) + return true; - /* DGO_GP6 */ - gp6 = readl(SIM_SEC_BASE_ADDR + 0x28); - if (gp6 & (1 << 5)) - return true; + return false; + } else { + u32 gpr0 = readl(SIM1_BASE_ADDR); + if (gpr0 & 0x1) + return true; - return false; + return false; + } +} + +bool rdc_enabled_in_boot(void) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + u32 val = 0; + int ret; + bool rdc_en = true; /* Default assume DBD_EN is set */ + + /* Read DBD_EN fuse */ + ret = fuse_read(8, 1, &val); + if (!ret) + rdc_en = !!(val & 0x200); /* only A1 part uses DBD_EN, so check DBD_EN new place*/ + + return rdc_en; + } else { + u32 gpr0 = readl(SIM1_BASE_ADDR); + if (gpr0 & 0x2) + return true; + + return false; + } +} + +static void spl_pass_boot_info(void) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + bool m33_booted = m33_image_booted(); + bool rdc_en = rdc_enabled_in_boot(); + u32 val = 0; + + if (m33_booted) + val |= 0x1; + + if (rdc_en) + val |= 0x2; + + writel(val, SIM1_BASE_ADDR); + } +} + +bool is_m33_handshake_necessary(void) +{ + /* Only need handshake in u-boot */ + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + return (m33_image_booted() || rdc_enabled_in_boot()); + else + return false; } int m33_image_handshake(ulong timeout_ms) @@ -746,10 +802,6 @@ void set_lpav_qos(void) int arch_cpu_init(void) { if (IS_ENABLED(CONFIG_SPL_BUILD)) { - u32 val = 0; - int ret; - bool rdc_en = true; /* Default assume DBD_EN is set */ - /* Enable System Reset Interrupt using WDOG_AD */ setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13)); /* Clear AD_PERIPH Power switch domain out of reset interrupt flag */ @@ -766,11 +818,6 @@ int arch_cpu_init(void) /* Disable wdog */ init_wdog(); - /* Read DBD_EN fuse */ - ret = fuse_read(8, 1, &val); - if (!ret) - rdc_en = !!(val & 0x4000); - if (get_boot_mode() == SINGLE_BOOT) { lpav_configure(false); } else { @@ -778,12 +825,14 @@ int arch_cpu_init(void) } /* Release xrdc, then allow A35 to write SRAM2 */ - if (rdc_en) + if (rdc_enabled_in_boot()) release_rdc(RDC_XRDC); xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00); clock_init_early(); + + spl_pass_boot_info(); } else { /* reconfigure core0 reset vector to ROM */ set_core0_reset_vector(0x1000); @@ -792,6 +841,17 @@ int arch_cpu_init(void) return 0; } +int checkcpu(void) +{ + if (is_m33_handshake_necessary()) { + if (!gd->arch.m33_handshake_done) + panic("M33 Sync: Timeout, Boot Stop!\n"); + else + puts("M33 Sync: OK\n"); + } + return 0; +} + int arch_cpu_init_dm(void) { struct udevice *devp; @@ -799,6 +859,17 @@ int arch_cpu_init_dm(void) u32 res; struct sentinel_get_info_data info; + if (!IS_ENABLED(CONFIG_SPL_BUILD) && is_m33_handshake_necessary()) { + /* Start handshake with M33 to ensure TRDC configuration completed */ + ret = m33_image_handshake(1000); + if (!ret) { + gd->arch.m33_handshake_done = true; + } else { + gd->arch.m33_handshake_done = false; + return 0; /* Skip and go through to panic in checkcpu as console is ready then */ + } + } + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8ulp-mu"); ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp); diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c index 4f4006a7594..3b0c57e497c 100644 --- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c @@ -164,7 +164,6 @@ void reset_lsm6dsx(uint8_t i2c_bus, uint8_t addr) int board_init(void) { - int sync = -ENODEV; #if defined(CONFIG_NXP_FSPI) || defined(CONFIG_FSL_FSPI_NAND) setup_flexspi(); @@ -177,13 +176,8 @@ int board_init(void) setup_fec(); #endif - if (m33_image_booted()) { - sync = m33_image_handshake(1000); - printf("M33 Sync: %s\n", sync? "Timeout": "OK"); - } - /* When sync with M33 is failed, use local driver to set for video */ - if (sync != 0 && IS_ENABLED(CONFIG_DM_VIDEO)) { + if (!is_m33_handshake_necessary() && IS_ENABLED(CONFIG_DM_VIDEO)) { mipi_dsi_mux_panel(); mipi_dsi_panel_backlight(); } |