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-rw-r--r--arch/arm/include/asm/arch-imx8/lpcg.h4
-rw-r--r--arch/arm/include/asm/arch-imx8/sci/types.h11
-rw-r--r--arch/arm/mach-imx/imx8/clock.c16
-rw-r--r--drivers/clk/imx/Makefile1
-rw-r--r--drivers/clk/imx/clk-imx8.c2
-rw-r--r--drivers/clk/imx/clk-imx8qxp.c14
-rw-r--r--include/dt-bindings/clock/imx8qxp-clock.h11
7 files changed, 44 insertions, 15 deletions
diff --git a/arch/arm/include/asm/arch-imx8/lpcg.h b/arch/arm/include/asm/arch-imx8/lpcg.h
index b3a454500d..85cb5b30c1 100644
--- a/arch/arm/include/asm/arch-imx8/lpcg.h
+++ b/arch/arm/include/asm/arch-imx8/lpcg.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -11,6 +11,8 @@
#include "imx8qm_lpcg.h"
#elif defined(CONFIG_IMX8QXP)
#include "imx8qxp_lpcg.h"
+#elif defined(CONFIG_IMX8DXL)
+#include "imx8qxp_lpcg.h"
#else
#error "No lpcg header"
#endif
diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h b/arch/arm/include/asm/arch-imx8/sci/types.h
index a5c00c3c39..36d5dee96e 100644
--- a/arch/arm/include/asm/arch-imx8/sci/types.h
+++ b/arch/arm/include/asm/arch-imx8/sci/types.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*/
#ifndef SC_TYPES_H
@@ -215,10 +215,11 @@ typedef u64 sc_ipc_t;
#define SC_C_SYNC_CTRL 55U
#define SC_C_OFS_AUDIO_ALT 56U
#define SC_C_DSP_BYP 57U
-#define SC_C_LAST 58U
-
-
-#define SC_P_ALL ((sc_pad_t)UINT16_MAX) /* All pads */
+#define SC_C_CLK_GEN_EN 58U
+#define SC_C_INTF_SEL 59U
+#define SC_C_RXC_DLY 60U
+#define SC_C_TIMER_SEL 61U
+#define SC_C_LAST 62U
/* Types */
diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c
index cb9ec2090f..645225e4c2 100644
--- a/arch/arm/mach-imx/imx8/clock.c
+++ b/arch/arm/mach-imx/imx8/clock.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*/
#include <common.h>
@@ -354,6 +354,8 @@ void init_clk_fec(int index)
* so finally RGMII TX clk is 125Mhz
*/
rate = 250000000;
+ if (is_imx8dxl() && index == 1) /* eQos */
+ rate = 125000000;
/* div = 8 clk_source = PLL_1 ss_slice #7 in verfication codes */
err = sc_pm_set_clock_rate(-1, enet[index], 2, &rate);
@@ -372,11 +374,13 @@ void init_clk_fec(int index)
}
/* Configure GPR regisers */
- if (sc_misc_set_control(-1, enet[index], SC_C_TXCLK, 0) != SC_ERR_NONE)
- printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_TXCLK);
- /* Enable divclk */
- if (sc_misc_set_control(-1, enet[index], SC_C_CLKDIV, 1) != SC_ERR_NONE)
- printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_CLKDIV);
+ if (!(is_imx8dxl() && index == 1)) {
+ if (sc_misc_set_control(-1, enet[index], SC_C_TXCLK, 0) != SC_ERR_NONE)
+ printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_TXCLK);
+ /* Enable divclk */
+ if (sc_misc_set_control(-1, enet[index], SC_C_CLKDIV, 1) != SC_ERR_NONE)
+ printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_CLKDIV);
+ }
if (sc_misc_set_control(-1, enet[index], SC_C_DISABLE_50, 1) != SC_ERR_NONE)
printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_DISABLE_50);
if (sc_misc_set_control(-1, enet[index], SC_C_DISABLE_125, 1) != SC_ERR_NONE)
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 01bbbdf3ae..5f07207cce 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
ifdef CONFIG_CLK_IMX8
obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
+obj-$(CONFIG_IMX8DXL) += clk-imx8qxp.o
obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
endif
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \
diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c
index 62c44d681d..dc836bbc61 100644
--- a/drivers/clk/imx/clk-imx8.c
+++ b/drivers/clk/imx/clk-imx8.c
@@ -19,7 +19,7 @@
#include "clk-imx8.h"
struct imx8_clks_collect *soc_data[] = {
-#ifdef CONFIG_IMX8QXP
+#if defined(CONFIG_IMX8QXP) || defined(CONFIG_IMX8DXL)
&imx8qxp_clk_collect,
#endif
#ifdef CONFIG_IMX8QM
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index d78909a917..63401b466f 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -35,7 +35,9 @@ static struct imx8_clks imx8qxp_clks[] = {
CLK_4( IMX8QXP_SDHC0_DIV, "SDHC0_DIV", SC_R_SDHC_0, SC_PM_CLK_PER ),
CLK_4( IMX8QXP_SDHC1_DIV, "SDHC1_DIV", SC_R_SDHC_1, SC_PM_CLK_PER ),
CLK_4( IMX8QXP_SDHC2_DIV, "SDHC2_DIV", SC_R_SDHC_2, SC_PM_CLK_PER ),
+#if !defined(CONFIG_IMX8DXL)
CLK_4( IMX8QXP_ENET0_ROOT_DIV, "ENET0_ROOT_DIV", SC_R_ENET_0, SC_PM_CLK_PER ),
+#endif
CLK_4( IMX8QXP_ENET0_RGMII_DIV, "ENET0_RGMII_DIV", SC_R_ENET_0, SC_PM_CLK_MISC0 ),
CLK_4( IMX8QXP_ENET1_ROOT_DIV, "ENET1_ROOT_DIV", SC_R_ENET_1, SC_PM_CLK_PER ),
CLK_4( IMX8QXP_ENET1_RGMII_DIV, "ENET1_RGMII_DIV", SC_R_ENET_1, SC_PM_CLK_MISC0 ),
@@ -57,6 +59,9 @@ static struct imx8_fixed_clks imx8qxp_fixed_clks[] = {
CLK_3( IMX8QXP_LSIO_MEM_CLK, "LSIO_MEM_CLK", SC_200MHZ ),
CLK_3( IMX8QXP_HSIO_PER_CLK, "HSIO_CLK", SC_133MHZ ),
CLK_3( IMX8QXP_HSIO_AXI_CLK, "HSIO_AXI", SC_400MHZ ),
+#if defined(CONFIG_IMX8DXL)
+ CLK_3( IMX8QXP_ENET0_ROOT_DIV, "ENET0_ROOT_DIV", SC_250MHZ ),
+#endif
};
static struct imx8_gpr_clks imx8qxp_gpr_clks[] = {
@@ -125,6 +130,15 @@ static struct imx8_lpcg_clks imx8qxp_lpcg_clks[] = {
CLK_5( IMX8QXP_ENET1_RGMII_TX_CLK, "ENET1_RGMII_TX", 12, ENET_1_LPCG, IMX8QXP_ENET1_RMII_TX_SEL ),
CLK_5( IMX8QXP_ENET1_RMII_RX_CLK, "ENET1_RMII_RX", 0, ENET_1_LPCG + 0x4, IMX8QXP_ENET1_RGMII_DIV ),
+#if defined(CONFIG_IMX8DXL)
+ CLK_5( IMX8DXL_EQOS_MEM_CLK, "EQOS_MEM_CLK", 8, ENET_1_LPCG, IMX8QXP_AXI_CONN_CLK_ROOT ),
+ CLK_5( IMX8DXL_EQOS_ACLK, "EQOS_ACLK", 16, ENET_1_LPCG, IMX8DXL_EQOS_MEM_CLK ),
+ CLK_5( IMX8DXL_EQOS_CSR_CLK, "EQOS_CSR_CLK", 24, ENET_1_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
+ CLK_5( IMX8DXL_EQOS_CLK, "EQOS_CLK", 20, ENET_1_LPCG, IMX8QXP_ENET1_ROOT_DIV ),
+ CLK_5( IMX8DXL_EQOS_PTP_CLK_S, "EQOS_PTP_S", 8, ENET_1_LPCG, IMX8QXP_ENET0_ROOT_DIV ),
+ CLK_5( IMX8DXL_EQOS_PTP_CLK, "EQOS_PTP", 0, ENET_1_LPCG, IMX8DXL_EQOS_PTP_CLK_S ),
+#endif
+
CLK_5( IMX8QXP_LSIO_FSPI0_IPG_S_CLK, "FSPI0_IPG_S", 0x18, FSPI_0_LPCG, IMX8QXP_LSIO_BUS_CLK ),
CLK_5( IMX8QXP_LSIO_FSPI0_IPG_CLK, "FSPI0_IPG", 0x14, FSPI_0_LPCG, IMX8QXP_LSIO_FSPI0_IPG_S_CLK ),
CLK_5( IMX8QXP_LSIO_FSPI0_HCLK, "FSPI0_HCLK", 0x10, FSPI_0_LPCG, IMX8QXP_LSIO_MEM_CLK ),
diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h
index 2aa927dba3..fb563e26d1 100644
--- a/include/dt-bindings/clock/imx8qxp-clock.h
+++ b/include/dt-bindings/clock/imx8qxp-clock.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*/
#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H
@@ -583,5 +583,12 @@
#define IMX8QXP_ELCDIF_PLL 535
#define IMX8QXP_LCD_SEL 536
-#define IMX8QXP_CLK_END 537
+#define IMX8DXL_EQOS_MEM_CLK 537
+#define IMX8DXL_EQOS_ACLK 538
+#define IMX8DXL_EQOS_CSR_CLK 539
+#define IMX8DXL_EQOS_CLK 540
+#define IMX8DXL_EQOS_PTP_CLK_S 541
+#define IMX8DXL_EQOS_PTP_CLK 542
+
+#define IMX8QXP_CLK_END 543
#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-30 13:05:35 +0000