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-rw-r--r--arch/arm/dts/imx8mp-evk-u-boot.dtsi58
-rw-r--r--arch/arm/dts/imx8mp-evk.dts378
-rw-r--r--arch/arm/dts/imx8mp.dtsi449
-rw-r--r--include/dt-bindings/clock/imx8mp-clock.h209
-rw-r--r--include/dt-bindings/reset/imx8mp-reset.h96
5 files changed, 1087 insertions, 103 deletions
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index 52f473dc52..ba70fa906d 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -19,12 +19,13 @@
};
};
-&reg_usdhc2_vmmc {
- u-boot,off-on-delay-us = <20000>;
+&pinctrl_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
};
&reg_usdhc2_vmmc {
u-boot,dm-spl;
+ u-boot,off-on-delay-us = <20000>;
};
&pinctrl_uart2 {
@@ -95,38 +96,55 @@
u-boot,dm-spl;
};
-&i2c4 {
- u-boot,dm-spl;
-};
-
-&i2c5 {
+&pinctrl_i2c1 {
u-boot,dm-spl;
};
-&i2c6 {
+&pinctrl_i2c1_gpio {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
+ assigned-clock-rates = <400000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};
&usdhc2 {
u-boot,dm-spl;
sd-uhs-sdr104;
sd-uhs-ddr50;
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+ assigned-clock-rates = <400000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};
&usdhc3 {
u-boot,dm-spl;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+ assigned-clock-rates = <400000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};
&wdog1 {
u-boot,dm-spl;
};
+&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
+
&eqos {
compatible = "fsl,imx-eqos";
/delete-property/ assigned-clocks;
@@ -146,4 +164,28 @@
phy-reset-post-delay = <100>;
};
+&flexspi {
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+};
+
+&usb3_0 {
+ /delete-property/ power-domains;
+};
+
+&usb3_1 {
+ /delete-property/ power-domains;
+};
+&usb_dwc3_0 {
+ compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <400000000>;
+};
+
+&usb_dwc3_1 {
+ compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <400000000>;
+};
diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts
index f846d69dac..b0dacf03e7 100644
--- a/arch/arm/dts/imx8mp-evk.dts
+++ b/arch/arm/dts/imx8mp-evk.dts
@@ -5,13 +5,15 @@
/dts-v1/;
+#include <dt-bindings/usb/pd.h>
#include "imx8mp.dtsi"
/ {
- model = "NXP i.MX8MPlus EVK board";
+ model = "NXP i.MX8MPlus LPDDR4 EVK board";
compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
chosen {
+ bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
stdout-path = &uart2;
};
@@ -64,6 +66,22 @@
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ };
+
+ cbtl04gp {
+ compatible = "nxp,cbtl04gp";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec_mux>;
+ switch-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
+ orientation-switch;
+
+ port {
+ usb3_data_ss: endpoint {
+ remote-endpoint = <&typec_con_ss>;
+ };
+ };
};
};
@@ -117,15 +135,214 @@
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
eee-broken-1000t;
- reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
};
};
};
-&i2c3 {
- clock-frequency = <400000>;
+&flexspi {
pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ status = "okay";
+
+ flash0: mt25qu256aba@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ pmic: pca9450@25 {
+ reg = <0x25>;
+ compatible = "nxp,pca9450c";
+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
+ pinctrl-0 = <&pinctrl_pmic>;
+ gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9450,pmic-buck2-uses-i2c-dvs;
+ /* Run/Standby voltage */
+ pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
+
+ buck1_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "buck1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2_reg: regulator@1 {
+ reg = <1>;
+ regulator-compatible = "buck2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "buck4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: regulator@4 {
+ reg = <4>;
+ regulator-compatible = "buck5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: regulator@5 {
+ reg = <5>;
+ regulator-compatible = "buck6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: regulator@6 {
+ reg = <6>;
+ regulator-compatible = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: regulator@7 {
+ reg = <7>;
+ regulator-compatible = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: regulator@8 {
+ reg = <8>;
+ regulator-compatible = "ldo3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: regulator@9 {
+ reg = <9>;
+ regulator-compatible = "ldo4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: regulator@10 {
+ reg = <10>;
+ regulator-compatible = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ adv_bridge: adv7535@3d {
+ compatible = "adi,adv7533";
+ reg = <0x3d>;
+ adi,addr-cec = <0x3b>;
+ adi,dsi-lanes = <4>;
+ status = "okay";
+
+ port {
+ adv7535_from_dsim: endpoint {
+ remote-endpoint = <&dsim_to_adv7535>;
+ };
+ };
+ };
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec>;
+ reg = <0x50>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <19 8>;
+
+ port {
+ typec_dr_sw: endpoint {
+ remote-endpoint = <&usb3_drd_sw>;
+ };
+ };
+
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ op-sink-microwatt = <15000000>;
+ self-powered;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ typec_con_ss: endpoint {
+ remote-endpoint = <&usb3_data_ss>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
status = "okay";
pca6416: gpio@20 {
@@ -136,6 +353,21 @@
};
};
+&lcdif1 {
+ status = "okay";
+};
+
+&mipi_dsi {
+ status = "okay";
+
+ port@1 {
+ dsim_to_adv7535: endpoint {
+ remote-endpoint = <&adv7535_from_dsim>;
+ attach-bridge;
+ };
+ };
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -147,9 +379,55 @@
status = "okay";
};
+&usb3_phy0 {
+ vbus-power-supply = <&ptn5110>;
+ fsl,phy-tx-vref-tune = <0xe>;
+ fsl,phy-tx-preemp-amp-tune = <3>;
+ fsl,phy-tx-vboost-level = <5>;
+ fsl,phy-comp-dis-tune = <7>;
+ fsl,pcs-tx-deemph-3p5db = <0x21>;
+ fsl,phy-pcs-tx-swing-full = <0x7f>;
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ role-switch-default-mode = "none";
+ status = "okay";
+
+ port {
+ usb3_drd_sw: endpoint {
+ remote-endpoint = <&typec_dr_sw>;
+ };
+ };
+};
+
+&usb3_phy1 {
+ fsl,phy-tx-preemp-amp-tune = <3>;
+ fsl,phy-tx-vref-tune = <0xb>;
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_vbus>;
+ dr_mode = "host";
+ status = "okay";
+};
+
&usdhc2 {
- assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
- assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
@@ -161,8 +439,6 @@
};
&usdhc3 {
- assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
- assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
@@ -180,6 +456,8 @@
};
&iomuxc {
+ pinctrl-names = "default";
+
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
@@ -246,20 +524,90 @@
>;
};
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
+ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
+ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
+ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
+ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
+ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
+ >;
+ };
+
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
>;
};
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
>;
};
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ pinctrl_i2c1_gpio: i2c1grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
+ MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
+ MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3grp-gpio {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
+ MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
+ >;
+ };
+
+ pinctrl_mipi_dsi_en: mipi_dsi_en {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x16
+ >;
+ };
+
+ pinctrl_pmic: pmicirq {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ >;
+ };
+
+ pinctrl_typec: typec1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4
+ >;
+ };
+
+ pinctrl_typec_mux: typec1muxgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
>;
@@ -272,6 +620,12 @@
>;
};
+ pinctrl_usb1_vbus: usb1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19
+ >;
+ };
+
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
@@ -364,7 +718,7 @@
pinctrl_wdog: wdoggrp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
};
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index c2d51a46cb..74d33fd05f 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/imx8mp-clock.h>
+#include <dt-bindings/reset/imx8mp-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -37,6 +38,9 @@
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
+ usb0 = &usb_dwc3_0;
+ usb1 = &usb_dwc3_1;
+ spi0 = &flexspi;
};
cpus {
@@ -92,6 +96,16 @@
};
};
+ gic: interrupt-controller@38800000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
+ <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ };
+
osc_32k: clock-osc-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -134,10 +148,200 @@
clock-output-names = "clk_ext4";
};
+ busfreq { /* BUSFREQ */
+ compatible = "fsl,imx_busfreq";
+ clocks = <&clk IMX8MP_DRAM_PLL_OUT>, <&clk IMX8MP_CLK_DRAM_ALT>,
+ <&clk IMX8MP_CLK_DRAM_APB>, <&clk IMX8MP_CLK_DRAM_APB>,
+ <&clk IMX8MP_CLK_DRAM_CORE>, <&clk IMX8MP_CLK_DRAM_ALT_ROOT>,
+ <&clk IMX8MP_SYS_PLL1_40M>, <&clk IMX8MP_SYS_PLL1_100M>,
+ <&clk IMX8MP_SYS_PLL2_333M>, <&clk IMX8MP_CLK_NOC>,
+ <&clk IMX8MP_CLK_AHB>, <&clk IMX8MP_CLK_MAIN_AXI>,
+ <&clk IMX8MP_CLK_24M>, <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_DRAM_PLL>;
+ clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div",
+ "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m",
+ "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m",
+ "sys_pll1_800m", "dram_pll_div";
+ };
+
+ power-domains {
+ compatible = "simple-bus";
+
+ /* HSIO SS */
+ hsiomix_pd: hsiomix-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ active-wakeup;
+ rpm-always-on;
+ #power-domain-cells = <0>;
+ domain-index = <0>;
+ domain-name = "hsiomix";
+ };
+
+ pcie_pd: pcie-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <1>;
+ domain-name = "pcie";
+ parent-domains = <&hsiomix_pd>;
+ };
+
+ usb_otg1_pd: usbotg1-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <2>;
+ domain-name = "usb_otg1";
+ parent-domains = <&hsiomix_pd>;
+ };
+
+ usb_otg2_pd: usbotg2-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <3>;
+ domain-name = "usb_otg2";
+ parent-domains = <&hsiomix_pd>;
+ };
+
+ /* MLMIX */
+ mlmix_pd: mlmix-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <4>;
+ domain-name = "mlmix";
+ clocks = <&clk IMX8MP_CLK_ML_AXI>,
+ <&clk IMX8MP_CLK_ML_AHB>,
+ <&clk IMX8MP_CLK_NPU_ROOT>;
+ };
+
+ audiomix_pd: audiomix-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <5>;
+ domain-name = "audiomix";
+ clocks = <&clk IMX8MP_CLK_AUDIO_AHB_ROOT>,
+ <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>;
+ };
+
+ gpumix_pd: gpumix-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <6>;
+ domain-name = "gpumix";
+ clocks = <&clk IMX8MP_CLK_GPU_ROOT>, <&clk IMX8MP_CLK_GPU_AHB>,
+ <&clk IMX8MP_CLK_GPU_AXI>;
+ };
+
+ gpu2d_pd: gpu2d-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <7>;
+ domain-name = "gpu2d";
+ parent-domains = <&gpumix_pd>;
+ clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
+ };
+
+ gpu3d_pd: gpu3d-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <8>;
+ domain-name = "gpu3d";
+ parent-domains = <&gpumix_pd>;
+ clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
+ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
+ };
+
+ vpumix_pd: vpumix-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <9>;
+ domain-name = "vpumix";
+ clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
+ };
+
+ vpu_g1_pd: vpug1-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <10>;
+ domain-name = "vpu_g1";
+ parent-domains = <&vpumix_pd>;
+ clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
+ };
+
+ vpu_g2_pd: vpug2-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <11>;
+ domain-name = "vpu_g2";
+ parent-domains = <&vpumix_pd>;
+ clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
+ };
+
+ vpu_h1_pd: vpuh1-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <12>;
+ domain-name = "vpu_h1";
+ parent-domains = <&vpumix_pd>;
+ clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
+ };
+
+ mediamix_pd: mediamix-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <13>;
+ domain-name = "mediamix";
+ clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+ };
+
+ ispdwp_pd: power-domain@14 {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <14>;
+ domain-name = "ispdwp";
+ parent-domains = <&mediamix_pd>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_ISP>;
+ };
+
+ mipi_phy1_pd: mipiphy1-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <15>;
+ domain-name = "mipi_phy1";
+ parent-domains = <&mediamix_pd>;
+ };
+
+ mipi_phy2_pd: mipiphy2-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <16>;
+ domain-name = "mipi_phy2";
+ parent-domains = <&mediamix_pd>;
+ };
+
+ hdmimix_pd: hdmimix-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <17>;
+ domain-name = "hdmimix";
+ clocks = <&clk IMX8MP_CLK_HDMI_ROOT>,
+ <&clk IMX8MP_CLK_HDMI_APB>,
+ <&clk IMX8MP_CLK_HDMI_REF_266M>;
+ };
+
+ hdmi_phy_pd: hdmiphy-pd {
+ compatible = "fsl,imx8m-pm-domain";
+ #power-domain-cells = <0>;
+ domain-index = <18>;
+ domain-name = "hdmi_phy";
+ parent-domains = <&hdmimix_pd>;
+ };
+ };
+
pmu {
- compatible = "arm,cortex-a53-pmu";
+ compatible = "arm,armv8-pmuv3";
+ interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
};
@@ -210,12 +414,13 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <8000000>;
arm,no-tick-in-suspend;
+ interrupt-parent = <&gic>;
};
soc@0 {
@@ -226,6 +431,11 @@
nvmem-cells = <&imx8mp_uid>;
nvmem-cell-names = "soc_unique_id";
+ caam_sm: caam-sm@100000 {
+ compatible = "fsl,imx6q-caam-sm";
+ reg = <0x100000 0x8000>;
+ };
+
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30000000 0x400000>;
@@ -295,7 +505,6 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- gpio-ranges = <&iomuxc 0 114 30>;
};
tmu: tmu@30260000 {
@@ -335,7 +544,8 @@
};
gpr: iomuxc-gpr@30340000 {
- compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
+ compatible = "fsl,imx8mp-iomuxc-gpr",
+ "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
@@ -366,6 +576,22 @@
reg = <0x30360000 0x10000>;
};
+ irq_sec_vio: caam_secvio {
+ compatible = "fsl,imx6q-caam-secvio";
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ jtag-tamper = "disabled";
+ watchdog-tamper = "enabled";
+ internal-boot-tamper = "enabled";
+ external-pin-tamper = "disabled";
+ };
+
+ caam_snvs: caam-snvs@30370000 {
+ compatible = "fsl,imx6q-caam-snvs";
+ reg = <0x30370000 0x10000>;
+ clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
+ clock-names = "ipg";
+ };
+
snvs: snvs@30370000 {
compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
reg = <0x30370000 0x10000>;
@@ -409,7 +635,8 @@
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
<&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
<&clk IMX8MP_AUDIO_PLL1>,
- <&clk IMX8MP_AUDIO_PLL2>;
+ <&clk IMX8MP_AUDIO_PLL2>,
+ <&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_ARM_PLL_OUT>,
<&clk IMX8MP_SYS_PLL2_1000M>,
@@ -425,7 +652,8 @@
<800000000>,
<400000000>,
<393216000>,
- <361267200>;
+ <361267200>,
+ <1039500000>;
};
src: reset-controller@30390000 {
@@ -512,6 +740,9 @@
clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
<&clk IMX8MP_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
+ assigned-clock-rates = <80000000>;
+ assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
dma-names = "rx", "tx";
status = "disabled";
@@ -526,6 +757,9 @@
clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
<&clk IMX8MP_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
+ assigned-clock-rates = <80000000>;
+ assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
dma-names = "rx", "tx";
status = "disabled";
@@ -540,6 +774,9 @@
clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
<&clk IMX8MP_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
+ assigned-clock-rates = <80000000>;
+ assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
dma-names = "rx", "tx";
status = "disabled";
@@ -589,8 +826,8 @@
assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
- fsl,clk-source = /bits/ 8 <0>;
- fsl,stop-mode = <&gpr 0x10 4>;
+ fsl,clk-source= <0>;
+ fsl,stop-mode = <&gpr 0x10 4 0x10 20>;
status = "disabled";
};
@@ -604,8 +841,8 @@
assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
- fsl,clk-source = /bits/ 8 <0>;
- fsl,stop-mode = <&gpr 0x10 5>;
+ fsl,clk-source= <0>;
+ fsl,stop-mode = <&gpr 0x10 5 0x10 21>;
status = "disabled";
};
@@ -719,6 +956,15 @@
status = "disabled";
};
+ flexspi_nand: flexspi_nand@30bb0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8mp-fspi-nand";
+ reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>;
+ reg-names = "FlexSPI", "FlexSPI-memory";
+ status = "disabled";
+ };
+
usdhc1: mmc@30b40000 {
compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>;
@@ -727,6 +973,8 @@
<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
<&clk IMX8MP_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
+ assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
@@ -741,6 +989,8 @@
<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
<&clk IMX8MP_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+ assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
@@ -755,12 +1005,29 @@
<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
<&clk IMX8MP_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+ assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
status = "disabled";
};
+ flexspi: spi@30bb0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imx8mm-fspi";
+ reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
+ <&clk IMX8MP_CLK_QSPI_ROOT>;
+ clock-names = "fspi", "fspi_en";
+ assigned-clock-rates = <80000000>;
+ assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
+ status = "disabled";
+ };
+
sdma1: dma-controller@30bd0000 {
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
reg = <0x30bd0000 0x10000>;
@@ -827,14 +1094,71 @@
};
};
- gic: interrupt-controller@38800000 {
- compatible = "arm,gic-v3";
- reg = <0x38800000 0x10000>,
- <0x38880000 0xc0000>;
- #interrupt-cells = <3>;
- interrupt-controller;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
+ aips4: bus@32c00000 {
+ compatible = "simple-bus";
+ reg = <0x32c00000 0x400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mipi_dsi: mipi_dsi@32e60000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8mp-mipi-dsim";
+ reg = <0x32e60000 0x10000>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
+ clock-names = "cfg", "pll-ref";
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
+ assigned-clock-rates = <594000000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&mipi_phy1_pd>;
+ status = "disabled";
+
+ port@0 {
+ dsim_from_lcdif: endpoint {
+ remote-endpoint = <&lcdif_to_dsim>;
+ };
+ };
+ };
+
+ lcdif1: lcd-controller@32e80000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8mp-lcdif1";
+ reg = <0x32e80000 0x10000>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+ clock-names = "pix", "disp-axi", "disp-apb";
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
+ <&clk IMX8MP_CLK_MEDIA_AXI>,
+ <&clk IMX8MP_CLK_MEDIA_APB>;
+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,
+ <&clk IMX8MP_SYS_PLL2_1000M>,
+ <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <594000000>, <500000000>, <200000000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ blk-ctl = <&mediamix_blk_ctl>;
+ power-domains = <&mediamix_pd>;
+ status = "disabled";
+
+ lcdif_disp0: port@0 {
+ reg = <0>;
+
+ lcdif_to_dsim: endpoint {
+ remote-endpoint = <&dsim_from_lcdif>;
+ };
+ };
+ };
+
+ mediamix_blk_ctl: blk-ctl@32ec0000 {
+ compatible = "fsl,imx8mp-mediamix-blk-ctl",
+ "syscon";
+ reg = <0x32ec0000 0x10000>;
+ };
+
};
ddr-pmu@3d800000 {
@@ -861,6 +1185,7 @@
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "hsio", "suspend";
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&hsiomix_pd>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
@@ -902,6 +1227,7 @@
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "hsio", "suspend";
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&hsiomix_pd>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
@@ -925,4 +1251,83 @@
};
};
};
+
+ pcie_phy: pcie-phy@32f00000 {
+ compatible = "fsl,imx8mp-pcie-phy";
+ reg = <0x0 0x32f00000 0x0 0x10000>;
+ clocks = <&clk IMX8MP_CLK_PCIE_PHY>;
+ clock-names = "phy";
+ assigned-clocks = <&clk IMX8MP_CLK_PCIE_PHY>;
+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ hsio_mix: hsio-mix@32f10000 {
+ compatible = "fsl,imx8mp-hsio-mix";
+ reg = <0x0 0x32f10000 0x0 0x8>;
+ };
+
+ dma_apbh: dma-apbh@33000000 {
+ compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0 0x33000000 0 0x2000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ clocks = <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+ };
+
+ gpmi: gpmi-nand@33002000{
+ compatible = "fsl,imx7d-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x33002000 0 0x2000>, <0 0x33004000 0 0x4000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bch";
+ clocks = <&clk IMX8MP_CLK_NAND_ROOT>,
+ <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+ clock-names = "gpmi_io", "gpmi_bch_apb";
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ pcie: pcie@33800000 {
+ compatible = "fsl,imx8mp-pcie", "snps,dw-pcie";
+ reg = <0x0 0x33800000 0x0 0x400000>,
+ <0x0 0x1ff00000 0x0 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+ 0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+ interrupt-names = "msi", "dma";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,max-link-speed = <3>;
+ power-domains = <&pcie_pd>;
+ resets = <&src IMX8MP_RESET_PCIEPHY>,
+ <&src IMX8MP_RESET_PCIEPHY_PERST>,
+ <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MP_RESET_PCIE_CTRL_APPS_CLK_REQ>,
+ <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff";
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+ fsl,imx8mp-hsio-mix = <&hsio_mix>;
+ status = "disabled";
+ };
};
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index e8d68fbb6e..3784cbbc75 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -322,68 +322,155 @@
#define IMX8MP_CLK_HSIO_AXI 311
#define IMX8MP_CLK_MEDIA_ISP 312
-#define IMX8MP_CLK_END 313
+#define IMX8MP_CLK_MEDIA_DISP2_PIX 313
+#define IMX8MP_CLK_MEDIA_LDB_ROOT 314
+#define IMX8MP_CLK_AUDIO_AHB_ROOT 315
+#define IMX8MP_CLK_AUDIO_AXI_ROOT 316
+#define IMX8MP_CLK_SAI1_ROOT 317
+#define IMX8MP_CLK_SAI2_ROOT 318
+#define IMX8MP_CLK_SAI3_ROOT 319
+#define IMX8MP_CLK_SAI5_ROOT 320
+#define IMX8MP_CLK_SAI6_ROOT 321
+#define IMX8MP_CLK_SAI7_ROOT 322
+#define IMX8MP_CLK_PDM_ROOT 323
-#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2
-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3
-#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4
-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5
-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6
-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7
-#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8
-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9
-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10
-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11
-#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12
-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13
-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14
-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15
-#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16
-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17
-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18
-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19
-#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20
-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21
-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22
-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23
-#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24
-#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25
-#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26
-#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27
-#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28
-#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29
-#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30
-#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31
-#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32
-#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33
-#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34
-#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35
-#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36
-#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37
-#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38
-#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39
-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40
-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41
-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42
-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43
-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44
-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45
-#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46
-#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47
-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48
-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49
-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50
-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51
-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52
-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53
-#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54
-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55
-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56
-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57
-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58
+#define IMX8MP_SAI1_MCLK 324
+#define IMX8MP_SAI2_MCLK 325
+#define IMX8MP_SAI3_MCLK 326
+#define IMX8MP_SAI4_MCLK 327
+#define IMX8MP_SAI5_MCLK 328
+#define IMX8MP_SAI6_MCLK 329
+#define IMX8MP_SAI7_MCLK 330
-#define IMX8MP_CLK_AUDIOMIX_END 59
+#define IMX8MP_CLK_END 331
+
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_IPG 0
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1 1
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK2 2
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK3 3
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_IPG 4
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK1 5
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK2 6
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK3 7
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG 8
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1 9
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK2 10
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK3 11
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_IPG 12
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1 13
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK2 14
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK3 15
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_IPG 16
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK1 17
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK2 18
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK3 19
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_IPG 20
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK1 21
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK2 22
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK3 23
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_ASRC_IPG 24
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_IPG 25
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT 27
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SPBA2_ROOT 28
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_DSP_ROOT 29
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_DSPDBG_ROOT 30
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_IPG 31
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_OCRAMA_IPG 32
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_AUD2HTX_IPG 33
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_EDMA_ROOT 34
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_AUDPLL_ROOT 35
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_MU2_ROOT 36
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_MU3_ROOT 37
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_PHY 38
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_ROOT 39
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1_SEL 40
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK2_SEL 41
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK1_SEL 42
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK2_SEL 43
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1_SEL 44
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK2_SEL 45
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI4_MCLK1_SEL 46
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI4_MCLK2_SEL 47
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1_SEL 48
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK2_SEL 49
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK1_SEL 50
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK2_SEL 51
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK1_SEL 52
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK2_SEL 53
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_SEL 54
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_REF_SEL 55
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL 56
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_BYPASS 57
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_OUT 58
+
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_END 59
+
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_APB_CLK 0
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_B_CLK 1
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_REF266M_CLK 2
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL24M_CLK 3
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL32K_CLK 4
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_TX_PIX_CLK 5
+#define IMX8MP_CLK_HDMI_BLK_CTRL_IRQS_STEER_CLK 6
+#define IMX8MP_CLK_HDMI_BLK_CTRL_NOC_HDMI_CLK 7
+#define IMX8MP_CLK_HDMI_BLK_CTRL_NOC_HDCP_CLK 8
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_APB_CLK 9
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_B_CLK 10
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PDI_CLK 11
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PIX_CLK 12
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_SPU_CLK 13
+#define IMX8MP_CLK_HDMI_BLK_CTRL_FDCC_REF_CLK 14
+#define IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_APB_CLK 15
+#define IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_B_CLK 16
+#define IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_CEA_CLK 17
+#define IMX8MP_CLK_HDMI_BLK_CTRL_VSFD_CEA_CLK 18
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_HPI_CLK 19
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_APB_CLK 20
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_CEC_CLK 21
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_ESM_CLK 22
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_GPA_CLK 23
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIXEL_CLK 24
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_SFR_CLK 25
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_SKP_CLK 26
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PREP_CLK 27
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_APB_CLK 28
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_INT_CLK 29
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_SEC_MEM_CLK 30
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_TRNG_SKP_CLK 31
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_VID_LINK_PIX_CLK 32
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_TRNG_APB_CLK 33
+#define IMX8MP_CLK_HDMI_BLK_CTRL_HTXPHY_CLK_SEL 34
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_CLK_SEL 35
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIPE_CLK_SEL 36
+
+#define IMX8MP_CLK_HDMI_BLK_CTRL_END 37
+
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_PCLK 0
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_CLKREF 1
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_PCLK 2
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_ACLK 3
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_PIXEL 4
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_APB 5
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_PROC 6
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_APB 7
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_BUS_BLK 8
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_PCLK 9
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_ACLK 10
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_PIXEL 11
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_APB 12
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_COR 13
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AXI 14
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AHB 15
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_COR 16
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AXI 17
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AHB 18
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_COR 19
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AXI 20
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AHB 21
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI2 22
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_AXI 23
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_AXI 24
+
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_END 25
#endif
diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h
new file mode 100644
index 0000000000..113a9a0e83
--- /dev/null
+++ b/include/dt-bindings/reset/imx8mp-reset.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef DT_BINDING_RESET_IMX8MP_H
+#define DT_BINDING_RESET_IMX8MP_H
+
+#define IMX8MP_RESET_A53_CORE_POR_RESET0 0
+#define IMX8MP_RESET_A53_CORE_POR_RESET1 1
+#define IMX8MP_RESET_A53_CORE_POR_RESET2 2
+#define IMX8MP_RESET_A53_CORE_POR_RESET3 3
+#define IMX8MP_RESET_A53_CORE_RESET0 4
+#define IMX8MP_RESET_A53_CORE_RESET1 5
+#define IMX8MP_RESET_A53_CORE_RESET2 6
+#define IMX8MP_RESET_A53_CORE_RESET3 7
+#define IMX8MP_RESET_A53_DBG_RESET0 8
+#define IMX8MP_RESET_A53_DBG_RESET1 9
+#define IMX8MP_RESET_A53_DBG_RESET2 10
+#define IMX8MP_RESET_A53_DBG_RESET3 11
+#define IMX8MP_RESET_A53_ETM_RESET0 12
+#define IMX8MP_RESET_A53_ETM_RESET1 13
+#define IMX8MP_RESET_A53_ETM_RESET2 14
+#define IMX8MP_RESET_A53_ETM_RESET3 15
+#define IMX8MP_RESET_A53_SOC_DBG_RESET 16
+#define IMX8MP_RESET_A53_L2RESET 17
+#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18
+#define IMX8MP_RESET_OTG1_PHY_RESET 19
+#define IMX8MP_RESET_OTG2_PHY_RESET 20
+#define IMX8MP_RESET_SUPERMIX_RESET 21
+#define IMX8MP_RESET_AUDIOMIX_RESET 22
+#define IMX8MP_RESET_MLMIX_RESET 23
+#define IMX8MP_RESET_PCIEPHY 24
+#define IMX8MP_RESET_PCIEPHY_PERST 25
+#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26
+#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27
+#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28
+#define IMX8MP_RESET_MEDIA_RESET 29
+#define IMX8MP_RESET_GPU2D_RESET 30
+#define IMX8MP_RESET_GPU3D_RESET 31
+#define IMX8MP_RESET_GPU_RESET 32
+#define IMX8MP_RESET_VPU_RESET 33
+#define IMX8MP_RESET_VPU_G1_RESET 34
+#define IMX8MP_RESET_VPU_G2_RESET 35
+#define IMX8MP_RESET_VPUVC8KE_RESET 36
+#define IMX8MP_RESET_NOC_RESET 37
+#define IMX8MP_RESET_PCIE_CTRL_APPS_CLK_REQ 38
+
+#define IMX8MP_RESET_NUM 39
+
+#define IMX8MP_AUDIO_BLK_CTRL_EARC_RESET 0
+#define IMX8MP_AUDIO_BLK_CTRL_EARC_PHY_RESET 1
+
+#define IMX8MP_AUDIO_BLK_CTRL_RESET_NUM 2
+
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI_PCLK 0
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI_CLKREF 1
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI_PCLK 2
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI_ACLK 3
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_PIXEL 4
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_APB 5
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_PROC 6
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_APB 7
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_BUS_BLK 8
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI2_PCLK 9
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI2_ACLK 10
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_PIXEL 11
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_APB 12
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_COR 13
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_AXI 14
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_AHB 15
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_COR 16
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_AXI 17
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_AHB 18
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_COR 19
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_AXI 20
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_AHB 21
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI2 22
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_AXI 23
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_AXI 24
+
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_NUM 25
+
+#define IMX8MP_HDMI_BLK_CTRL_HDMI_TX_RESET 0
+#define IMX8MP_HDMI_BLK_CTRL_HDMI_PHY_RESET 1
+#define IMX8MP_HDMI_BLK_CTRL_HDMI_PAI_RESET 2
+#define IMX8MP_HDMI_BLK_CTRL_HDMI_PVI_RESET 3
+#define IMX8MP_HDMI_BLK_CTRL_HDMI_TRNG_RESET 4
+#define IMX8MP_HDMI_BLK_CTRL_IRQ_STEER_RESET 5
+#define IMX8MP_HDMI_BLK_CTRL_HDMI_HDCP_RESET 6
+#define IMX8MP_HDMI_BLK_CTRL_LCDIF_RESET 7
+
+#define IMX8MP_HDMI_BLK_CTRL_RESET_NUM 8
+
+
+#endif
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-30 08:01:09 +0000