diff options
| -rw-r--r-- | arch/arm/include/asm/mach-imx/regs-bch.h | 7 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/mxs_nand.c | 18 |
2 files changed, 23 insertions, 2 deletions
diff --git a/arch/arm/include/asm/mach-imx/regs-bch.h b/arch/arm/include/asm/mach-imx/regs-bch.h index 39ac5f4d450..3c1abb7221c 100644 --- a/arch/arm/include/asm/mach-imx/regs-bch.h +++ b/arch/arm/include/asm/mach-imx/regs-bch.h @@ -6,7 +6,8 @@ * on behalf of DENX Software Engineering GmbH * * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2010, 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * */ #ifndef __MX28_REGS_BCH_H__ @@ -40,6 +41,7 @@ struct mxs_bch_regs { mxs_reg_32(hw_bch_dbgahbmread) mxs_reg_32(hw_bch_blockname) mxs_reg_32(hw_bch_version) + mxs_reg_32(hw_bch_debug1) }; #endif @@ -75,6 +77,9 @@ struct mxs_bch_regs { #define BCH_MODE_ERASE_THRESHOLD_MASK 0xff #define BCH_MODE_ERASE_THRESHOLD_OFFSET 0 +#define BCH_MODE_ERASE_THRESHOLD(v) \ + (((v) << BCH_MODE_ERASE_THRESHOLD_OFFSET) & \ + BCH_MODE_ERASE_THRESHOLD_MASK) #define BCH_ENCODEPTR_ADDR_MASK 0xffffffff #define BCH_ENCODEPTR_ADDR_OFFSET 0 diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 55d24cd0620..2ac06a57306 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -10,6 +10,7 @@ * * Copyright (C) 2010 Freescale Semiconductor, Inc. * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * Copyright 2017-2019 NXP */ #include <common.h> @@ -660,11 +661,13 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, { struct mxs_nand_info *nand_info = nand_get_controller_data(nand); struct bch_geometry *geo = &nand_info->bch_geometry; + struct mxs_bch_regs *bch_regs = nand_info->bch_regs; struct mxs_dma_desc *d; uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; uint32_t corrected = 0, failed = 0; uint8_t *status; int i, ret; + int flag = 0; /* Compile the DMA descriptor - wait for ready. */ d = mxs_nand_get_dma_desc(nand_info); @@ -768,8 +771,13 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, if (status[i] == 0x00) continue; - if (status[i] == 0xff) + if (status[i] == 0xff) { + if (is_mx6dqp() || is_mx7() || + is_mx6ul()) + if (readl(&bch_regs->hw_bch_debug1)) + flag = 1; continue; + } if (status[i] == 0xfe) { if (mxs_nand_erased_page(mtd, nand, @@ -801,6 +809,8 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, memcpy(buf, nand_info->data_buf, mtd->writesize); + if (flag) + memset(buf, 0xff, mtd->writesize); rtn: mxs_nand_return_dma_descs(nand_info); @@ -1160,6 +1170,12 @@ int mxs_nand_setup_ecc(struct mtd_info *mtd) writel(tmp, &bch_regs->hw_bch_flash0layout1); nand_info->bch_flash0layout1 = tmp; + /* Set erase threshold to ecc strength for mx6ul, mx6qp and mx7 */ + if (is_mx6dqp() || is_mx7() || + is_mx6ul()) + writel(BCH_MODE_ERASE_THRESHOLD(geo->ecc_strength), + &bch_regs->hw_bch_mode); + /* Set *all* chip selects to use layout 0 */ writel(0, &bch_regs->hw_bch_layoutselect); |