diff options
63 files changed, 2094 insertions, 588 deletions
diff --git a/.travis.yml b/.travis.yml index e4e7e653f6..6662ca126a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -50,6 +50,7 @@ install: - . /tmp/venv/bin/activate - pip install pytest==2.8.7 - pip install python-subunit + - pip install pyelftools - grub-mkimage -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - grub-mkimage -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - mkdir ~/grub2-arm @@ -250,7 +250,7 @@ config BUILD_TARGET default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5 default "u-boot-spl.kwb" if ARCH_MVEBU && SPL default "u-boot-elf.srec" if RCAR_GEN3 - default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI + default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || ARCH_SUNXI) default "u-boot.kwb" if KIRKWOOD default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT help @@ -1847,7 +1847,8 @@ clean: $(clean-dirs) -o -name modules.builtin -o -name '.tmp_*.o.*' \ -o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \ -o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \ - -type f -print | xargs rm -f + -type f -print | xargs rm -f \ + bl31.c bl31.elf bl31_*.bin image.map # mrproper - Delete all generated files, including .config # diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4dfc2c6309..7fbd0a1d06 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -93,7 +93,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-vyasa.dtb dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb + rk3328-evb.dtb \ + rk3328-rock64.dtb dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-lion.dtb \ @@ -536,7 +537,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ vf610-bk4r1.dtb dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \ - imx53-kp.dtb + imx53-kp.dtb \ + imx53-m53menlo.dtb dtb-$(CONFIG_MX6Q) += \ imx6-apalis.dtb \ diff --git a/arch/arm/dts/imx53-m53.dtsi b/arch/arm/dts/imx53-m53.dtsi new file mode 100644 index 0000000000..fe5e0d308e --- /dev/null +++ b/arch/arm/dts/imx53-m53.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 Marek Vasut <marex@denx.de> + */ + +#include "imx53.dtsi" + +/ { + model = "Aries/DENX M53"; + compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53"; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x20000000>, + <0xb0000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p2v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + + reg_backlight: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "lcd-supply"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; + + touchscreen@41 { + compatible = "st,stmpe610"; + reg = <0x41>; + id = <0>; + blocks = <0x5>; + interrupts = <6 0x0>; + interrupt-parent = <&gpio7>; + irq-trigger = <0x1>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <3>; + st,touch-det-delay = <3>; + st,settling = <4>; + st,fraction-z = <7>; + st,i-drive = <1>; + }; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@68 { + compatible = "st,m41t62"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-m53evk { + pinctrl_hog: hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 + MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 + MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 + >; + }; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + status = "okay"; +}; diff --git a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi new file mode 100644 index 0000000000..329fa3b5e2 --- /dev/null +++ b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marek Vasut <marex@denx.de> + */ + +/ { + soc { + u-boot,dm-pre-reloc; + + aips@50000000 { + u-boot,dm-pre-reloc; + }; + }; +}; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&gpio2 { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio4 { + u-boot,dm-pre-reloc; +}; + +&gpio5 { + u-boot,dm-pre-reloc; +}; + +&gpio6 { + u-boot,dm-pre-reloc; +}; + +&gpio7 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx53-m53menlo.dts b/arch/arm/dts/imx53-m53menlo.dts new file mode 100644 index 0000000000..a6805eca9d --- /dev/null +++ b/arch/arm/dts/imx53-m53menlo.dts @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marek Vasut <marex@denx.de> + */ + +/dts-v1/; +#include "imx53-m53.dtsi" +#include "imx53-m53menlo-u-boot.dtsi" + +/ { + model = "MENLO M53 EMBEDDED DEVICE"; + compatible = "menlo,m53menlo", "fsl,imx53"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + user1 { + label = "TestLed601"; + gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + user2 { + label = "TestLed602"; + gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + eth { + label = "EthLedYe"; + gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + }; + + panel { + compatible = "edt,etm070080dh6"; + enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>, + <&clks IMX5_CLK_CKO1_PODF>, + <&clks IMX5_CLK_CKO1>; + assigned-clock-parents = <&clks IMX5_CLK_AHB>; + assigned-clock-rates = <133333334>, <33333334>, <33333334>; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06>; + interrupt-parent = <&gpio6>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + dac@60 { + compatible = "microchip,mcp4725"; + reg = <0x60>; + }; +}; + +&i2c2 { + touchscreen@41 { + status = "disabled"; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-m53evk { + hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 + MX53_PAD_EIM_EB3__GPIO2_31 0x1d5 + MX53_PAD_PATA_DA_0__GPIO7_6 0x1d5 + MX53_PAD_GPIO_19__CCM_CLKO 0x1d5 + MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x1d5 + MX53_PAD_CSI0_DAT4__GPIO5_22 0x1d5 + MX53_PAD_CSI0_DAT5__GPIO5_23 0x1d5 + MX53_PAD_CSI0_DAT6__GPIO5_24 0x1d5 + MX53_PAD_CSI0_DAT7__GPIO5_25 0x1d5 + MX53_PAD_CSI0_DAT8__GPIO5_26 0x1d5 + MX53_PAD_CSI0_DAT9__GPIO5_27 0x1d5 + MX53_PAD_CSI0_DAT10__GPIO5_28 0x1d5 + MX53_PAD_CSI0_DAT11__GPIO5_29 0x1d5 + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1d5 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX53_PAD_CSI0_DAT15__GPIO6_1 0x1d5 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1d5 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4 + MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1c4 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4 + >; + }; + + pinctrl_display_gpio: display-gpiogrp { + fsl,pins = < + MX53_PAD_CSI0_DAT12__GPIO5_30 0x1d5 /* Reset */ + MX53_PAD_CSI0_DAT13__GPIO5_31 0x1d5 /* Interrupt */ + >; + }; + + pinctrl_edt_ft5x06: edt-ft5x06grp { + fsl,pins = < + MX53_PAD_PATA_DATA9__GPIO2_9 0x1d5 /* Reset */ + MX53_PAD_CSI0_DAT19__GPIO6_5 0x1d5 /* Interrupt */ + MX53_PAD_PATA_DATA10__GPIO2_10 0x1d5 /* Wake */ + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x4 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 + MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4 + >; + }; + + pinctrl_lvds0: lvds0grp { + /* LVDS pins only have pin mux configuration */ + fsl,pins = < + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + >; + }; + + pinctrl_usb: usbgrp { + fsl,pins = < + MX53_PAD_GPIO_2__GPIO1_2 0x1d5 + MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1d5 + >; + }; + }; +}; + +&ldb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0>; + status = "okay"; + + lvds0: lvds-channel@0 { + reg = <0>; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@2 { + reg = <2>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb>; + vbus-supply = <®_usbh1_vbus>; + phy_type = "utmi"; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi index 211ff5f69e..ed341cfd9d 100644 --- a/arch/arm/dts/imx53.dtsi +++ b/arch/arm/dts/imx53.dtsi @@ -1,17 +1,8 @@ -/* - * Copyright 2016 Beckhoff Automation - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "skeleton.dtsi" +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2011 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + #include "imx53-pinfunc.h" #include <dt-bindings/clock/imx5-clock.h> #include <dt-bindings/gpio/gpio.h> @@ -19,8 +10,17 @@ #include <dt-bindings/interrupt-controller/irq.h> / { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + aliases { - serial1 = &uart2; + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -36,7 +36,45 @@ mmc1 = &esdhc2; mmc2 = &esdhc3; mmc3 = &esdhc4; - usb1 = &usbh1; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &cspi; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + clocks = <&clks IMX5_CLK_ARM>; + clock-latency = <61036>; + voltage-tolerance = <5>; + operating-points = < + /* kHz */ + 166666 850000 + 400000 900000 + 800000 1050000 + 1000000 1200000 + 1200000 1300000 + >; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&ipu_di0>, <&ipu_di1>; + }; + + capture_subsystem { + compatible = "fsl,imx-capture-subsystem"; + ports = <&ipu_csi0>, <&ipu_csi1>; }; tzic: tz-interrupt-controller@fffc000 { @@ -46,13 +84,143 @@ reg = <0x0fffc000 0x4000>; }; + clocks { + ckil { + compatible = "fsl,imx-ckil", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22579200>; + }; + + ckih2 { + compatible = "fsl,imx-ckih2", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + osc { + compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + pmu: pmu { + compatible = "arm,cortex-a8-pmu"; + interrupt-parent = <&tzic>; + interrupts = <77>; + }; + + usbphy0: usbphy-0 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + status = "okay"; + }; + + usbphy1: usbphy-1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + status = "okay"; + }; + soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&tzic>; ranges; - u-boot,dm-pre-reloc; + + sata: sata@10000000 { + compatible = "fsl,imx53-ahci"; + reg = <0x10000000 0x1000>; + interrupts = <28>; + clocks = <&clks IMX5_CLK_SATA_GATE>, + <&clks IMX5_CLK_SATA_REF>, + <&clks IMX5_CLK_AHB>; + clock-names = "sata", "sata_ref", "ahb"; + status = "disabled"; + }; + + ipu: ipu@18000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ipu"; + reg = <0x18000000 0x08000000>; + interrupts = <11 10>; + clocks = <&clks IMX5_CLK_IPU_GATE>, + <&clks IMX5_CLK_IPU_DI0_GATE>, + <&clks IMX5_CLK_IPU_DI1_GATE>; + clock-names = "bus", "di0", "di1"; + resets = <&src 2>; + + ipu_csi0: port@0 { + reg = <0>; + + ipu_csi0_from_parallel_sensor: endpoint { + }; + }; + + ipu_csi1: port@1 { + reg = <1>; + + ipu_csi1_from_parallel_sensor: endpoint { + }; + }; + + ipu_di0: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + ipu_di0_disp0: endpoint@0 { + reg = <0>; + }; + + ipu_di0_lvds0: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds0_in>; + }; + }; + + ipu_di1: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + ipu_di1_disp1: endpoint@0 { + reg = <0>; + }; + + ipu_di1_lvds1: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds1_in>; + }; + + ipu_di1_tve: endpoint@2 { + reg = <2>; + remote-endpoint = <&tve_in>; + }; + }; + }; + + gpu: gpu@30000000 { + compatible = "amd,imageon-200.0", "amd,imageon"; + reg = <0x30000000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <12>; + interrupt-names = "kgsl_3d0_irq"; + clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; + clock-names = "core_clk", "mem_iface_clk"; + }; aips@50000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; @@ -92,6 +260,47 @@ status = "disabled"; }; + uart3: serial@5000c000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + interrupts = <33>; + clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, + <&clks IMX5_CLK_UART3_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi1: spi@50010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + reg = <0x50010000 0x4000>; + interrupts = <36>; + clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, + <&clks IMX5_CLK_ECSPI1_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ssi2: ssi@50014000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx53-ssi", + "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x50014000 0x4000>; + interrupts = <30>; + clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, + <&clks IMX5_CLK_SSI2_ROOT_GATE>; + clock-names = "ipg", "baud"; + dmas = <&sdma 24 1 0>, + <&sdma 25 1 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; + esdhc3: esdhc@50020000 { compatible = "fsl,imx53-esdhc"; reg = <0x50020000 0x4000>; @@ -117,25 +326,18 @@ }; }; - iomuxc: iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc"; - reg = <0x53fa8000 0x4000>; - }; - - gpr: iomuxc-gpr@53fa8000 { - compatible = "fsl,imx53-iomuxc-gpr", "syscon"; - reg = <0x53fa8000 0xc>; + aipstz1: bridge@53f00000 { + compatible = "fsl,imx53-aipstz"; + reg = <0x53f00000 0x60>; }; - uart2: serial@53fc0000 { - compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart"; - reg = <0x53fc0000 0x4000>; - interrupts = <32>; - clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, - <&clks IMX5_CLK_UART2_PER_GATE>; - clock-names = "ipg", "per"; - dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; - dma-names = "rx", "tx"; + usbotg: usb@53f80000 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80000 0x0200>; + interrupts = <18>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -144,15 +346,37 @@ reg = <0x53f80200 0x0200>; interrupts = <14>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 1>; + fsl,usbphy = <&usbphy1>; dr_mode = "host"; status = "disabled"; }; - clks: ccm@53fd4000{ - compatible = "fsl,imx53-ccm"; - reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; - #clock-cells = <1>; + usbh2: usb@53f80400 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80400 0x0200>; + interrupts = <16>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 2>; + dr_mode = "host"; + status = "disabled"; + }; + + usbh3: usb@53f80600 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80600 0x0200>; + interrupts = <17>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbmisc = <&usbmisc 3>; + dr_mode = "host"; + status = "disabled"; + }; + + usbmisc: usbmisc@53f80800 { + #index-cells = <1>; + compatible = "fsl,imx53-usbmisc"; + reg = <0x53f80800 0x200>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; }; gpio1: gpio@53f84000 { @@ -195,6 +419,188 @@ #interrupt-cells = <2>; }; + kpp: kpp@53f94000 { + compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; + reg = <0x53f94000 0x4000>; + interrupts = <60>; + clocks = <&clks IMX5_CLK_DUMMY>; + status = "disabled"; + }; + + wdog1: wdog@53f98000 { + compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; + reg = <0x53f98000 0x4000>; + interrupts = <58>; + clocks = <&clks IMX5_CLK_DUMMY>; + }; + + wdog2: wdog@53f9c000 { + compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; + reg = <0x53f9c000 0x4000>; + interrupts = <59>; + clocks = <&clks IMX5_CLK_DUMMY>; + status = "disabled"; + }; + + gpt: timer@53fa0000 { + compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; + reg = <0x53fa0000 0x4000>; + interrupts = <39>; + clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, + <&clks IMX5_CLK_GPT_HF_GATE>; + clock-names = "ipg", "per"; + }; + + srtc: rtc@53fa4000 { + compatible = "fsl,imx53-rtc"; + reg = <0x53fa4000 0x4000>; + interrupts = <24>; + clocks = <&clks IMX5_CLK_SRTC_GATE>; + }; + + iomuxc: iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc"; + reg = <0x53fa8000 0x4000>; + }; + + gpr: iomuxc-gpr@53fa8000 { + compatible = "fsl,imx53-iomuxc-gpr", "syscon"; + reg = <0x53fa8000 0xc>; + }; + + ldb: ldb@53fa8008 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ldb"; + reg = <0x53fa8008 0x4>; + gpr = <&gpr>; + clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, + <&clks IMX5_CLK_LDB_DI1_SEL>, + <&clks IMX5_CLK_IPU_DI0_SEL>, + <&clks IMX5_CLK_IPU_DI1_SEL>, + <&clks IMX5_CLK_LDB_DI0_GATE>, + <&clks IMX5_CLK_LDB_DI1_GATE>; + clock-names = "di0_pll", "di1_pll", + "di0_sel", "di1_sel", + "di0", "di1"; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + + lvds0_in: endpoint { + remote-endpoint = <&ipu_di0_lvds0>; + }; + }; + + port@2 { + reg = <2>; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + status = "disabled"; + + port@1 { + reg = <1>; + + lvds1_in: endpoint { + remote-endpoint = <&ipu_di1_lvds1>; + }; + }; + + port@2 { + reg = <2>; + }; + }; + }; + + pwm1: pwm@53fb4000 { + #pwm-cells = <2>; + compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; + reg = <0x53fb4000 0x4000>; + clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, + <&clks IMX5_CLK_PWM1_HF_GATE>; + clock-names = "ipg", "per"; + interrupts = <61>; + }; + + pwm2: pwm@53fb8000 { + #pwm-cells = <2>; + compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; + reg = <0x53fb8000 0x4000>; + clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, + <&clks IMX5_CLK_PWM2_HF_GATE>; + clock-names = "ipg", "per"; + interrupts = <94>; + }; + + uart1: serial@53fbc000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fbc000 0x4000>; + interrupts = <31>; + clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, + <&clks IMX5_CLK_UART1_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@53fc0000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fc0000 0x4000>; + interrupts = <32>; + clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, + <&clks IMX5_CLK_UART2_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + can1: can@53fc8000 { + compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; + reg = <0x53fc8000 0x4000>; + interrupts = <82>; + clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, + <&clks IMX5_CLK_CAN1_SERIAL_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can2: can@53fcc000 { + compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; + reg = <0x53fcc000 0x4000>; + interrupts = <83>; + clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, + <&clks IMX5_CLK_CAN2_SERIAL_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + src: src@53fd0000 { + compatible = "fsl,imx53-src", "fsl,imx51-src"; + reg = <0x53fd0000 0x4000>; + #reset-cells = <1>; + }; + + clks: ccm@53fd4000{ + compatible = "fsl,imx53-ccm"; + reg = <0x53fd4000 0x4000>; + interrupts = <0 71 0x04 0 72 0x04>; + #clock-cells = <1>; + }; + gpio5: gpio@53fdc000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53fdc000 0x4000>; @@ -234,6 +640,18 @@ clocks = <&clks IMX5_CLK_I2C3_GATE>; status = "disabled"; }; + + uart4: serial@53ff0000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53ff0000 0x4000>; + interrupts = <13>; + clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, + <&clks IMX5_CLK_UART4_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; }; aips@60000000 { /* AIPS2 */ @@ -243,25 +661,74 @@ reg = <0x60000000 0x10000000>; ranges; + aipstz2: bridge@63f00000 { + compatible = "fsl,imx53-aipstz"; + reg = <0x63f00000 0x60>; + }; + + iim: iim@63f98000 { + compatible = "fsl,imx53-iim", "fsl,imx27-iim"; + reg = <0x63f98000 0x4000>; + interrupts = <69>; + clocks = <&clks IMX5_CLK_IIM_GATE>; + }; + + uart5: serial@63f90000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x63f90000 0x4000>; + interrupts = <86>; + clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, + <&clks IMX5_CLK_UART5_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + tigerp: tigerp@63fa0000 { + compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp"; + reg = <0x63fa0000 0x28>; + }; + + owire: owire@63fa4000 { + compatible = "fsl,imx53-owire", "fsl,imx21-owire"; + reg = <0x63fa4000 0x4000>; + clocks = <&clks IMX5_CLK_OWIRE_GATE>; + status = "disabled"; + }; + + ecspi2: spi@63fac000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + reg = <0x63fac000 0x4000>; + interrupts = <37>; + clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, + <&clks IMX5_CLK_ECSPI2_PER_GATE>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + sdma: sdma@63fb0000 { compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; + <&clks IMX5_CLK_AHB>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; }; - fec: ethernet@63fec000 { - compatible = "fsl,imx53-fec", "fsl,imx25-fec"; - reg = <0x63fec000 0x4000>; - interrupts = <87>; - clocks = <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>, - <&clks IMX5_CLK_FEC_GATE>; - clock-names = "ipg", "ahb", "ptp"; + cspi: spi@63fc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; + reg = <0x63fc0000 0x4000>; + interrupts = <38>; + clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, + <&clks IMX5_CLK_CSPI_IPG_GATE>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -284,66 +751,65 @@ clocks = <&clks IMX5_CLK_I2C1_GATE>; status = "disabled"; }; - }; - - ipu: ipu@18000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ipu"; - reg = <0x18000000 0x08000000>; - interrupts = <11 10>; - clocks = <&clks IMX5_CLK_IPU_GATE>, - <&clks IMX5_CLK_IPU_DI0_GATE>, - <&clks IMX5_CLK_IPU_DI1_GATE>; - clock-names = "bus", "di0", "di1"; - resets = <&src 2>; - u-boot,dm-pre-reloc; - ipu_csi0: port@0 { - reg = <0>; + ssi1: ssi@63fcc000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x63fcc000 0x4000>; + interrupts = <29>; + clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, + <&clks IMX5_CLK_SSI1_ROOT_GATE>; + clock-names = "ipg", "baud"; + dmas = <&sdma 28 0 0>, + <&sdma 29 0 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; }; - ipu_csi1: port@1 { - reg = <1>; + audmux: audmux@63fd0000 { + compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; + reg = <0x63fd0000 0x4000>; + status = "disabled"; }; - ipu_di0: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - ipu_di0_disp0: endpoint@0 { - reg = <0>; - }; - - ipu_di0_lvds0: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds0_in>; - }; + nfc: nand@63fdb000 { + compatible = "fsl,imx53-nand"; + reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; + interrupts = <8>; + clocks = <&clks IMX5_CLK_NFC_GATE>; + status = "disabled"; }; - ipu_di1: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - ipu_di1_disp1: endpoint@0 { - reg = <0>; - }; - - ipu_di1_lvds1: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds1_in>; - }; + ssi3: ssi@63fe8000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", + "fsl,imx21-ssi"; + reg = <0x63fe8000 0x4000>; + interrupts = <96>; + clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, + <&clks IMX5_CLK_SSI3_ROOT_GATE>; + clock-names = "ipg", "baud"; + dmas = <&sdma 46 0 0>, + <&sdma 47 0 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + status = "disabled"; + }; - ipu_di1_tve: endpoint@2 { - reg = <2>; - remote-endpoint = <&tve_in>; - }; + fec: ethernet@63fec000 { + compatible = "fsl,imx53-fec", "fsl,imx25-fec"; + reg = <0x63fec000 0x4000>; + interrupts = <87>; + clocks = <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; }; - }; - tve: tve@63ff0000 { + tve: tve@63ff0000 { compatible = "fsl,imx53-tve"; reg = <0x63ff0000 0x1000>; interrupts = <92>; @@ -357,68 +823,33 @@ remote-endpoint = <&ipu_di1_tve>; }; }; - }; - - src: src@53fd0000 { - compatible = "fsl,imx53-src", "fsl,imx51-src"; - reg = <0x53fd0000 0x4000>; - #reset-cells = <1>; - }; - - ldb: ldb@53fa8008 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx53-ldb"; - reg = <0x53fa8008 0x4>; - gpr = <&gpr>; - clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, - <&clks IMX5_CLK_LDB_DI1_SEL>, - <&clks IMX5_CLK_IPU_DI0_SEL>, - <&clks IMX5_CLK_IPU_DI1_SEL>, - <&clks IMX5_CLK_LDB_DI0_GATE>, - <&clks IMX5_CLK_LDB_DI1_GATE>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", - "di0", "di1"; - status = "disabled"; - - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds0_in: endpoint { - remote-endpoint = <&ipu_di0_lvds0>; - }; - }; - - port@2 { - reg = <2>; - }; - }; - - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - status = "disabled"; + }; - port@1 { - reg = <1>; + vpu: vpu@63ff4000 { + compatible = "fsl,imx53-vpu", "cnm,coda7541"; + reg = <0x63ff4000 0x1000>; + interrupts = <9>; + clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, + <&clks IMX5_CLK_VPU_GATE>; + clock-names = "per", "ahb"; + resets = <&src 1>; + iram = <&ocram>; + }; - lvds1_in: endpoint { - remote-endpoint = <&ipu_di1_lvds1>; - }; - }; + sahara: crypto@63ff8000 { + compatible = "fsl,imx53-sahara"; + reg = <0x63ff8000 0x4000>; + interrupts = <19 20>; + clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, + <&clks IMX5_CLK_SAHARA_IPG_GATE>; + clock-names = "ipg", "ahb"; + }; + }; - port@2 { - reg = <2>; - }; - }; + ocram: sram@f8000000 { + compatible = "mmio-sram"; + reg = <0xf8000000 0x20000>; + clocks = <&clks IMX5_CLK_OCRAM>; }; }; }; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi new file mode 100644 index 0000000000..b077436cbc --- /dev/null +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts new file mode 100644 index 0000000000..7bcc53fcce --- /dev/null +++ b/arch/arm/dts/rk3328-rock64.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 PINE64 + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Pine64 Rock64"; + compatible = "pine64,rock64", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_host_5v: vcc-host-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_host_drv>; + regulator-name = "vcc_host_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_io>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,force_thresh_dma_mode; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x24>; + rx_delay = <0x18>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vdd_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb3 { + usb30_host_drv: usb30-host-drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spiflash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + /* maximum speed for Rockchip SPI */ + spi-max-frequency = <50000000>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index ca0fc391b2..0e2e047180 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -629,7 +629,6 @@ ap_i2c_audio: &i2c8 { &uart2 { status = "okay"; - u-boot,dm-pre-reloc; }; &usb_host0_ohci { diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 897e0bda85..74368da550 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -639,7 +639,6 @@ }; &uart0 { - u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts>; status = "okay"; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 0786c1193a..fcfce9ae02 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -10,3 +10,11 @@ &spi1 { u-boot,dm-pre-reloc; }; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index ade7285786..d8f9d8dc5f 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -78,10 +78,6 @@ }; }; -&clk_hse { - u-boot,dm-pre-reloc; -}; - &fmc { /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ bank1: bank@0 { @@ -123,9 +119,7 @@ }; fmc_pins: fmc@0 { - u-boot,dm-pre-reloc; pins { - u-boot,dm-pre-reloc; pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */ <STM32_PINMUX('D', 9, AF12)>, /* D14 */ <STM32_PINMUX('D', 8, AF12)>, /* D13 */ diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index 53a645dace..209a82c9cf 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -152,6 +152,16 @@ slew-rate = <2>; }; }; + + usart1_pins_a: usart1@0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; + }; }; &qspi { diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index d42a15e877..24d16299e8 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -17,7 +17,7 @@ #define ALIGN_SIZE 0x1000 #define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8 #define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0 -#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18 +#define MX6SL_PU_IROM_MMU_EN_VAR 0x00901c60 #define IS_HAB_ENABLED_BIT \ (is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \ (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c05e3c3f48..1624b084b9 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -109,6 +109,13 @@ endif config ROCKCHIP_RK3328 bool "Support Rockchip RK3328" select ARM64 + select SUPPORT_SPL + select SPL + imply SPL_SERIAL_SUPPORT + imply SPL_SEPARATE_BSS + select ENABLE_ARM_SOC_BOOT0_HOOK + select DEBUG_UART_BOARD_INIT + select SYS_NS16550 help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two @@ -158,6 +165,7 @@ config ROCKCHIP_RK3399 select SPL select SPL_ATF select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + select SPL_BOARD_INIT if SPL select SPL_LOAD_FIT select SPL_CLK if SPL select SPL_PINCTRL if SPL @@ -183,6 +191,7 @@ config ROCKCHIP_RK3399 imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT imply TPL_SYS_MALLOC_SIMPLE + imply TPL_BOARD_INIT imply TPL_BOOTROM_SUPPORT imply TPL_DRIVERS_MISC_SUPPORT imply TPL_OF_CONTROL diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 846c82d70a..23760a959a 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -18,6 +18,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3328) += rk3328-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py index 212bd0a854..45ec105887 100755 --- a/arch/arm/mach-rockchip/make_fit_atf.py +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -12,6 +12,7 @@ import os import sys import getopt +import logging # pip install pyelftools from elftools.elf.elffile import ELFFile @@ -89,13 +90,17 @@ def append_conf_section(file, cnt, dtname, segments): file.write('\t\tconfig_%d {\n' % cnt) file.write('\t\t\tdescription = "%s";\n' % dtname) file.write('\t\t\tfirmware = "atf_1";\n') - file.write('\t\t\tloadables = "uboot",') + file.write('\t\t\tloadables = "uboot"') + if segments != 0: + file.write(',') for i in range(1, segments): file.write('"atf_%d"' % (i)) if i != (segments - 1): file.write(',') else: file.write(';\n') + if segments == 0: + file.write(';\n') file.write('\t\t\tfdt = "fdt_1";\n') file.write('\t\t};\n') file.write('\n') @@ -171,8 +176,18 @@ def generate_atf_binary(bl31_file_name): def main(): uboot_elf = "./u-boot" - bl31_elf = "./bl31.elf" fit_its = sys.stdout + if "BL31" in os.environ: + bl31_elf=os.getenv("BL31"); + elif os.path.isfile("./bl31.elf"): + bl31_elf = "./bl31.elf" + else: + os.system("echo 'int main(){}' > bl31.c") + os.system("${CROSS_COMPILE}gcc -c bl31.c -o bl31.elf") + bl31_elf = "./bl31.elf" + logging.basicConfig(format='%(levelname)s:%(message)s', level=logging.DEBUG) + logging.warning(' BL31 file bl31.elf NOT found, resulting binary is non-functional') + logging.warning(' Please read Building section in doc/README.rockchip') opts, args = getopt.getopt(sys.argv[1:], "o:u:b:h") for opt, val in opts: diff --git a/arch/arm/mach-rockchip/rk3328-board-spl.c b/arch/arm/mach-rockchip/rk3328-board-spl.c new file mode 100644 index 0000000000..7f49d056a0 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328-board-spl.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_debug_uart_init(void) +{ +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 800ca80022..890d80025f 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -11,13 +11,16 @@ #include <spl.h> #include <spl_gpio.h> #include <syscon.h> +#include <asm/gpio.h> #include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3399.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/periph.h> #include <asm/arch-rockchip/sys_proto.h> +#include <power/regulator.h> #include <dm/pinctrl.h> void board_return_to_bootrom(void) @@ -161,7 +164,7 @@ void board_init_f(ulong dummy) * printhex8(0x1234); * printascii("string"); */ - printascii("U-Boot SPL board init\n"); + debug("U-Boot SPL board init\n"); #endif ret = spl_early_init(); @@ -202,6 +205,66 @@ void board_init_f(ulong dummy) } } +#if defined(SPL_GPIO_SUPPORT) +static void rk3399_force_power_on_reset(void) +{ + ofnode node; + struct gpio_desc sysreset_gpio; + + debug("%s: trying to force a power-on reset\n", __func__); + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) { + debug("%s: no /config node?\n", __func__); + return; + } + + if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, + &sysreset_gpio, GPIOD_IS_OUT)) { + debug("%s: could not find a /config/sysreset-gpio\n", __func__); + return; + } + + dm_gpio_set_value(&sysreset_gpio, 1); +} +#endif + +void spl_board_init(void) +{ +#if defined(SPL_GPIO_SUPPORT) + struct rk3399_cru *cru = rockchip_get_cru(); + + /* + * The RK3399 resets only 'almost all logic' (see also in the TRM + * "3.9.4 Global software reset"), when issuing a software reset. + * This may cause issues during boot-up for some configurations of + * the application software stack. + * + * To work around this, we test whether the last reset reason was + * a power-on reset and (if not) issue an overtemp-reset to reset + * the entire module. + * + * While this was previously fixed by modifying the various places + * that could generate a software reset (e.g. U-Boot's sysreset + * driver, the ATF or Linux), we now have it here to ensure that + * we no longer have to track this through the various components. + */ + if (cru->glb_rst_st != 0) + rk3399_force_power_on_reset(); +#endif + +#if defined(SPL_DM_REGULATOR) + /* + * Turning the eMMC and SPI back on (if disabled via the Qseven + * BIOS_ENABLE) signal is done through a always-on regulator). + */ + if (regulators_enable_boot_on(false)) + debug("%s: Cannot enable boot on regulator\n", __func__); +#endif + + preloader_console_init(); +} + #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/arch/arm/mach-rockchip/rk3399-board-tpl.c b/arch/arm/mach-rockchip/rk3399-board-tpl.c index 86d3ffe97c..4a301249b4 100644 --- a/arch/arm/mach-rockchip/rk3399-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3399-board-tpl.c @@ -8,6 +8,7 @@ #include <dm.h> #include <ram.h> #include <spl.h> +#include <version.h> #include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> @@ -46,7 +47,7 @@ void board_init_f(ulong dummy) * printhex8(0x1234); * printascii("string"); */ - printascii("U-Boot TPL board init\n"); + debug("U-Boot TPL board init\n"); #endif ret = spl_early_init(); if (ret) { @@ -73,6 +74,12 @@ u32 spl_boot_device(void) return BOOT_DEVICE_BOOTROM; } +void spl_board_init(void) +{ + puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " + U_BOOT_TIME " " U_BOOT_TZ ")\n"); +} + #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/arch/arm/mach-stm32/soc.c b/arch/arm/mach-stm32/soc.c index 6ae31d3a1f..41338a1a33 100644 --- a/arch/arm/mach-stm32/soc.c +++ b/arch/arm/mach-stm32/soc.c @@ -18,7 +18,7 @@ int arch_cpu_init(void) */ #if defined(CONFIG_STM32F4) { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, - O_I_WB_RD_WR_ALLOC, REGION_16MB }, + O_I_WB_RD_WR_ALLOC, REGION_512MB }, #endif { 0x90000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, diff --git a/arch/arm/mach-uniphier/arm32/debug_ll.S b/arch/arm/mach-uniphier/arm32/debug_ll.S index 9fe3eaadf1..e56e1f679c 100644 --- a/arch/arm/mach-uniphier/arm32/debug_ll.S +++ b/arch/arm/mach-uniphier/arm32/debug_ll.S @@ -16,9 +16,19 @@ #include CONFIG_DEBUG_LL_INCLUDE #endif +#define SG_REVISION_TYPE_SHIFT 16 +#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT) #define BAUDRATE 115200 #define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d)) +.macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd + ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride) + ldr \rd, [\ra] + and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32)) + orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32)) + str \rd, [\ra] +.endm + ENTRY(debug_ll_init) ldr r0, =SG_REVISION ldr r1, [r0] diff --git a/arch/arm/mach-uniphier/debug-uart/Makefile b/arch/arm/mach-uniphier/debug-uart/Makefile index 5d78db58cb..81e9314a50 100644 --- a/arch/arm/mach-uniphier/debug-uart/Makefile +++ b/arch/arm/mach-uniphier/debug-uart/Makefile @@ -7,8 +7,6 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += debug-uart-sld8.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += debug-uart-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += debug-uart-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += debug-uart-ld6b.o -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += debug-uart-ld20.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += debug-uart-ld20.o endif obj-y += debug-uart.o diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-ld20.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-ld20.c deleted file mode 100644 index b742feb4b0..0000000000 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart-ld20.c +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> - */ - -#include <config.h> -#include <linux/kernel.h> -#include <linux/io.h> - -#include "../sc64-regs.h" -#include "../sg-regs.h" -#include "debug-uart.h" - -#define UNIPHIER_LD20_UART_CLK 58820000 - -unsigned int uniphier_ld20_debug_uart_init(void) -{ - u32 tmp; - - sg_set_iectrl(54); /* TXD0 */ - sg_set_iectrl(58); /* TXD1 */ - sg_set_iectrl(90); /* TXD2 */ - sg_set_iectrl(94); /* TXD3 */ - sg_set_pinsel(54, 0, 8, 4); /* TXD0 -> TXD0 */ - sg_set_pinsel(58, 1, 8, 4); /* SPITXD1 -> TXD1 */ - sg_set_pinsel(90, 1, 8, 4); /* PC0WE -> TXD2 */ - sg_set_pinsel(94, 1, 8, 4); /* PCD00 -> TXD3 */ - - tmp = readl(SC_CLKCTRL4); - tmp |= SC_CLKCTRL4_PERI; - writel(tmp, SC_CLKCTRL4); - - return DIV_ROUND_CLOSEST(UNIPHIER_LD20_UART_CLK, 16 * CONFIG_BAUDRATE); -} diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c index 992b4a9857..bc96b2e7be 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c @@ -8,6 +8,7 @@ #include <linux/io.h> #include <linux/serial_reg.h> +#include "../sg-regs.h" #include "../soc-info.h" #include "debug-uart.h" @@ -26,8 +27,36 @@ static void _debug_uart_putc(int c) writel(c, base + UNIPHIER_UART_TX); } +#ifdef CONFIG_SPL_BUILD +void sg_set_pinsel(unsigned int pin, unsigned int muxval, + unsigned int mux_bits, unsigned int reg_stride) +{ + unsigned int shift = pin * mux_bits % 32; + unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride; + u32 mask = (1U << mux_bits) - 1; + u32 tmp; + + tmp = readl(reg); + tmp &= ~(mask << shift); + tmp |= (mask & muxval) << shift; + writel(tmp, reg); +} + +void sg_set_iectrl(unsigned int pin) +{ + unsigned int bit = pin % 32; + unsigned long reg = SG_IECTRL + pin / 32 * 4; + u32 tmp; + + tmp = readl(reg); + tmp |= 1 << bit; + writel(tmp, reg); +} +#endif + void _debug_uart_init(void) { +#ifdef CONFIG_SPL_BUILD void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; unsigned int divisor; @@ -62,12 +91,6 @@ void _debug_uart_init(void) divisor = uniphier_ld6b_debug_uart_init(); break; #endif -#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) - case UNIPHIER_LD11_ID: - case UNIPHIER_LD20_ID: - divisor = uniphier_ld20_debug_uart_init(); - break; -#endif default: return; } @@ -75,5 +98,6 @@ void _debug_uart_init(void) writel(UART_LCR_WLEN8 << 8, base + UNIPHIER_UART_LCR_MCR); writel(divisor, base + UNIPHIER_UART_LDR); +#endif } DEBUG_UART_FUNCS diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.h b/arch/arm/mach-uniphier/debug-uart/debug-uart.h index 4cbd2f08e7..f4e98c0bb0 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart.h +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.h @@ -12,7 +12,9 @@ unsigned int uniphier_sld8_debug_uart_init(void); unsigned int uniphier_pro5_debug_uart_init(void); unsigned int uniphier_pxs2_debug_uart_init(void); unsigned int uniphier_ld6b_debug_uart_init(void); -unsigned int uniphier_ld11_debug_uart_init(void); -unsigned int uniphier_ld20_debug_uart_init(void); + +void sg_set_pinsel(unsigned int pin, unsigned int muxval, + unsigned int mux_bits, unsigned int reg_stride); +void sg_set_iectrl(unsigned int pin); #endif /* _MACH_DEBUG_UART_H */ diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 7e7c1d98db..fa4b3e386b 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -7,6 +7,7 @@ #include <common.h> #include <linux/errno.h> +#include <linux/io.h> #include <linux/kernel.h> #include <linux/printk.h> #include <linux/sizes.h> diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h index b105335f69..28de19c039 100644 --- a/arch/arm/mach-uniphier/sc-regs.h +++ b/arch/arm/mach-uniphier/sc-regs.h @@ -12,10 +12,6 @@ #define SC_BASE_ADDR 0x61840000 -#define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110) -#define SC_DPLLOSCCTRL_DPLLST (0x1 << 1) -#define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0) - #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200) #define SC_DPLLCTRL_SSC_EN (0x1 << 31) #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16) diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 0497655fb5..39ffed5885 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -87,54 +87,4 @@ #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16) #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16) -#ifdef __ASSEMBLY__ - - .macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd - ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride) - ldr \rd, [\ra] - and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32)) - orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32)) - str \rd, [\ra] - .endm - -#else - -#include <linux/types.h> -#include <linux/io.h> - -static inline void sg_set_pinsel(unsigned pin, unsigned muxval, - unsigned mux_bits, unsigned reg_stride) -{ - unsigned shift = pin * mux_bits % 32; - unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride; - u32 mask = (1U << mux_bits) - 1; - u32 tmp; - - tmp = readl(reg); - tmp &= ~(mask << shift); - tmp |= (mask & muxval) << shift; - writel(tmp, reg); -} - -static inline void sg_set_iectrl(unsigned pin) -{ - unsigned bit = pin % 32; - unsigned long reg = SG_IECTRL + pin / 32 * 4; - u32 tmp; - - tmp = readl(reg); - tmp |= 1 << bit; - writel(tmp, reg); -} - -static inline void sg_set_iectrl_range(unsigned min, unsigned max) -{ - int i; - - for (i = min; i <= max; i++) - sg_set_iectrl(i); -} - -#endif /* __ASSEMBLY__ */ - #endif /* UNIPHIER_SG_REGS_H */ diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c index 6bdd6d5b23..31ba44e452 100644 --- a/board/menlo/m53menlo/m53menlo.c +++ b/board/menlo/m53menlo/m53menlo.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <dm.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> @@ -28,6 +29,7 @@ #include <spl.h> #include <splash.h> #include <usb/ehci-ci.h> +#include <video_console.h> DECLARE_GLOBAL_DATA_PTR; @@ -80,33 +82,6 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); } -#ifdef CONFIG_USB_EHCI_MX5 -int board_ehci_hcd_init(int port) -{ - if (port == 0) { - /* USB OTG PWRON */ - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, - PAD_CTL_PKE | - PAD_CTL_DSE_HIGH)); - gpio_direction_output(IMX_GPIO_NR(1, 4), 0); - - /* USB OTG Over Current */ - imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13); - } else if (port == 1) { - /* USB Host PWRON */ - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, - PAD_CTL_PKE | - PAD_CTL_DSE_HIGH)); - gpio_direction_output(IMX_GPIO_NR(1, 2), 0); - - /* USB Host Over Current */ - imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC); - } - - return 0; -} -#endif - static void setup_iomux_fec(void) { static const iomux_v3_cfg_t fec_pads[] = { @@ -150,44 +125,6 @@ static void setup_iomux_fec(void) imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); } -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg = { - MMC_SDHC1_BASE_ADDR, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1); - gpio_direction_input(IMX_GPIO_NR(1, 1)); - - return !gpio_get_value(IMX_GPIO_NR(1, 1)); -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) - -int board_mmc_init(bd_t *bis) -{ - static const iomux_v3_cfg_t sd1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), - }; - - esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); - - return fsl_esdhc_initialize(bis, &esdhc_cfg); -} -#endif - -#ifdef CONFIG_VIDEO static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk) { static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; @@ -215,6 +152,8 @@ static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk) static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev) { + gpio_request(IMX_GPIO_NR(6, 0), "LCD"); + /* For ETM0430G0DH6 model, this must be enabled before the clock. */ gpio_direction_output(IMX_GPIO_NR(6, 0), 1); @@ -227,6 +166,8 @@ static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev) static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev) { + gpio_request(IMX_GPIO_NR(6, 0), "LCD"); + /* * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 . @@ -330,7 +271,6 @@ struct display_info_t const displays[] = { }; size_t display_count = ARRAY_SIZE(displays); -#endif #ifdef CONFIG_SPLASH_SCREEN static struct splash_location default_splash_locations[] = { @@ -349,6 +289,50 @@ int splash_screen_prepare(void) } #endif +int board_late_init(void) +{ +#if defined(CONFIG_VIDEO_IPUV3) + struct udevice *dev; + int xpos, ypos, ret; + char *s; + void *dst; + ulong addr, len; + + splash_get_pos(&xpos, &ypos); + + s = env_get("splashimage"); + if (!s) + return 0; + + addr = simple_strtoul(s, NULL, 16); + dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE); + if (!dst) + return -ENOMEM; + + ret = splash_screen_prepare(); + if (ret < 0) + return ret; + + len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE; + ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2, + (uchar *)addr, &len); + if (ret) { + printf("Error: no valid bmp or bmp.gz image at %lx\n", addr); + free(dst); + return ret; + } + + ret = uclass_get_device(UCLASS_VIDEO, 0, &dev); + if (ret) + return ret; + + ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true); + if (ret) + return ret; +#endif + return 0; +} + #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) @@ -424,6 +408,8 @@ static void m53_set_clock(void) const u32 dramclk = 400; u32 cpuclk; + gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK"); + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, PAD_CTL_DSE_HIGH | PAD_CTL_PKE)); gpio_direction_input(IMX_GPIO_NR(4, 0)); diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 2ee6e462a6..c661d2e06a 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -4,3 +4,9 @@ S: Maintained F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig + +ROCK64-RK3328 +M: Matwey V. Kornilov <matwey.kornilov@gmail.com> +S: Maintained +F: configs/rock64-rk3328_defconfig +F: arch/arm/dts/rk3328-rock64-u-boot.dtsi diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index bf2ad98c47..eb1b832274 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -6,46 +6,14 @@ #include <common.h> #include <dm.h> #include <dm/pinctrl.h> -#include <dm/uclass-internal.h> #include <asm/arch-rockchip/periph.h> #include <power/regulator.h> -#include <spl.h> int board_init(void) { - struct udevice *pinctrl, *regulator; + struct udevice *regulator; int ret; - /* - * The PWM do not have decicated interrupt number in dts and can - * not get periph_id by pinctrl framework, so let's init them here. - * The PWM2 and PWM3 are for pwm regulater. - */ - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto out; - } - - /* Enable pwm0 for panel backlight */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM0); - if (ret) { - debug("%s PWM0 pinctrl init fail! (ret=%d)\n", __func__, ret); - goto out; - } - - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2); - if (ret) { - debug("%s PWM2 pinctrl init fail!\n", __func__); - goto out; - } - - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM3); - if (ret) { - debug("%s PWM3 pinctrl init fail!\n", __func__); - goto out; - } - ret = regulators_enable_boot_on(false); if (ret) debug("%s: Cannot enable boot on regulator\n", __func__); @@ -65,30 +33,3 @@ int board_init(void) out: return 0; } - -void spl_board_init(void) -{ - struct udevice *pinctrl; - int ret; - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - goto err; - } - - preloader_console_init(); - return; -err: - printf("%s: Error %d\n", __func__, ret); - - /* No way to report error here */ - hang(); -} diff --git a/board/technexion/pico-imx7d/README b/board/technexion/pico-imx7d/README index f21d8301cb..6aa0d25af5 100644 --- a/board/technexion/pico-imx7d/README +++ b/board/technexion/pico-imx7d/README @@ -11,7 +11,7 @@ $ make mrproper $ make pico-imx7d_defconfig $ make -This generates the SPL and u-boot.img binaries. +This generates the SPL and u-boot-dtb.img binaries. 1. Loading U-Boot via USB Serial Download Protocol @@ -32,15 +32,15 @@ to use an externally powered USB hub between the board and the host computer. Open a terminal program such as minicom. -Copy SPL and u-boot.img to the imx_usb_loader folder. +Copy SPL and u-boot-dtb.img to the imx_usb_loader folder. Load the SPL binary via USB: $ sudo ./imx_usb SPL -Load the u-boot.img binary via USB: +Load the u-boot-dtb.img binary via USB: -$ sudo ./imx_usb u-boot.img +$ sudo ./imx_usb u-boot-dtb.img Then U-Boot starts and its messages appear in the console program. @@ -55,11 +55,11 @@ Run the DFU agent so we can flash the new images using dfu-util tool: => dfu 0 mmc 0 -Flash SPL and u-boot.img into the eMMC running the following commands on a PC: +Flash SPL and u-boot-dtb.img into the eMMC running the following commands on a PC: $ sudo dfu-util -D SPL -a spl -$ sudo dfu-util -D u-boot.img -a u-boot +$ sudo dfu-util -D u-boot-dtb.img -a u-boot Remove power from the pico board. diff --git a/board/theobroma-systems/puma_rk3399/README b/board/theobroma-systems/puma_rk3399/README index f67dfb451f..9b31b0b379 100644 --- a/board/theobroma-systems/puma_rk3399/README +++ b/board/theobroma-systems/puma_rk3399/README @@ -60,7 +60,7 @@ Creating a SPL image for SD-Card/eMMC Creating a SPL image for SPI-NOR > tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin spl_nor.img Create the FIT image containing U-Boot proper, ATF, M0 Firmware, devicetree - > make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb + > make CROSS_COMPILE=aarch64-linux-gnu- Flash the image =============== diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its deleted file mode 100644 index 530f059f3d..0000000000 --- a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR X11 */ -/* - * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH - * - * Minimal dts for a SPL FIT image payload. - */ - -/dts-v1/; - -/ { - description = "FIT image with U-Boot proper, ATF bl31, M0 Firmware, DTB"; - #address-cells = <1>; - - images { - uboot { - description = "U-Boot (64-bit)"; - data = /incbin/("../../../u-boot-nodtb.bin"); - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <0x00200000>; - }; - atf { - description = "ARM Trusted Firmware"; - data = /incbin/("../../../bl31-rk3399.bin"); - type = "firmware"; - arch = "arm64"; - os = "arm-trusted-firmware"; - compression = "none"; - load = <0x1000>; - entry = <0x1000>; - }; - pmu { - description = "Cortex-M0 firmware"; - data = /incbin/("../../../rk3399m0.bin"); - type = "pmu-firmware"; - compression = "none"; - load = <0x180000>; - }; - fdt { - description = "RK3399-Q7 (Puma) flat device-tree"; - data = /incbin/("../../../u-boot.dtb"); - type = "flat_dt"; - compression = "none"; - }; - }; - - configurations { - default = "conf"; - conf { - description = "Theobroma Systems RK3399-Q7 (Puma) SoM"; - firmware = "atf"; - loadables = "uboot", "pmu"; - fdt = "fdt"; - }; - }; -}; diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.sh b/board/theobroma-systems/puma_rk3399/fit_spl_atf.sh new file mode 100755 index 0000000000..420e7daf4c --- /dev/null +++ b/board/theobroma-systems/puma_rk3399/fit_spl_atf.sh @@ -0,0 +1,94 @@ +#!/bin/sh +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> +# +# Based on the board/sunxi/mksunxi_fit_atf.sh +# +# Script to generate FIT image source for 64-bit puma boards with +# U-Boot proper, ATF, PMU firmware and devicetree. +# +# usage: $0 <dt_name> [<dt_name> [<dt_name] ...] + +[ -z "$BL31" ] && BL31="bl31.bin" + +if [ ! -f $BL31 ]; then + echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2 + echo "Please read Building section in doc/README.rockchip" >&2 + BL31=/dev/null +fi + +[ -z "$PMUM0" ] && PMUM0="rk3399m0.bin" + +if [ ! -f $PMUM0 ]; then + echo "WARNING: PMUM0 file $PMUM0 NOT found, resulting binary is non-functional" >&2 + echo "Please read Building section in doc/README.rockchip" >&2 + PMUM0=/dev/null +fi + +cat << __HEADER_EOF +/* SPDX-License-Identifier: GPL-2.0+ OR X11 */ +/* + * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH + * + * Minimal dts for a SPL FIT image payload. + */ + +/dts-v1/; + +/ { + description = "FIT image with U-Boot proper, ATF bl31, M0 Firmware, DTB"; + #address-cells = <1>; + + images { + uboot { + description = "U-Boot (64-bit)"; + data = /incbin/("u-boot-nodtb.bin"); + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <0x4a000000>; + }; + atf { + description = "ARM Trusted Firmware"; + data = /incbin/("$BL31"); + type = "firmware"; + arch = "arm64"; + os = "arm-trusted-firmware"; + compression = "none"; + load = <0x1000>; + entry = <0x1000>; + }; + pmu { + description = "Cortex-M0 firmware"; + data = /incbin/("$PMUM0"); + type = "pmu-firmware"; + compression = "none"; + load = <0x180000>; + }; + fdt { + description = "RK3399-Q7 (Puma) flat device-tree"; + data = /incbin/("u-boot.dtb"); + type = "flat_dt"; + compression = "none"; + }; +__HEADER_EOF + +cat << __CONF_HEADER_EOF + }; + + configurations { + default = "conf"; + conf { + description = "Theobroma Systems RK3399-Q7 (Puma) SoM"; + firmware = "atf"; + loadables = "uboot", "pmu"; + fdt = "fdt"; + }; +__CONF_HEADER_EOF + +cat << __ITS_EOF + }; +}; +__ITS_EOF diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index c6b509c109..251cd2d566 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -13,10 +13,8 @@ #include <dm/pinctrl.h> #include <dm/uclass-internal.h> #include <asm/io.h> -#include <asm/gpio.h> #include <asm/setup.h> #include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3399.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/periph.h> @@ -38,62 +36,6 @@ int board_init(void) return 0; } -static void rk3399_force_power_on_reset(void) -{ - ofnode node; - struct gpio_desc sysreset_gpio; - - debug("%s: trying to force a power-on reset\n", __func__); - - node = ofnode_path("/config"); - if (!ofnode_valid(node)) { - debug("%s: no /config node?\n", __func__); - return; - } - - if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, - &sysreset_gpio, GPIOD_IS_OUT)) { - debug("%s: could not find a /config/sysreset-gpio\n", __func__); - return; - } - - dm_gpio_set_value(&sysreset_gpio, 1); -} - -void spl_board_init(void) -{ - int ret; - struct rk3399_cru *cru = rockchip_get_cru(); - - /* - * The RK3399 resets only 'almost all logic' (see also in the TRM - * "3.9.4 Global software reset"), when issuing a software reset. - * This may cause issues during boot-up for some configurations of - * the application software stack. - * - * To work around this, we test whether the last reset reason was - * a power-on reset and (if not) issue an overtemp-reset to reset - * the entire module. - * - * While this was previously fixed by modifying the various places - * that could generate a software reset (e.g. U-Boot's sysreset - * driver, the ATF or Linux), we now have it here to ensure that - * we no longer have to track this through the various components. - */ - if (cru->glb_rst_st != 0) - rk3399_force_power_on_reset(); - - /* - * Turning the eMMC and SPI back on (if disabled via the Qseven - * BIOS_ENABLE) signal is done through a always-on regulator). - */ - ret = regulators_enable_boot_on(false); - if (ret) - debug("%s: Cannot enable boot on regulator\n", __func__); - - preloader_console_init(); -} - static void setup_macaddr(void) { #if CONFIG_IS_ENABLED(CMD_NET) diff --git a/board/vamrs/rock960_rk3399/README b/board/vamrs/rock960_rk3399/README index d14399090e..c5c675c4ea 100644 --- a/board/vamrs/rock960_rk3399/README +++ b/board/vamrs/rock960_rk3399/README @@ -61,7 +61,6 @@ Compile the U-Boot > export CROSS_COMPILE=aarch64-linux-gnu- > make rock960-rk3399_defconfig > make - > make u-boot.itb Compile the rkdeveloptool ========================= diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c index 0f5ef3a09a..2eb7120e84 100644 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -5,11 +5,7 @@ #include <common.h> #include <dm.h> -#include <dm/pinctrl.h> -#include <dm/uclass-internal.h> -#include <asm/arch-rockchip/periph.h> #include <power/regulator.h> -#include <spl.h> int board_init(void) { @@ -21,30 +17,3 @@ int board_init(void) return 0; } - -void spl_board_init(void) -{ - struct udevice *pinctrl; - int ret; - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - goto err; - } - - preloader_console_init(); - return; -err: - printf("%s: Error %d\n", __func__, ret); - - /* No way to report error here */ - hang(); -} diff --git a/common/spl/spl_sdp.c b/common/spl/spl_sdp.c index 7fc4404971..806bf1327e 100644 --- a/common/spl/spl_sdp.c +++ b/common/spl/spl_sdp.c @@ -29,10 +29,14 @@ static int spl_sdp_load_image(struct spl_image_info *spl_image, return -ENODEV; } - /* This command typically does not return but jumps to an image */ - sdp_handle(controller_index); - pr_err("SDP ended\n"); + /* + * This command either loads a legacy image, jumps and never returns, + * or it loads a FIT image and returns it to be handled by the SPL + * code. + */ + ret = spl_sdp_handle(controller_index, spl_image); + debug("SDP ended\n"); - return -EINVAL; + return ret; } SPL_LOAD_IMAGE_METHOD("USB SDP", 0, BOOT_DEVICE_BOARD, spl_sdp_load_image); diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index aff9c32362..92d6817ad5 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -1,7 +1,10 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3328=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -19,11 +22,15 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1 diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 0e5fa01fde..5a1fbf5298 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x71000000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_TARGET_M53MENLO=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 @@ -17,9 +18,8 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/menlo/m53menlo/imximage.cfg" CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttymxc0,115200" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_VERSION_VARIABLE=y +CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_TEXT_BASE=0x70008000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_NAND_SUPPORT=y @@ -27,11 +27,14 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -48,27 +51,37 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(u-boot),512k(env1),512k(env2),-(ubi)" CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx53-m53menlo" CONFIG_ENV_IS_IN_NAND=y +CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_NAND=y CONFIG_NAND_MXC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX5=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_RTC_M41T62=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_MX5=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set CONFIG_IMX_WATCHDOG=y CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 03f0bfdb59..5cb2273a15 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -15,13 +15,12 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y -CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/puma_rk3399/fit_spl_atf.its" +CONFIG_SPL_FIT_GENERATOR="board/theobroma-systems/puma_rk3399/fit_spl_atf.sh" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 -CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig new file mode 100644 index 0000000000..6529dedfb6 --- /dev/null +++ b/configs/rock64-rk3328_defconfig @@ -0,0 +1,91 @@ +CONFIG_SMBIOS_MANUFACTURER="pine64" +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3328=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/doc/README.rockchip b/doc/README.rockchip index 264f7e4994..02e2497b15 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -48,9 +48,10 @@ Two RK3036 boards are supported: - EVB RK3036 - use evb-rk3036 configuration - Kylin - use kylin_rk3036 configuration -One RK3328 board is supported: +Two RK3328 board are supported: - - EVB RK3328 + - EVB RK3328 - use evb-rk3328_defconfig + - Pine64 Rock64 board - use rock64-rk3328_defconfig Size RK3399 boards are supported (aarch64): @@ -103,7 +104,6 @@ For example: => cd /path/to/u-boot => make nanopi-neo4-rk3399_defconfig => make - => make u-boot.itb - Get the rkbin @@ -137,8 +137,8 @@ For example: => cd arm-trusted-firmware => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 - (copy bl31.bin into U-Boot root dir) - => cp build/rk3399/release/bl31/bl31.bin /path/to/u-boot/bl31-rk3399.bin + (export bl31.bin) + => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.bin For rest of rk3399 boards. @@ -149,8 +149,8 @@ For example: => make realclean => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 - (copy bl31.elf into U-Boot root dir) - => cp build/rk3399/release/bl31/bl31.elf /path/to/u-boot + (export bl31.elf) + => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf - Compile PMU M0 firmware @@ -162,15 +162,14 @@ For example: (export cross compiler path for Cortex-M0 PMU) => make CROSS_COMPILE=arm-cortex_m0-eabi- - (copy rk3399m0.bin into U-Boot root dir) - => cp rk3399m0.bin /path/to/u-boot + (export rk3399m0.bin) + => export PMUM0=/path/to/rk3399-cortex-m0/rk3399m0.bin - Compile U-Boot => cd /path/to/u-boot => make orangepi-rk3399_defconfig => make - => make u-boot.itb (Get spl/u-boot-spl-dtb.bin, u-boot.itb images and some boards would get spl/u-boot-spl.bin since it doesn't enable CONFIG_SPL_OF_CONTROL @@ -310,6 +309,31 @@ tools/mkimage -n rk3188 -T rksd -d spl/u-boot-spl.bin out truncate -s %2048 u-boot.bin cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 7C4E0304550509072D2C7B38170D1711' >> out +Booting from an SD card on Pine64 Rock64 (RK3328) +================================================= + +For Rock64 rk3328 board the following three parts are required: +TPL, SPL, and the u-boot image tree blob. While u-boot-spl.bin and +u-boot.itb are to be compiled as usual, TPL is currently not +implemented in u-boot, so you need to pick one from rkbin: + + - Get the rkbin + + => git clone https://github.com/rockchip-linux/rkbin.git + + - Create TPL/SPL image + + => tools/mkimage -n rk3328 -T rksd -d rkbin/bin/rk33/rk3328_ddr_333MHz_v1.16.bin idbloader.img + => cat spl/u-boot-spl.bin >> idbloader.img + + - Write TPL/SPL image at 64 sector + + => sudo dd if=idbloader.img of=/dev/mmcblk0 seek=64 + + - Write u-boot image tree blob at 16384 sector + + => sudo dd if=u-boot.itb of=/dev/mmcblk0 seek=16384 + Booting from an SD card on RK3399 ================================= diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index f2c99d4723..5efaa2f66b 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -28,6 +28,10 @@ static const int i2c4_muxvals[] = {1, 1}; static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17}; static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned spi0_pins[] = {56, 57, 58, 59}; +static const int spi0_muxvals[] = {0, 0, 0, 0}; +static const unsigned spi1_pins[] = {169, 170, 171, 172}; +static const int spi1_muxvals[] = {1, 1, 1, 1}; static const unsigned system_bus_pins[] = {1, 2, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17}; static const int system_bus_muxvals[] = {0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, @@ -58,6 +62,8 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c3), UNIPHIER_PINCTRL_GROUP(i2c4), UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(spi0), + UNIPHIER_PINCTRL_GROUP(spi1), UNIPHIER_PINCTRL_GROUP(system_bus), UNIPHIER_PINCTRL_GROUP(system_bus_cs1), UNIPHIER_PINCTRL_GROUP(uart0), @@ -77,6 +83,8 @@ static const char * const uniphier_ld11_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c3), UNIPHIER_PINMUX_FUNCTION(i2c4), UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(spi0), + UNIPHIER_PINMUX_FUNCTION(spi1), UNIPHIER_PINMUX_FUNCTION(system_bus), UNIPHIER_PINMUX_FUNCTION(uart0), UNIPHIER_PINMUX_FUNCTION(uart1), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index 8ec87f285e..d3c5833c99 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -43,6 +43,14 @@ static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned sd_pins[] = {10, 11, 12, 13, 14, 15, 16, 17}; static const int sd_muxvals[] = {3, 3, 3, 3, 3, 3, 3, 3}; /* No SDVOLC */ +static const unsigned spi0_pins[] = {56, 57, 58, 59}; +static const int spi0_muxvals[] = {0, 0, 0, 0}; +static const unsigned spi1_pins[] = {169, 170, 171, 172}; +static const int spi1_muxvals[] = {1, 1, 1, 1}; +static const unsigned spi2_pins[] = {86, 87, 88, 89}; +static const int spi2_muxvals[] = {1, 1, 1, 1}; +static const unsigned spi3_pins[] = {74, 75, 76, 77}; +static const int spi3_muxvals[] = {1, 1, 1, 1}; static const unsigned system_bus_pins[] = {1, 2, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17}; static const int system_bus_muxvals[] = {0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, @@ -77,6 +85,10 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c4), UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(spi0), + UNIPHIER_PINCTRL_GROUP(spi1), + UNIPHIER_PINCTRL_GROUP(spi2), + UNIPHIER_PINCTRL_GROUP(spi3), UNIPHIER_PINCTRL_GROUP(system_bus), UNIPHIER_PINCTRL_GROUP(system_bus_cs1), UNIPHIER_PINCTRL_GROUP(uart0), @@ -99,6 +111,10 @@ static const char * const uniphier_ld20_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c4), UNIPHIER_PINMUX_FUNCTION(nand), UNIPHIER_PINMUX_FUNCTION(sd), + UNIPHIER_PINMUX_FUNCTION(spi0), + UNIPHIER_PINMUX_FUNCTION(spi1), + UNIPHIER_PINMUX_FUNCTION(spi2), + UNIPHIER_PINMUX_FUNCTION(spi3), UNIPHIER_PINMUX_FUNCTION(system_bus), UNIPHIER_PINMUX_FUNCTION(uart0), UNIPHIER_PINMUX_FUNCTION(uart1), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c index c822bccbd1..bf1a9e9e98 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c @@ -37,6 +37,8 @@ static const unsigned nand_cs1_pins[] = {22, 23}; static const int nand_cs1_muxvals[] = {0, 0}; static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52}; static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned spi0_pins[] = {135, 136, 137, 138}; +static const int spi0_muxvals[] = {12, 12, 12, 12}; static const unsigned system_bus_pins[] = {16, 17, 18, 19, 20, 165, 166, 167, 168, 169, 170, 171, 172, 173}; static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, @@ -80,6 +82,7 @@ static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = { UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(nand_cs1), UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(spi0), UNIPHIER_PINCTRL_GROUP(system_bus), UNIPHIER_PINCTRL_GROUP(system_bus_cs0), UNIPHIER_PINCTRL_GROUP(system_bus_cs1), @@ -106,6 +109,7 @@ static const char * const uniphier_ld4_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c3), UNIPHIER_PINMUX_FUNCTION(nand), UNIPHIER_PINMUX_FUNCTION(sd), + UNIPHIER_PINMUX_FUNCTION(spi0), UNIPHIER_PINMUX_FUNCTION(system_bus), UNIPHIER_PINMUX_FUNCTION_SPL(uart0), UNIPHIER_PINMUX_FUNCTION_SPL(uart1), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c index 30d411694c..f22c046804 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c @@ -37,6 +37,10 @@ static const unsigned nand_cs1_pins[] = {37, 38}; static const int nand_cs1_muxvals[] = {0, 0}; static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55}; static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned spi0_pins[] = {199, 200, 201, 202}; +static const int spi0_muxvals[] = {8, 8, 8, 8}; +static const unsigned spi1_pins[] = {93, 94, 95, 96}; +static const int spi1_muxvals[] = {1, 1, 1, 1}; static const unsigned system_bus_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}; static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -84,6 +88,8 @@ static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = { UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(nand_cs1), UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(spi0), + UNIPHIER_PINCTRL_GROUP(spi1), UNIPHIER_PINCTRL_GROUP(system_bus), UNIPHIER_PINCTRL_GROUP(system_bus_cs1), UNIPHIER_PINCTRL_GROUP(system_bus_cs2), @@ -112,6 +118,8 @@ static const char * const uniphier_ld6b_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c3), UNIPHIER_PINMUX_FUNCTION(nand), UNIPHIER_PINMUX_FUNCTION(sd), + UNIPHIER_PINMUX_FUNCTION(spi0), + UNIPHIER_PINMUX_FUNCTION(spi1), UNIPHIER_PINMUX_FUNCTION(system_bus), UNIPHIER_PINMUX_FUNCTION_SPL(uart0), UNIPHIER_PINMUX_FUNCTION_SPL(uart1), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c index eb5978a166..8bae163a8e 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c @@ -50,6 +50,10 @@ static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326, 327}; static const int sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned spi0_pins[] = {199, 200, 201, 202}; +static const int spi0_muxvals[] = {11, 11, 11, 11}; +static const unsigned spi1_pins[] = {195, 196, 197, 198, 235, 238, 239}; +static const int spi1_muxvals[] = {11, 11, 11, 11, 11, 11, 11}; static const unsigned system_bus_pins[] = {25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38}; static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -103,6 +107,8 @@ static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = { UNIPHIER_PINCTRL_GROUP(nand_cs1), UNIPHIER_PINCTRL_GROUP(sd), UNIPHIER_PINCTRL_GROUP(sd1), + UNIPHIER_PINCTRL_GROUP(spi0), + UNIPHIER_PINCTRL_GROUP(spi1), UNIPHIER_PINCTRL_GROUP(system_bus), UNIPHIER_PINCTRL_GROUP(system_bus_cs0), UNIPHIER_PINCTRL_GROUP(system_bus_cs1), @@ -135,6 +141,8 @@ static const char * const uniphier_pro4_functions[] = { UNIPHIER_PINMUX_FUNCTION(nand), UNIPHIER_PINMUX_FUNCTION(sd), UNIPHIER_PINMUX_FUNCTION(sd1), + UNIPHIER_PINMUX_FUNCTION(spi0), + UNIPHIER_PINMUX_FUNCTION(spi1), UNIPHIER_PINMUX_FUNCTION(system_bus), UNIPHIER_PINMUX_FUNCTION_SPL(uart0), UNIPHIER_PINMUX_FUNCTION_SPL(uart1), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c index 685d8be80c..1f4931bcf0 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c @@ -37,6 +37,12 @@ static const unsigned nand_cs1_pins[] = {26, 27}; static const int nand_cs1_muxvals[] = {0, 0}; static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258}; static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned spi0_pins[] = {120, 121, 122, 123}; +static const int spi0_muxvals[] = {0, 0, 0, 0}; +static const unsigned spi1_pins[] = {134, 139, 85, 86}; +static const int spi1_muxvals[] = {1, 1, 1, 1}; +static const unsigned spi2_pins[] = {55, 56, 57, 58, 82, 83, 84}; +static const int spi2_muxvals[] = {0, 0, 0, 0, 1, 1, 1}; static const unsigned system_bus_pins[] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17}; static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -88,6 +94,9 @@ static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = { UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(nand_cs1), UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(spi0), + UNIPHIER_PINCTRL_GROUP(spi1), + UNIPHIER_PINCTRL_GROUP(spi2), UNIPHIER_PINCTRL_GROUP(system_bus), UNIPHIER_PINCTRL_GROUP(system_bus_cs0), UNIPHIER_PINCTRL_GROUP(system_bus_cs1), @@ -117,6 +126,9 @@ static const char * const uniphier_pro5_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c6), UNIPHIER_PINMUX_FUNCTION(nand), UNIPHIER_PINMUX_FUNCTION(sd), + UNIPHIER_PINMUX_FUNCTION(spi0), + UNIPHIER_PINMUX_FUNCTION(spi1), + UNIPHIER_PINMUX_FUNCTION(spi2), UNIPHIER_PINMUX_FUNCTION(system_bus), UNIPHIER_PINMUX_FUNCTION_SPL(uart0), UNIPHIER_PINMUX_FUNCTION_SPL(uart1), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index 8609f1b7a7..038a7dd7be 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -46,6 +46,10 @@ static const unsigned nand_cs1_pins[] = {37, 38}; static const int nand_cs1_muxvals[] = {8, 8}; static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55}; static const int sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8}; +static const unsigned spi0_pins[] = {199, 200, 201, 202}; +static const int spi0_muxvals[] = {8, 8, 8, 8}; +static const unsigned spi1_pins[] = {93, 94, 95, 96}; +static const int spi1_muxvals[] = {1, 1, 1, 1}; static const unsigned system_bus_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}; static const int system_bus_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, @@ -88,6 +92,8 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = { UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(nand_cs1), UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(spi0), + UNIPHIER_PINCTRL_GROUP(spi1), UNIPHIER_PINCTRL_GROUP(system_bus), UNIPHIER_PINCTRL_GROUP(system_bus_cs1), UNIPHIER_PINCTRL_GROUP_SPL(uart0), @@ -115,6 +121,8 @@ static const char * const uniphier_pxs2_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c6), UNIPHIER_PINMUX_FUNCTION(nand), UNIPHIER_PINMUX_FUNCTION(sd), + UNIPHIER_PINMUX_FUNCTION(spi0), + UNIPHIER_PINMUX_FUNCTION(spi1), UNIPHIER_PINMUX_FUNCTION(system_bus), UNIPHIER_PINMUX_FUNCTION_SPL(uart0), UNIPHIER_PINMUX_FUNCTION_SPL(uart1), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index 5b4a514103..452d76d721 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -41,6 +41,10 @@ static const unsigned nand_pins[] = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned sd_pins[] = {43, 44, 45, 46, 47, 48, 49, 50, 51}; static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned spi0_pins[] = {100, 101, 102, 103}; +static const int spi0_muxvals[] = {0, 0, 0, 0}; +static const unsigned spi1_pins[] = {112, 113, 114, 115}; +static const int spi1_muxvals[] = {2, 2, 2, 2}; static const unsigned system_bus_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}; static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -77,6 +81,8 @@ static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c3), UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(spi0), + UNIPHIER_PINCTRL_GROUP(spi1), UNIPHIER_PINCTRL_GROUP(system_bus), UNIPHIER_PINCTRL_GROUP(system_bus_cs1), UNIPHIER_PINCTRL_GROUP(uart0), @@ -101,6 +107,8 @@ static const char * const uniphier_pxs3_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c3), UNIPHIER_PINMUX_FUNCTION(nand), UNIPHIER_PINMUX_FUNCTION(sd), + UNIPHIER_PINMUX_FUNCTION(spi0), + UNIPHIER_PINMUX_FUNCTION(spi1), UNIPHIER_PINMUX_FUNCTION(system_bus), UNIPHIER_PINMUX_FUNCTION(uart0), UNIPHIER_PINMUX_FUNCTION(uart1), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c index c072fc5280..1e38ba16f9 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c @@ -37,6 +37,8 @@ static const unsigned nand_cs1_pins[] = {22, 23}; static const int nand_cs1_muxvals[] = {0, 0}; static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40}; static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned spi0_pins[] = {118, 119, 120, 121}; +static const int spi0_muxvals[] = {3, 3, 3, 3}; static const unsigned system_bus_pins[] = {136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149}; static const int system_bus_muxvals[] = {-1, -1, -1, -1, -1, -1, -1, -1, -1, @@ -78,6 +80,7 @@ static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = { UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(nand_cs1), UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(spi0), UNIPHIER_PINCTRL_GROUP(system_bus), UNIPHIER_PINCTRL_GROUP(system_bus_cs1), UNIPHIER_PINCTRL_GROUP(system_bus_cs2), @@ -103,6 +106,7 @@ static const char * const uniphier_sld8_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c3), UNIPHIER_PINMUX_FUNCTION(nand), UNIPHIER_PINMUX_FUNCTION(sd), + UNIPHIER_PINMUX_FUNCTION(spi0), UNIPHIER_PINMUX_FUNCTION(system_bus), UNIPHIER_PINMUX_FUNCTION_SPL(uart0), UNIPHIER_PINMUX_FUNCTION_SPL(uart1), diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index ae97ab2b49..fab7ce6f97 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -638,7 +638,20 @@ static u32 sdp_jump_imxheader(void *address) return 0; } -static void sdp_handle_in_ep(void) +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_SPL_LOAD_FIT +static ulong sdp_fit_read(struct spl_load_info *load, ulong sector, + ulong count, void *buf) +{ + debug("%s: sector %lx, count %lx, buf %lx\n", + __func__, sector, count, (ulong)buf); + memcpy(buf, (void *)(load->dev + sector), count); + return count; +} +#endif +#endif + +static void sdp_handle_in_ep(struct spl_image_info *spl_image) { u8 *data = sdp_func->in_req->buf; u32 status; @@ -690,10 +703,25 @@ static void sdp_handle_in_ep(void) /* If imx header fails, try some U-Boot specific headers */ if (status) { #ifdef CONFIG_SPL_BUILD + image_header_t *header = + sdp_ptr(sdp_func->jmp_address); +#ifdef CONFIG_SPL_LOAD_FIT + if (image_get_magic(header) == FDT_MAGIC) { + struct spl_load_info load; + + debug("Found FIT\n"); + load.dev = header; + load.bl_len = 1; + load.read = sdp_fit_read; + spl_load_simple_fit(spl_image, &load, 0, + header); + + return; + } +#endif /* In SPL, allow jumps to U-Boot images */ struct spl_image_info spl_image = {}; - spl_parse_image_header(&spl_image, - (struct image_header *)sdp_func->jmp_address); + spl_parse_image_header(&spl_image, header); jump_to_image_no_args(&spl_image); #else /* In U-Boot, allow jumps to scripts */ @@ -715,19 +743,32 @@ static void sdp_handle_in_ep(void) }; } -void sdp_handle(int controller_index) +#ifndef CONFIG_SPL_BUILD +int sdp_handle(int controller_index) +#else +int spl_sdp_handle(int controller_index, struct spl_image_info *spl_image) +#endif { printf("SDP: handle requests...\n"); while (1) { if (ctrlc()) { puts("\rCTRL+C - Operation aborted.\n"); - return; + return -EINVAL; } +#ifdef CONFIG_SPL_BUILD + if (spl_image->flags & SPL_FIT_FOUND) + return 0; +#endif + WATCHDOG_RESET(); usb_gadget_handle_interrupts(controller_index); - sdp_handle_in_ep(); +#ifdef CONFIG_SPL_BUILD + sdp_handle_in_ep(spl_image); +#else + sdp_handle_in_ep(NULL); +#endif } } diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 4b0a3fb26b..db37fa7b73 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -58,6 +58,7 @@ #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_ETHPRIME "FEC" +#define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */ #define CONFIG_FEC_MXC_PHYADDR 6 #define CONFIG_TFTP_TSIZE @@ -121,8 +122,8 @@ "imx6q-apalis-cam-eval.dtb fat 0 1" #define EMMC_BOOTCMD \ - "set_emmcargs emmcargs ip=off root=PARTUUID=${uuid} ro,noatime " \ - "rootfstype=ext4 rootwait\0" \ + "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} " \ + "ro,noatime rootfstype=ext4 rootwait\0" \ "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \ "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ "${vidargs}; echo Booting from internal eMMC chip...; " \ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index fc0b1f480c..7b68c1c0a1 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -136,7 +136,6 @@ /* * LCD */ -#ifdef CONFIG_VIDEO #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SPLASH_SCREEN @@ -145,7 +144,6 @@ #define CONFIG_BMP_16BPP #define CONFIG_VIDEO_LOGO #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) -#endif /* LVDS display */ #define CONFIG_SYS_LDB_CLOCK 33260000 @@ -205,6 +203,8 @@ "splashfile=boot/usplash.bmp.gz\0" \ "splashimage=0x88000000\0" \ "splashpos=m,m\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ "addcons=" \ "setenv bootargs ${bootargs} " \ "console=${consdev},${baudrate}\0" \ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 9a3b3b1e80..91015402ef 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -79,7 +79,6 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ "image=zImage\0" \ "splashpos=m,m\0" \ "console=ttymxc4\0" \ diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 71aad7029a..2a81c803b6 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -16,6 +16,10 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x2000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ diff --git a/include/efi_api.h b/include/efi_api.h index 4de5d208f5..a36ececc81 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -242,7 +242,8 @@ struct efi_runtime_services { unsigned long descriptor_size, uint32_t descriptor_version, struct efi_mem_desc *virtmap); - efi_status_t (*convert_pointer)(unsigned long dbg, void **address); + efi_status_t (EFIAPI *convert_pointer)( + efi_uintn_t debug_disposition, void **address); efi_status_t (EFIAPI *get_variable)(u16 *variable_name, const efi_guid_t *vendor, u32 *attributes, diff --git a/include/sdp.h b/include/sdp.h index f6252d027f..6ac64fb1f3 100644 --- a/include/sdp.h +++ b/include/sdp.h @@ -10,6 +10,13 @@ #define __SDP_H_ int sdp_init(int controller_index); -void sdp_handle(int controller_index); + +#ifdef CONFIG_SPL_BUILD +#include <spl.h> + +int spl_sdp_handle(int controller_index, struct spl_image_info *spl_image); +#else +int sdp_handle(int controller_index); +#endif #endif /* __SDP_H_ */ |